Load/Store Instructions All data transfers between registers and memory use the load and store class of instructions.. All memory addresses are generated using a base register pointer, s
Trang 1Chapter 11
value in that field may produce unpredictable results.1 Another feature of the compare instructions
is that they will always set the flags, so the state of the S bit is ignored
The next group of data processing instructions is the very powerful set of multiplication tions There are size multiplication instructions, as shown in the following table:
MUL Multiply two 32-bit numbers, produce a 32-bit result: Rd = Rm * Rs MUL{cond}{S} Rd, Rm, Rn
rd number for a 32-bit result:
UMULL Multiply two unsigned 32-bit numbers, produce an unsigned 64-bit resulted in
UMLAL
Multiply two unsigned 32-bit numbers and
add an unsigned 64-bit number in two
registers to produce an unsigned 64-bit
resulted in two registers:
[RdHi][RdLo] = [RdHi][RdLo] + Rm * Rs
UMLAL{cond}{S} RdLo,RdHi,Rm,Rs
SMULL Multiply two signed 32-bit numbers, pro- duce a signed 64-bit result in two registers SMULL{cond}{S} RdLo,RdHi,Rm,Rs
SMLAL
Multiply two signed 32-bit numbers and
add a signed 64-bit number in two
regis-ters to produce a signed 64-bit resulted in
to multiplications
2 Load/Store Instructions
All data transfers between registers and memory use the load and store class of instructions All memory addresses are generated using a base register pointer, summed with an additional immediate offset value, register values or scaled register values In addition, the calculated memory address pointer may be used without updating the base register pointer with the new address value Finally, the address calculation may take place before or after the address is used in the instruction The load/store operations must also deal with the size and type of the operands, since bytes and half-words are also permitted
1 There’s a wonderful story about the intrepid hobbyists/pioneers of the PC industry It became sort of a cottage try to try to figure out what the unimplemented op-codes did In other words, “What would happen if the SBZ field was set to 011?” Sometimes some very interesting undocumented instructions were discovered and were actually designed into commercial products Unfortunately, when the CPU manufacturer revised the chip, they often changed the codes for unsupported instruction codes, figuring, “Who would use them?” You can imagine the uproar when products started failing when a new batch of processors was plugged in.
Trang 2indus-The ARM Architecture
Since we’ve already discussed much of the operation of the load/store instructions as part of our discussion of the addressing modes that they use, we’ll just take a brief look at the format of the load/store instruction word
The load register instruction may take any of the following forms:
LDRH Load a register from an 16-bit memory half-word LDRH{cond} Rn,<address mode>
LDRSB Load a register from an 8-bit signed memory byte LDRSB{cond} Rn,<address mode>
LDRSH Load a register from a 16-bit signed memory half-word LDRSH{cond} Rn,<address mode>
Special mnemonics must be used for the signed byte and half-word data types because these ues are sign extended to 32-bits when the register is loaded from memory No special instruction is necessary for a 32-bit value in memory because it is the native data size of the ARM architecture Figure 11.7 shows the format
val-for the load/store instructions
for word or unsigned bytes
Note that the load and stores
are almost identical, the
dif-ference being the state of the
L bit in bit position 20 The
instruction format is slightly
different for half-words and
signed bytes
The meanings of the common fields are as follows:
• Bits 31:28: Conditional execution fields.
• Bits 27:25: Fixed.
• Bit 24: For pre-index mode, P = 1 The offset is applied to the base register and the sum of
the base register and the offset is used as the memory load/store address For post-index mode P = 0 The base register is used as the memory pointer and then the sum of the offset and base register value is written back to the base register
• Bit 23: The When U = 1 the offset is added to the base register value to form the memory
address If U = 0 the offset is subtracted from the base register value
• Bit 22: When B = 1 the memory access is an unsigned byte If B = 0 the access is a 32-bit
word
• Bit 21: If the P bit = 1, then the W bit determines if the calculated memory address value
is written back to update the base register If W = 0 the base register is not updated When the P bit = 0 and W = 1 the current access is treated as a user mode access When the
Figure 11.7: Format for the ARM word or unsigned byte load/store instructions.
Immediate offset/Index COND 0 1 0 P U B W L Rn Rd 12-bit offset
Register offset/Index COND 0 1 1 P U B W L Rn Rd 0 0 0 0 0 0 0 0 Rm
Scaled register offset/Index COND 0 1 1 P U B W L Rn Rd Immediate Shift Shift 0 Rm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Trang 3Chapter 11
• Bit 20: If L = 1 then the operation is a memory load If L = 0 then it is a memory store
operation
• Bits 19:16: Base register pointer.
• Bits 15:12: Destination register for load operation or source register for store operation.
• Bits 11:0: Addressing mode dependent.
Let’s look at some examples of memory load and store operations
LDRSH r6, [r0, -r2 ]!
Load register r5 with the signed half-word pointed to by r0 – r2 Update r0 with com- puted address value after the memory load operation.
0xE13060F2
LDRNE r0,[r9,#-12]
Conditionally execute if the Zero Flag = 0
Load register r0 with the word value pointed
to by register r3 minus 12 bytes The value in r9 is not changed.
0x1519000C
LDRVCB r11,[r4],r2,LSL #4
Conditionally execute if the Overflow Flag =
0 Load register r11 with the unsigned byte pointed to by r4 Then update r4 so that r4 = r4 + r2*16
0x76D4B202
LDR R8,[PC,r5]
Load register r8 with the word value pointed
to by the sum of the current value of the
Conditionally execute if the Carry Flag = 0
Store the half-word in register r11 in the memory location pointed to by r2 – 10 r2 is unchanged.
0x3142B0BA
STREQ r0,[r4,r5,lsr #7]
Conditionally execute if the Zero Flag = 1
Store the word in r0 to the memory address pointed to by r4 + the result of r5 shifted right 7 bit positions r5 is unchanged.
0x078403A5
STRB r6,[r4],r3
Store the byte in register r6 to the memory address pointed to by r4 Then add the con- tents of r3 to r4 and update r4 with the sum 0xE6C46003
STRPLH r11,[r9,#-2]!
Conditionally execute if the Negative Flag
= 0 Store the half word contents of r11 to the memory address pointed to by r9 – 2
Update r9 with the new address
Trang 4The ARM Architecture
The general form of the load
multiple registers and store
multiple registers is shown in
Figure 11.8 Each bit in the bit
field 15:0 corresponds to a register to be loaded or stored A 1 in the bit position indicates that the corresponding register is to be loaded or stored The lowest numbered register is stored at the low-est memory address and the highest numbered register is stored at the highest memory address The definition of the bit fields is as follows:
• Bits 31:28: Conditional execution fields.
• Bits 27:25: Fixed
• Bit 24: When P = 1 the address is incremented or decremented prior to the memory access
(pre-indexing) When P = 0 the current memory pointer address is used first, and then the memory pointer is changed (post-indexing)
• Bit 23: When U = 1 the memory addresses are incremented with each transfer When
U = 0 the memory addresses are decremented
• Bit 22: When S = 1 and the LDM instruction is loading the program counter (r15), then
the current program status register (CPSR) will be loaded from the saved program status register (SPSR) If the load operation does not involve r15 and for all STM instructions, the S bit indicates that when the processor is in privileged mode, the standard user mode registers are transferred and not the registers of the current mode The state of the S bit is set by appending the up-carat symbol, ‘^’, to the end of the instruction
• Bit 21: If W=1, the pointer register will be permanently updated after the multiple
regis-ter transfer occurs Since each data transfer is 4 bytes long, the memory poinregis-ter will be updates by 4 times the number of registers transferred If W = 0, the register will not be updated
• Bit 20: If L = 1 then a memory to register (load) operation will take place If L = 0 then a
register to memory (store) operation will occur
• Bits 19:16: Denotes the pointer register.
• Bits 15:0: Register list.
The general syntax of the load multiple or store multiple instructions is shown below The terms in braces are optional
Here, XY represents:
• IA: Increment After
• IB: Increment Before
• DA: Decrement After
• DB: Decrement Before
The following are two representative forms of the load and store multiple instructions
Figure 11.8: Format for the ARM multiple register load/store operation.
COND 1 0 0 P U S W L Rn Register List
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Trang 5STMNEIA r0,{r2-r9}
Conditionally execute this instruction if the Zero Flag = 0 Store the contents of registers r2 through r9 in the block of memory pointed to by r0 Store register r2 and then increment r0 for the next store operation After the multiple data transfer is completed the value of r0 is restored to its previous value.
The corresponding form of the swap instruction is:
The question still remains, “Why have the swap instruction at all?” The answer is that the swap
instruction is an atomic operation An atomic operation cannot be interrupted Most instructions
are atomic That is, once an instruction starts and the processor receives an external interrupt, the instruction must complete before the interrupt can be taken care of In the above example of the memory to register exchange operation, we need to use 3 instructions to complete the data trans-fer These 3 instructions are not atomic because an interrupt could cause a gap to occur in the exchange of data If the interrupt also changed the data in these registers or memory, then the data exchange might become corrupted The swap instruction is a way to lock the bus so that it must complete before another event can take control
Trang 6The ARM Architecture
3 Branch Instructions
There are two forms of the branch instruction; branch (B) and branch with link (BL) The
instruc-tions are similar with the exception that the branch with link instruction automatically saves the address of the next instruction after the BL instruction in the link register, r14 This is just a sub-routine call To return from the subroutine, you just copy the link register to the program counter:
The range of the branch
in-struction is +/- 32 megabytes
Just like the 68K, the branch
instruction in the ARM
archi-tecture is a pc-relative displacement The displacement is added or subtracted from the current value of the pc and the pc is reloaded with this new value, causing a program branch to occur The form of the branch instruction is shown in Figure 11.9
The branch address is calculated as follows:
1 The 24 bit offset value is sign-extended to 32 bits
2 The result is shifted left by 2 bit positions (multiplied by 4) to provide a word-aligned displacement value, or effectively, a 26-bit word address
3 The displacement is added to the program counter and the result is stored back into the pc
4 Software Interrupt Instructions
The software interrupt instruction is designed to allow application code to change the program execution context through a vector stored in memory This instruction is similar to the TRAP instruction of the 68K and the INT instruction of the 8086 In general, the software interrupt (SWI)
is used by an application to make a call to operating system services
Since the SWI instruction is used to change context, it must also save the current processor context
so that it can return after the interrupt The action of the SWI is as follows:
1 Save the address of the instruction after the SWI instruction in register r14_svc
2 Save the CPSR in SPSR_svc
Enter supervisor mode and disable the normal interrupts, but not the fast interrupt request
3 Load the PC with address 0x00000008 and execute the instruction there
Rather than use the exception vector table as an indirect address to the start of the software rupt service routine, the vector table location contains space for one instruction, which is then used
inter-as a branch to the start of the code This may seem strange if you think about the 68K’s vector table organization, but with the ARM architecture it really doesn’t matter Since all instructions are one word long, you don’t need to use an indirect pointer to get to the start of the ISR code Motorola must use a vector because an unconditional jump instruction would take up too much space How-ever, since an ARM instruction fits into the same space as an address, either method would work.The software interrupt instruction also contains a 24-bit immediate operand field that may be used to pass parameters to the interrupt service routine Thus, instead of using multiple software interrupt vectors, a single vector is used, but information about the type of interrupt service being
Figure 11.9: Format for the ARM branch and branch with link instructions
COND 1 0 1 L 24-bit offset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Trang 7Chapter 11
5 Program Status Register Instructions
The last ARM instruction category that will look at contains two instructions that implement a load or store operation between the CPSR or SPSR registers and the general purpose registers The syntax for the instructions is as follows:
MRS{condition} Rd, <cpsr or spsr>
MSR{condition} <cpsr or spsr>_<fields>, Rm MSR{condition} <cpsr or spsr>_<fields>, #Immediate
The MRS instruction moves the current value of the CPSR or SPSR to a general purpose register The MSR instruction moves the contents of a general purpose register or an immediate value into the CPSR or SPSR
Some comments on the status register instructions This instruction will be ignored if the sor is in user mode and the instruction attempts to modify any other field besides the Flag Field It must be in one of the privileged modes for this instruction to be executable because the program status registers may only be modified when the processor is in one of the privileged modes
proces-The values for the field variables are as follows:
• _C: The Control Field represents bits 0 through 7 of the program status register This is
further subdivided as:
– Bits 0:4: Processor mode
– Bit 5: Enable Thumb Mode
– Bit 6: Enable Fast Interrupt Request Mode
– Bit 7: Enable Interrupt Request Mode
• _X: The Extension Field represents bits 8:15 Currently this field is not used, but is
re-served by ARM for future expansion These bits should not be modified
• _S: The Status Field represents bits 16:23 Currently this field is not used, but is reserved
by ARM for future expansion These bits should not be modified
• _F: The flag field represents bits 24:31 This field is further subdivided as:
– Bit 28: V bit- Overflow Flag
– Bit 29: C bit- Carry Flag
– Bit 30: Z bit- Zero Flag
– Bit 31: N bit- Negative Flag
The immediate operand can only modify the bits in the Flag Field Also, in order not to tently modify bits in the program status register that should not be modified, the program status register should be modified using the following three steps:
inadver-1 Copy the contents of the PSR into a general purpose register using the MRS instruction,
2 Modify the appropriate bits in the general purpose register,
3 Copy the general purpose register back into the PSR using the MSR instruction
The following instruction sequence enables the FIR mode
Trang 8The ARM Architecture
The field bits are logically
OR’ed together, so that,
for example, you may use
cxsf_cpsr to modify all the
fields of the cpsr
The formats of the MSR
and MRS instructions are
shown in Figure 11.10 If
the R bit = 1 the program
status register used is the
SPSR, if R = 0 the program status register is the CPSR register The immediate filed is rotated by the rotate field value to move the bits to the Flag bits position of the PSR
ARM System Vectors
The system vectors for the ARM architecture
are rather sparse, compared to the 68K and 8086
architectures There are a total of 8 system
vec-tors, shown in the following table:
The Fast Interrupt Request vector is the last
vector in the table for a reason that may not be
so obvious Recall that each vector is a 32-bit
word, capable of holding just one instruction
That instruction will generally be a branch instruction to the starting point of the user’s service routine The FIR vector sits at the top of the table so that the FIR service routine can begin at address 0x0000001C and continue on from there, without the need to add a branch instruction to get to the real code If you want to be fast, every clock cycle counts!
The Prefetch Abort vector is used when the processor attempts to fetch an instruction from an address without having the correct permissions to access that instruction It is called a pre-fetch abort because the actual instruction decoding takes place after the instruction is fetched, but the exception actually occurs during the prefetching of the instruction We’ll look into this more deeply when we study pipelined processors in a later chapter
The Data Abort vector is like the Prefetch Abort vector, except for data Thus, a Data Abort Exception will occur when the processor attempts to fetch data from a memory region without the correct access permissions
The Reset vector is also unique because when it is asserted the processor will immediately stop execution and begin the reset sequence With other exceptions, the processor will complete the current instruction before accepting the exception sequence Of course, this makes good sense, since a reset has no need to restore the system context, so you might as well get on with it as soon
as possible
Figure 11.10: Format for the ARM modify status register instructions.
MSR COND 0 0 0 1 0 R 0 0 1 1 1 1 Rd 0 0 0 0 0 0 0 0 0 0 0 0
MSR Immediate Form COND 0 0 1 1 0 R 1 0 field_mask 1 1 1 1 Rotate Immediate
MSR Register Form COND 0 0 0 1 0 R 1 0 field_mask 1 1 1 1 0 0 0 0 0 0 0 0 0 Rm
Trang 9Chapter 11
Summary and Conclusions
The ARM instruction set is a thoroughly modern, 32-bit RISC instruction set Unlike the 8086 and 68K processors, all instructions are the same length and, with few, exceptions, execute in one clock cycle The register set is almost completely general-purpose Only three of the 16 regis-ters user mode registers have dedicated uses All data processing instructions take place between registers and all memory operations are restricted to memory-to-register load operations and regis-ter-to-memory store operations All memory accesses use one of the general purpose registers as a base address memory pointer Additional effective addressing modes enhance this model by adding incrementing, decrementing, index register, immediate offset values and scaled register modes While you might disagree with this, the ARM instruction set architecture is quite a bit simpler and more restrictive than the architectures that we’ve previously examined This simplicity places more dependence upon the compiler to be able to generate the most optimal code flow, and hence, the most efficient code
With this chapter’s overview of the ARM architecture we will be leaving the study of common chitectures and move on to other topics We’ll return to the study of architecture once again when
ar-we consider pipelines in detail in a later chapter At that time ar-we’ll return to the ARM architecture once again, but hopefully, we’ll stay at a higher level the next time around While a certain per-centage of those of you reading these chapters may have found this as exciting as watching paint dry, these is a method to the madness In order to understand a computer’s architecture from a software perspective, we must look at examples of how the various bit patterns are used to form the instruction words
Dr Science, a performer on National Public Radio, once said,
“I like to read columns of random numbers, looking for patterns.”
Summary of Chapter 11
Chapter 11 covered:
• A brief history of the evolution of the ARM architecture
• An overview of the ARM7TDMI processor architecture
• An introduction to the ARM instruction set and addressing modes
Chapter 11: Endnotes
1 Jim Turley, RISCy Business, Embedded Systems Programming, March, 2003, p 37.
2 Ibid.
3 ARM Corporate Backgrounder, http://www.arm.com/miscPDFs/3822.pdf, p 1.
4 Andrew N Sloss, Dominic Symes and Chris Wright, ARM System Developer’s Guide, ISBN 1-55860-874-5,
Morgan-Kaufmann, San Francisco, CA.
5 Dave Jagger, Editor, Advanced RISC Machines Architectural Reference Manual, ISBN 0-13-736299-4, Prentice-Hall,
London.
6 Steve Furber, ARM System-on-chip Architecture, ISBN 0-201-67519-6, Addison-Wesley, Harlow, England.
7 Andrew N Sloss, Dominic Symes and Chris Wright, ibid, pp 143–149.
Trang 101 What are the operating modes of the ARM system? How do they compare with the 68K?
2 Why is there a Fast Interrupt Request Mode and how is it implemented?
3 Compare the 16 base registers of the ARM architecture with the 16 registers of the 68K architecture
4 Is the instruction,
MOV r4,#&103
a legal or illegal instruction? Why? Note: &103 is the ARM notation for a hexadecimal number
5 Write a code snippet that loads register r4 with the immediate value &103
6 Initialize register r7 with the value &06AA4C01
7 Suppose that the contents of register r8 = &0010AA00 and the contents of register
r6 = &0000CFD3 What will be the value stored in register r11 after the instruction:
Trang 11C H A P T E R 12
Interfacing with the Real World
Objectives
When you are finished with this lesson, you will be able to:
Describe why interrupts are inherent in computer/real-world interaction;
Explain why interrupts are prioritized;
Understand the concept of I/O ports;
Explain how analog signals are converted to the digital domain and vice versa;
Understand the tradeoffs associated with speed versus accuracy in the analog to digital conversion process.
Introduction
In the previous lesson we saw that a computer that operated only within its own environment, and couldn’t interact with the real world is a rather useless computer It is a nice environment for studying architecture, but that’s about all its good for It was somewhat refreshing (I hope) when you were able to add input and output activity (I/O) to your programs using the TRAP #15 instruc-tions Now, let’s begin our discussion of computers and the real-world by consider Figure 12.1 The drawing inside the dotted lines in the figure represents the minimum number of components necessary to have an operating computer Outside of the dotted lines is everything else that we need to make it do useful work
As you can see, a processor, memory array, glue logic (memory decoding and such) and clocks form the basic computer, but this computer is relatively worthless in human terms We somehow
need to be able to interact (interface) with external stimuli.
The external world (real world) has its own sets of constraints that we must be able to deal with
The real world is a very messy place compared to the motherboard of your PC Some of these constraints are:
• real world events are generally not digital in nature;
• real world events happen at much different rates than the fundamental clock cycle in the computer;
• real world events are transitory and may be lost if not serviced within the appropriate timeframe;
• real world events often take place in environments that are dirty, wet, extremely hot or cold, or have large amounts of background noise (electrical interference);
Trang 12Interfacing with the Real World
• failures in computers
that service real world
events have real world
consequences
Criti-cal systems may fail
(Y2K) or human life
may be lost
If we are going to accept the
fact that we need to make
some order out of the chaos of
the real-world, we first need
to understand how the
real-world and the computer can
communicate with each other
Since events happen at such
different rates, we need
meth-ods that will allow us to
synchronize the worlds inside
and outside of our computer
environment The first of these
methods that we need to discuss is the concept of interrupts
Interrupts
So far we’ve examined the computer system in terms of the processor and memory Add a clock and this is a functional, but useless, computer On occasion, throughout the previous lessons, you
might have noticed the word interrupt sprinkled here and there Now let’s take the time to
under-stand just what the interrupt is all about Recall that we actually alluded to interrupts when we studied the computer architectures in the previous chapters In particular, we looked at the ARM architecture and its interrupt and fast interrupt request modes We also looked at software inter-rupts and how they were used to change the context of the processor and access the operating system Now, let’s step back and look at the interrupt process itself
In order for a computer to be worth the cost of the electricity that you feed into it, it must be able
to interact with you and its environment You manipulate a keyboard and a mouse The computer responds with actions on the screen, sound, disk access, etc Sometimes unexpected events, called
exceptions, occur and the computer has to be able to deal with them A typical exception might
be the result of an errant pointer causing the program to attempt a memory fetch from a region of memory where no physical memory is present Or, you try to divide by zero Duh!
When asynchronous events, both internal and external to the processor, need to grab the attention
of the processor, they do it by generating an interrupt The interrupt forces the processor to stop its
normal program execution and start executing another block of code called the interrupt service
Figure 12.1: A typical computer system The functional blocks shown inside of the dotted lines are the minimal requirements for a computer
to actually run
Microprocessor
Address Bus Data Bus Status Bus Glue Logic and Address Decode Clock Generation
and Distribution
Real Time Clock
Random Access Memory - RAM
Read Only Memory - ROM ( FLASH )
Minimal Requirements for an operating computer
I/O Interface ( D/A, A/D, Digital )
Communications
Other Peripheral Devices
To outside world
To outside world
To host computer
To User I/F Watchdog Timer
NMI
Trang 13Chapter 12
Suppose we didn’t have interrupts In order for a processor to take care of these events it would have to periodically check each event that might require servicing to see if the event is ready for service A good analogy is the ringer on the telephone Here you are, eating dinner (the applica-tion), when the phone rings (the interrupt) You put down your fork and answer the phone (ISR) You tell the telemarketer that you don’t want a free vacation at the exciting Riviera Resort in Newfoundland and go back to your dinner (return from the interrupt)
Now, suppose that the ringer on your phone is broken The only way for you to tell if someone
is calling you is to pick up the phone every few seconds and say, “Hello, hello, is anyone there?”
This gets very old, very fast The analogous process in a computer is called polling In a polled
system, the computer periodically checks each event that might require servicing as part of its regular program code Polling is still a very acceptable way to program a computer when the appli-cation lends itself to a polled structure A burglar alarm controller is a perfect example of a polled system The program checks every sensor in turn to see if it has been tripped by a burglar or by the family cat If a sensor has tripped, the program turns on the alarm The program runs in a continu-
ous loop, called a polling loop, checking the sensors
As you might imagine, when a computer is polling its peripheral devices to see if they need to
be serviced, it isn’t doing much of anything else That’s why we have interrupts The interrupts, because they are asynchronous, happen more or less randomly, and the processor deals with them
on an “as needed” basis However, we should not lose sight of the fact that interrupts could also happen at very precise intervals, as well as randomly For example, your Windows Operating Sys-tem has external timers providing clock ticks every few milliseconds, and other systems may have interrupts appearing regularly every few microseconds The key point is that the interrupts are not synchronized to our program’s execution Now let’s examine some of the common types of inter-rupts that you might encounter in a computer system
The most common interrupt is the RESET (RST) RESET is a very dramatic interrupt It starts the processor from the beginning It does not, as do other interrupts, return to a point in the applica-tion where it left off The RESET interrupt assumes that everything is suspect and you truly want
to start from the beginning When you assert the RESET by pressing the RESET button on your computer you cause the following sequence of events to occur:
1 clear the contents of the internal registers;
2 establish the processor in a known state; and
3 begin program execution from a known memory location
Please note that the above process is a general list of actions for the RESET interrupt As we ously saw, different processors start in different ways Modern Pentium and Athlon CPUs have very complex start-up sequences when RESET is asserted
previ-If you examine the RESET interrupt at the hardware level you might be surprised to see that you have to hold the RESET input asserted for quite a number of clock pulses in order for the RESET
to work properly This is another clue that our algorithmic state machine is busy behind the scenes
It is typical that the RESET input may have to be asserted for 50 to several hundred clock cycles in order to bring the state machine to the correct state
Trang 14Interfacing with the Real World
Interrupts, because they are asynchronous, can interrupt each other A processor can be in an ISR when another interrupt comes in What does the processor do? In order to deal with this situation interrupts may be prioritized A more important (higher priority) interrupt may always preempt a lower priority interrupt What are some examples of high and low priority interrupts? Answering this question is not always as straight-forward as it seems Sometimes we are concerned with the window of time that is available to us to service the interrupt If we are trying to capture and pro-cess a fast data stream, such as a digital video camcorder, and we don’t want to drop any frames, then we might give that interrupt a higher priority
Another factor might be criticality of the interrupt Most laptop computers have a high priority terrupt driven by the circuitry that monitors the battery’s energy level When the battery has almost lost its ability to power the computer, a high-priority ISR automatically takes over and saves the state of the computer so you can shut down and recover when the battery is recharged Speaking
in-of criticality in-of the interrupt, the highest priority interrupt mechanisms are usually reserved for protecting human life
A lower priority interrupt will have to wait if a higher priority interrupt is being serviced because
the higher priority interrupt can mask the interrupt signal from the lower priority interrupt This
is why you get the hourglass in Windows when your PC is busy with the disk drive It’s Windows way of telling you that the mouse is waiting its turn while the disk data is being read
In many situations, particularly with operating systems such as Windows and Linux, the time it takes for the computer and operating system to respond to an interrupt, is unpredictable, and may not be fast enough, to reliably service all of the interrupts in the allotted amount of time In order
to deal with computer-based systems that must function reliably while dealing with real-world events, a different type of operating system was designed Operating systems that must be able to
handle external events occurring in real-world time frames are called real-time operating systems,
or RTOSs Unlike Windows, an RTOS is not an egalitarian operating system The operating system
on your PC schedules tasks in a round robin fashion Each task that is executing receives a slice of time from the operating system (usually abbreviated O/S), independent of how “important” that task may be Sometimes the O/S will, in the background, give tasks that appear to be doing input and output more time than tasks that are not However, the key is that we cannot predict with high confidence that under all conditions, that all tasks will be executed in order of their criticality and that all interrupts will be serviced in the required time windows Of course, getting a faster comput-
er always helps, but sometimes economic reality rears its ugly head and that is not a viable option.RTOSs use a very different scheduling mechanism than PC O/Ss An RTOS task of higher prior-ity that is ready to run will always preempt a lower priority task that is currently running Also, the kernel software of the O/S is carefully designed to minimize the time spent switching between tasks This is the reason why the ARM architecture has a fast interrupt request mode and banked registers Both features are architectural enhancements for speeding up the response time of the processor to the stringent requirements of servicing interrupts in a timely manner
Figure 12.2 is a graph of the behavior of a computer system running under the control of an RTOS
Trang 15Chapter 12
of descending priority The highest
priority interrupt, Int_1 has a higher
priority than Int_2, which has a higher
priority than any task The lowest
prior-ity task is the system in its idle state
Notice how each task of higher priority
may preempt the lower priority task until
the higher priority task either runs to
completion or must wait for information
before it can proceed Consider the task
labeled Task_3 When Task_3 becomes
active it preempts Task_5 and continues
to run until it stops at about Time =
10.4155 seconds At that time Task_5
starts again until it is preempted once
again, this time by Task_1, the highest
priority task
Task_1 runs but is preempted by Int_2 When the ISR for Int_2 completes, Task_1 starts up
again and then stops, allowing Task_3 to once again take over When Task_3 finally stops ing Task_5 can begin to execute However, Task_4 suddenly comes alive and preempts Task_5 Finally, Task_4 completes and Task_5 can finish execution When Task_5 completes the system returns to the idle state
execut-If all this seems very complicated, you’re right Even in this “relatively simple” example, you can begin to see the potential problems that might emerge What if Task_5 keeps getting preempted
by the higher priority tasks and interrupts above it and never runs to completion? That is certainly
a possibility We can also, have certain sequence of events cause the system to lock up One such
situation is called priority inversion Priority inversion occurs when higher priority tasks are
suspended from running because lower priority tasks were themselves preempted, but the lower priority task retains control of a system resource, such as a memory buffer, that the higher prior-
ity task needs to use A very interesting priority inversion problem occurred with the Mars Rover
project1 when the rover had just halted on Mars The mission control team back in Pasadena ran simulations with an identical rover running in the Jet Propulsion Laboratory’s back yard and they discovered that the rover’s RTOS had locked up due to a priority inversion They were able to cor-rect the problem and upload new code to the rover’s 8086-based computer system
You’ve seen from the above example that interrupts, because they are asynchronous, can interrupt each other A processor can be in an ISR when another interrupt comes in What does the proces-sor do? In order to deal with this situation interrupts are generally prioritized A more important (higher priority) interrupt may always preempt a lower priority interrupt, just as a higher priority task may preempt a lower priority task What are some examples of high and low priority inter-rupts? A lower priority interrupt will have to wait if a higher priority interrupt is being serviced
because the higher priority interrupt can mask the interrupt signal from the lower priority interrupt
Figure 12.2: Graph of the interrupt and task switching response of a typical real-time operating system The X axis spans approximately 3 milliseconds of execution time
Int_1 Int_2 Task_1 Task_2 Task_3 Task_4 Task_5 Task_6 Task_7 Task_8 System idle
Time (Seconds)