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PowerPoint Presentation TRƯỜNG ĐẠI HỌC BÁCH KHOA TPHCM KHOA ĐIỆN – ĐIỆN TỬ * BÁO CÁO ĐỀ TÀI THIẾT KẾ CPU 8 BIT (LC3b) GVHD Trần Hoàng Linh NHÓM Thành viên Lê Tiến Khải 1411783 Lê Huỳnh Thiện Nhân 1412[.]

TRƯỜNG ĐẠI HỌC BÁCH KHOA TPHCM

KHOA ĐIỆN – ĐIỆN TỬ * _

BÁO CÁO ĐỀ TÀI THIẾT KẾ CPU 8 BIT (LC3b)

GVHD : Trần Hoàng Linh

Thành viên:

Lê Tiến Khải 1411783

Lê Huỳnh Thiện Nhân 1412606 Nguyễn Thanh Nhân1412628

REG FILE

MEMORY

IR

MARMUX

EAB

PC

ALU

GateMARMUX

GateALU GateSHF

GatePC

GateMDR

clk rst clk

clk

clk clk

rst

rst

rst rst

LD.IR

LD.CC

LD.REG

LD.MAR LD.MDR

memWE

selMDR selEAB1

selEAB2

selMAR

N Z P

selPC

LD.PC

SR2 DR

SR1

SR2 out

SR1 out

ALUK 8

16

16

16 16

16

16

11

6

6

2

2

16

3

3 3

16

SƠ ĐỒ KHỐI

REG FILE

MARMUX

ZEXT

&LSHF1

IR

SEXT

PCMUX

N Z P LOGIC

SHF

MAR

MDR

LD.IR

SEXT

SEXT

SEXT

ADDR2MUX LSHF1

+

ADDR1MUX

PC LD.PC

+2

LD.REG

SR2

SR2 OUT

SR1 OUT

DRMUX DR

SR2MUX

ALU

A B

GateMARMUX

GateALU GateSHF

GatePC

LD.MAR

WE

MDRMUX

MIO.EN

LD.MDR

GateMDR IR[5]

SR1MUX SR1

111 IR[11:9]

IR[8:6]

IR[11:9]

ALUK

CONTROL

LD.MDR LD.REG

LD.CC

LD.PC GateALU

[10:0]

[8:0]

[5:0]

[4:0]

[7:0]

IR[5:0]

16 16

3

3 3

16

16 16 16

2

16

16

16 0

16 16 16

6

16 16 16

2

SƠ ĐỒ CHI TIẾT

LƯU ĐỒ TRẠNG THÁI

REG FILE

CONTROL

MARMUX

ZEXT

&LSHF1

IR

SEXT

PCMUX

N Z P LOGIC

SHF

MAR

MDR

LD.IR

SEXT

SEXT

SEXT

ADDR2MUX LSHF1

+

ADDR1MUX

PC LD.PC

+2

LD.REG

SR2

SR2 OUT

SR1 OUT

DRMUX

DR

SR2MUX

ALU

A B

GateMARMUX

GateALU GateSHF

GatePC

LD.MAR

WE

MDRMUX

MIO.EN

LD.MDR

GateMDR IR[5]

SR1MUX SR1

111 IR[11:9]

IR[8:6]

IR[11:9]

ALUK

LD.MAR

LD.MDR LD.REG

LD.CC

LD.PC GateALU

[10:0]

[8:0]

[5:0]

[4:0]

[7:0]

IR[5:0]

16 16

3

3 3

16

16 16 16

2

16

16

16 0

16 16 16

6

16 16 16

2

GatePC

LD.MAR

01 LD.PC

MIO.EN

1

LD.MDR

GateMDR LD.IR

IR[5]

1

ALUK

00

IR[11:9]

IR[8:6]

GateALU LD.REG

LD.CC

REG FILE

CONTROL

MARMUX

ZEXT

&LSHF1

IR

SEXT

PCMUX

N Z P LOGIC

SHF

MAR

MDR

LD.IR

SEXT

SEXT

SEXT

ADDR2MUX LSHF1

+

ADDR1MUX

PC LD.PC

+2

LD.REG

SR2

SR2 OUT

SR1 OUT

DRMUX

DR

SR2MUX

ALU

A B

GateMARMUX

GateALU GateSHF

GatePC

LD.MAR

WE

MDRMUX

MIO.EN

LD.MDR

GateMDR IR[5]

SR1MUX SR1

111 IR[11:9]

IR[8:6]

IR[11:9]

ALUK

LD.MAR

LD.MDR LD.REG

LD.CC

LD.PC GateALU

[10:0]

[8:0]

[5:0]

[4:0]

[7:0]

IR[5:0]

16 16

3

3 3

16

16 16 16

2

16

16

16 0

16 16 16

6

16 16 16

2

ADD

GatePC

LD.MAR

01 LD.PC

MIO.EN

1

LD.MDR

GateMDR LD.IR

IR[5]

1

ALUK

00

IR[11:9]

IR[8:6]

GateALU

LD.REG

LD.CC

0 0 0 1 DR SR1 1 imm5

REG FILE

CONTROL

MARMUX

ZEXT

&LSHF1

IR

SEXT

PCMUX

N Z P LOGIC

SHF

MAR

MDR

LD.IR

SEXT

SEXT

SEXT

ADDR2MUX LSHF1

+

ADDR1MUX

PC LD.PC

+2

LD.REG

SR2

SR2 OUT

SR1 OUT

DRMUX

DR

SR2MUX

ALU

A B

GateMARMUX

GateALU GateSHF

GatePC

LD.MAR

WE

MDRMUX

MIO.EN

LD.MDR

GateMDR IR[5]

SR1MUX SR1

111 IR[11:9]

IR[8:6]

IR[11:9]

ALUK

LD.MAR

LD.MDR LD.REG

LD.CC

LD.PC GateALU

[10:0]

[8:0]

[5:0]

[4:0]

[7:0]

IR[5:0]

16 16

3

3 3

16

16 16 16

2

16

16

16 0

16 16 16

6

16 16 16

2

AND

GatePC

LD.MAR

01 LD.PC

MIO.EN

1

LD.MDR

GateMDR LD.IR

IR[5]

0

ALUK

11

IR[11:9]

IR[8:6]

SR2

GateALU

LD.REG

LD.CC

0 1 0 1 DR SR1 0 00 SR2

REG FILE

CONTROL

MARMUX

ZEXT

&LSHF1

IR

SEXT

PCMUX

N Z P LOGIC

SHF

MAR

MDR

LD.IR

SEXT

SEXT

SEXT

ADDR2MUX LSHF1

+

ADDR1MUX

PC LD.PC

+2

LD.REG

SR2

SR2 OUT

SR1 OUT

DRMUX

DR

SR2MUX

ALU

A B

GateMARMUX

GateALU GateSHF

GatePC

LD.MAR

WE

MDRMUX

MIO.EN

LD.MDR

GateMDR IR[5]

SR1MUX SR1

111 IR[11:9]

IR[8:6]

IR[11:9]

ALUK

LD.MAR

LD.MDR LD.REG

LD.CC

LD.PC GateALU

[10:0]

[8:0]

[5:0]

[4:0]

[7:0]

IR[5:0]

16 16

3

3 3

16

16 16 16

2

16

16

16 0

16 16 16

6

16 16 16

2

AND

GatePC

LD.MAR

01 LD.PC

MIO.EN

1

LD.MDR

GateMDR LD.IR

IR[5]

1

ALUK

11

IR[11:9]

IR[8:6]

GateALU

LD.REG

LD.CC

0 1 0 1 DR SR1 1 imm5

REG FILE

CONTROL

MARMUX

ZEXT

&LSHF1

IR

SEXT

PCMUX

N Z P LOGIC

SHF

MAR

MDR

LD.IR

SEXT

SEXT

SEXT

ADDR2MUX LSHF1

+

ADDR1MUX

PC LD.PC

+2

LD.REG

SR2

SR2 OUT

SR1 OUT

DRMUX

DR

SR2MUX

ALU

A B

GateMARMUX

GateALU GateSHF

GatePC

LD.MAR

WE

MDRMUX

MIO.EN

LD.MDR

GateMDR IR[5]

SR1MUX SR1

111 IR[11:9]

IR[8:6]

IR[11:9]

ALUK

LD.MAR

LD.MDR LD.REG

LD.CC

LD.PC GateALU

[10:0]

[8:0]

[5:0]

[4:0]

[7:0]

IR[5:0]

16 16

3

3 3

16

16 16 16

2

16

16

16 0

16 16 16

6

16 16 16

2

NOT

GatePC

LD.MAR

01 LD.PC

MIO.EN

1

LD.MDR

GateMDR LD.IR

ALUK

10

IR[11:9]

IR[8:6]

GateALU

LD.REG

LD.CC

1 0 0 1 DR SR1 1 11111

REG FILE

CONTROL

MARMUX

ZEXT

&LSHF1

IR

SEXT

PCMUX

N Z P LOGIC

SHF

MAR

MDR

LD.IR

SEXT

SEXT

SEXT

ADDR2MUX LSHF1

+

ADDR1MUX

PC LD.PC

+2

LD.REG

SR2

SR2 OUT

SR1 OUT

DRMUX

DR

SR2MUX

ALU

A B

GateMARMUX

GateALU GateSHF

GatePC

LD.MAR

WE

MDRMUX

MIO.EN

LD.MDR

GateMDR IR[5]

SR1MUX SR1

111 IR[11:9]

IR[8:6]

IR[11:9]

ALUK

LD.MAR

LD.MDR LD.REG

LD.CC

LD.PC GateALU

[10:0]

[8:0]

[5:0]

[4:0]

[7:0]

IR[5:0]

16 16

3

3 3

16

16 16 16

2

16

16

16 0

16 16 16

6

16 16 16

2

LEA

GatePC

LD.MAR

01 LD.PC

MIO.EN

1

LD.MDR

GateMDR LD.IR

IR[11:9]

LD.REG

LD.CC

1 1 1 0 DR PCoffset9

0 10

1 GateMARMUX

REG FILE

CONTROL

MARMUX

ZEXT

&LSHF1

IR

SEXT

PCMUX

N Z P LOGIC

SHF

MAR

MDR

LD.IR

SEXT

SEXT

SEXT

ADDR2MUX LSHF1

+

ADDR1MUX

PC LD.PC

+2

LD.REG

SR2

SR2 OUT

SR1 OUT

DRMUX

DR

SR2MUX

ALU

A B

GateMARMUX

GateALU GateSHF

GatePC

LD.MAR

WE

MDRMUX

MIO.EN

LD.MDR

GateMDR IR[5]

SR1MUX SR1

111 IR[11:9]

IR[8:6]

IR[11:9]

ALUK

LD.MAR

LD.MDR LD.REG

LD.CC

LD.PC GateALU

[10:0]

[8:0]

[5:0]

[4:0]

[7:0]

IR[5:0]

16 16

3

3 3

16

16 16 16

2

16

16

16 0

16 16 16

6

16 16 16

2

LDR

GatePC

LD.MAR

01 LD.PC

MIO.EN

1

LD.MDR

GateMDR LD.IR

IR[11:9]

LD.REG

LD.CC

0 1 1 0 DR BaseR offset6

01

1 GateMARMUX

1

IR[8:6]

REG FILE

CONTROL

MARMUX

ZEXT

&LSHF1

IR

SEXT

PCMUX

N Z P LOGIC

SHF

MAR

MDR

LD.IR

SEXT

SEXT

SEXT

ADDR2MUX LSHF1

+

ADDR1MUX

PC LD.PC

+2

LD.REG

SR2

SR2 OUT

SR1 OUT

DRMUX

DR

SR2MUX

ALU

A B

GateMARMUX

GateALU GateSHF

GatePC

LD.MAR

WE

MDRMUX

MIO.EN

LD.MDR

GateMDR IR[5]

SR1MUX SR1

111 IR[11:9]

IR[8:6]

IR[11:9]

ALUK

LD.MAR

LD.MDR LD.REG

LD.CC

LD.PC GateALU

[10:0]

[8:0]

[5:0]

[4:0]

[7:0]

IR[5:0]

16 16

3

3 3

16

16 16 16

2

16

16

16 0

16 16 16

6

16 16 16

2

STR

GatePC

LD.MAR

01 LD.PC

MIO.EN

1

LD.MDR

GateMDR LD.IR

0 1 1 1 SR BaseR offset6

01

1 GateMARMUX

1

IR[8:6]

IR[11:9]

ALUK

01

GateALU

0

WE 11

REG FILE

CONTROL

MARMUX

ZEXT

&LSHF1

IR

SEXT

PCMUX

N Z P LOGIC

SHF

MAR

MDR

LD.IR

SEXT

SEXT

SEXT

ADDR2MUX LSHF1

+

ADDR1MUX

PC LD.PC

+2

LD.REG

SR2

SR2 OUT

SR1 OUT

DRMUX

DR

SR2MUX

ALU

A B

GateMARMUX

GateALU GateSHF

GatePC

LD.MAR

WE

MDRMUX

MIO.EN

LD.MDR

GateMDR IR[5]

SR1MUX SR1

111 IR[11:9]

IR[8:6]

IR[11:9]

ALUK

LD.MAR

LD.MDR LD.REG

LD.CC

LD.PC GateALU

[10:0]

[8:0]

[5:0]

[4:0]

[7:0]

IR[5:0]

16 16

3

3 3

16

16 16 16

2

16

16

16 0

16 16 16

6

16 16 16

2

JMP

GatePC

LD.MAR

11 LD.PC

MIO.EN

1

LD.MDR

GateMDR LD.IR

ALUK

01

GateALU

1 1 0 0 000 BaseR 000000

11

IR[8:6]

REG FILE

CONTROL

MARMUX

ZEXT

&LSHF1

IR

SEXT

PCMUX

N Z P LOGIC

SHF

MAR

MDR

LD.IR

SEXT

SEXT

SEXT

ADDR2MUX LSHF1

+

ADDR1MUX

PC LD.PC

+2

LD.REG

SR2

SR2 OUT

SR1 OUT

DRMUX

DR

SR2MUX

ALU

A B

GateMARMUX

GateALU GateSHF

GatePC

LD.MAR

WE

MDRMUX

MIO.EN

LD.MDR

GateMDR IR[5]

SR1MUX SR1

111 IR[11:9]

IR[8:6]

IR[11:9]

ALUK

LD.MAR

LD.MDR LD.REG

LD.CC

LD.PC GateALU

[10:0]

[8:0]

[5:0]

[4:0]

[7:0]

IR[5:0]

16 16

3

3 3

16

16 16 16

2

16

16

16 0

16 16 16

6

16 16 16

2

JSR

GatePC

LD.MAR

01 LD.PC

MIO.EN

1

LD.MDR

GateMDR LD.IR

111

IR[11] = 0

LD.REG

0 1 0 0 0 00 BaseR 000000

IR[8:6]

ALUK

01

GateALU 11

REG FILE

CONTROL

MARMUX

ZEXT

&LSHF1

IR

SEXT

PCMUX

N Z P LOGIC

SHF

MAR

MDR

LD.IR

SEXT

SEXT

SEXT

ADDR2MUX LSHF1

+

ADDR1MUX

PC LD.PC

+2

LD.REG

SR2

SR2 OUT

SR1 OUT

DRMUX

DR

SR2MUX

ALU

A B

GateMARMUX

GateALU GateSHF

GatePC

LD.MAR

WE

MDRMUX

MIO.EN

LD.MDR

GateMDR IR[5]

SR1MUX SR1

111 IR[11:9]

IR[8:6]

IR[11:9]

ALUK

LD.MAR

LD.MDR LD.REG

LD.CC

LD.PC GateALU

[10:0]

[8:0]

[5:0]

[4:0]

[7:0]

IR[5:0]

16 16

3

3 3

16

16 16 16

2

16

16

16 0

16 16 16

6

16 16 16

2

JSRR

GatePC

LD.MAR

01 LD.PC

MIO.EN

1

LD.MDR

GateMDR LD.IR

111

[10:0]

IR[11] = 1

0

11

10

LD.REG

0 1 0 0 1 PCoffset11

REG FILE

CONTROL

MARMUX

ZEXT

&LSHF1

IR

SEXT

PCMUX

N Z P LOGIC

SHF

MAR

MDR

LD.IR

SEXT

SEXT

SEXT

ADDR2MUX LSHF1

+

ADDR1MUX

PC LD.PC

+2

LD.REG

SR2

SR2 OUT

SR1 OUT

DRMUX

DR

SR2MUX

ALU

A B

GateMARMUX

GateALU GateSHF

GatePC

LD.MAR

WE

MDRMUX

MIO.EN

LD.MDR

GateMDR IR[5]

SR1MUX SR1

111 IR[11:9]

IR[8:6]

IR[11:9]

ALUK LD.MAR

LD.CC

[10:0]

[8:0]

[5:0]

[4:0]

[7:0]

IR[5:0]

16 16

3

3 3

16

16 16 16

2

16

16

16 0

16 16 16

6

16 16 16

2

BR 0 0 0 0 n z p PCoffset9

GatePC

LD.MAR

01 LD.PC

MIO.EN

1

LD.MDR

GateMDR LD.IR

0 11

BEN = 1 GateMARMUX

REG FILE

CONTROL

MARMUX

ZEXT

&LSHF1

IR

SEXT

PCMUX

N Z P LOGIC

SHF

MAR

MDR

LD.IR

SEXT

SEXT

SEXT

ADDR2MUX LSHF1

+

ADDR1MUX

PC LD.PC

+2

LD.REG

SR2

SR2 OUT

SR1 OUT

DRMUX

DR

SR2MUX

ALU

A B

GateMARMUX

GateALU GateSHF

GatePC

LD.MAR

WE

MDRMUX

MIO.EN

LD.MDR

GateMDR IR[5]

SR1MUX SR1

111 IR[11:9]

IR[8:6]

IR[11:9]

ALUK

LD.MAR

LD.MDR LD.REG

LD.CC

LD.PC GateALU

[10:0]

[8:0]

[5:0]

[4:0]

[7:0]

IR[5:0]

16 16

3

3 3

16

16 16 16

2

16

16

16 0

16 16 16

6

16 16 16

2

TRAP

GatePC

LD.MAR

01 LD.PC

MIO.EN

1

LD.MDR

GateMDR LD.IR

1

1 1 1 1 0000 trapvect8

0

GateMARMUX

LD.REG

111

11