The mini mips verilog code and the test bench

The mini mips verilog code and the test bench

THE MINI-MIPS VERILOG CODE AND THE TEST-BENCH

module top(

input clk, reset,

output [31:0] WriteData,DataAdr,

output MemWrite);

wire [31:0] Pcnext, Instr, Readdata;

// instantiate processor and memories

mips mips (clk,reset,Instr,Readdata,Pcnext,DataAdr,WriteData,MemWrite);

instructmem instructmem (Pcnext[7:2],Instr);

datamem datamem (clk,MemWrite,DataAdr,WriteData,Readdata);

Verilog: Mips

module mips(

input clk,reset, input [31:0] InstrF,ReaddataM,

output [31:0] PcnextFD,

output [31:0] ALUoutM,WriteDataM, output MemWriteM);

endmodule

output [1:0] RegDstE, output [1:0] jumpD, output PcSrcM);

flopr register (clk,reset,

{RegWriteE,MemtoRegE,MemWriteE,BegE,BneE}, {RegWriteM,MemtoRegM,MemWriteM,BeqM,BneM});

flopr registerW_ (clk,reset,

{RegWriteM,MemtoRegM), {RegWriteW,MemtoRegW});

endmodule

.MemtoRegW(MemtoRegw), RegWriteW(RegWriteW), jumpD(jumpD),

.ALUSrcE(ALUSrcE), RegDstE(RegDstE));

mux4 muxALUSrcE_ (WriteDataE,SignImmE,{InstrD[16:0],16'b00},32'b00,ALUSrcE,SrcBE);

mux4 muxRegDstE_ (rtE,rdE,5'b11111,4'b0000,RegDstE,WriteRegE);

mux2 muxMemtoRegW (ALUoutW,ReaddataW,MemtoRegW,ResultW);

//register file (operates in Decode and WriteBack)

registerfile rf (clk,RegWriteW,InstrD[25:21],InstrD[20:16],WriteRegW,MuxResultD,SrcAD,WriteDataD);

//Fetch stage Logic

flopr PcReg (clk,reset,PcnextbarFD,PcnextFD);

adder PcAdd1 (PcnextFD,32'b100,PcPlus4F);

//Decode stage

assign opcodeD = InstrD[31:26];

assign functD = InstrD[5:0];

flopr 12D (clk,reset,InstrF,InstrD[31:0]);

Signext se (InstrD[15:0],SignExD);

//Execute stage

flopr rE (clk, reset, SrcAD,SrcAE);

flopr r2E (clk, reset, WriteDataD, WriteDataE);

flopr r3E (clk, reset, InstrD[20:16],rtE);

flopr r4E (clk, reset, InstrD[15:11],rdE);

flopr r5E (clk, reset, SignExD,SignimmE);

flopr r6E (clk, reset, PcPlus4D,PcPlus4E);

adder pcadd2 (SignimmshE,PcPlus4E,PcBranchE);

flopr r1W (clk, reset, ALUoutM, ALUoutW);

flopr r2W (clk, reset, ReaddataM,ReaddataW);

flopr r3W (clk, reset, WriteRegM, WriteRegW);

endmodule

4'b0010: Result <= SrcA+SrcB; //add

4'b1001: Result <=~ (SrcA|SrcB); //nor

4'b1010: Result <= SrcA-SrcB; //sub

.ALUcontrol(ALUcontrol), Result(Result),

Verilog: Resettable Flip-Flop

module flopr #(parameter width = 8) //Resettable register

Verilog: Multiplexer 2 inputs

module mux2 #(parameter width = 8)

-S(S), -Y(y));

Verilog: Multiplexer 4 inputs

module mux4 #(parameter width = 8)

-S(S), V(V));

// three port register file

// read two ports combinationally

// write third port on rising edge of clock

// register O hardwired to 0

always @ (posedge clk)

if (we3) rf[wa3] <= wd3;

assign rd1 = (ral != 0) ? rf[ra1] : 0;

assign rd2 = (ra2 != 0) ? rf[ra2] : 0;

endmodule

// \Instantiate the Unit Under Test (UUT)