scaled planar floating gate nand flash memory technology doc

Figure 1,2: Demand for NAND flash memory Souree: Gartner May 2008, Semiconductor Forecast Database SEQS-WW-DB 1.21 Figure 2.2: Semiconductor memory market for flash, DRAM and SRAM Sour

SCALED PLANAR FLOATING-GATE NAND FLASH MEMORY

‘TECHNOLOGY: CHALLENGES AND NOVEL SOLUTIONS

A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

Shyam Raghunathan October 2010

(© 2011 by Shyam Sunder Raghunathan, All Rights Reserve

Resdisebuted by Stanford University under Ticense with the author

“This work is leensed under a Creative Commons Attribution- [CDG] wovommeriat 3.0 United States License

‘This dissertation is online al

anf edulyy374y9591

1 ceri that Ihave res this dissertation and that, in my opinion tis fully adequate

in scope and quality as a dissertation forthe degree of Doctor of Philosophy

Krishna Saraswat, Primary Adviser

1 cenily that {have read this dissertation and that, in my opinion, i fully adequate

Ít scope and quality as dissertation forthe degece of Doctor of Philosophy

Yoshio Nishi, Co-Adviser

1 comity that have reed this dissertation and that in my’ opinion itis fully adequae

In scope and quality as dissertation forthe degree of Doctor of Philosophy

Approved forthe Stanford University Committee on Graduate Studies

Patricia J Gumport, Vice Provost Gra

This signature page was generated electronically upon subsson of thi dissertation ia

ectoni Jorma An orginal signed bard cops a he sgeannrs page iso ite in

University Archives.

“This page is imentonally left blank

Abstract

Abstract

Fash memory isthe most widely used non-volatile information storage device today NAND flash memories are ubiquitous in their use as portable storage media in cellphones, cameras, music players, and other posable eletonic devices In ation NAND fash memory has recently seen rapid option as sista drives (SSD) in place of hardisk dives (HDD) in modem personal computers and data servers, fn sxkition t greater speed and beter endurance agsinst mechanical damage, SSDs also

‘consume moc lesser power than HDs

The NAND flash memory device, consisting of 8 hating-gate transistor ee

Abstract

polysilicon floating-pates becoming ineweasingly ballistic We also experimentally

<demonsteste doping-related issues in te poly-silicon floating-gate,

Finally, in onder to facilitate continued sealing of the contol dielectric, we explore replacement of the conventional siieon oxide-nittide dielectric with high-k

didecuic materials We integrate polysilicon floating-gate cells With ALO; high-k contol delete, and show tha the presence of 2 silicon nie interlayer improves the interface between the floaing-gate and the contol dielectsic We also integste ret floating-gte cells with ALOs contol delete, and these eels exhibit very

goed electrical characteristies, Funther, we establish that deeper work-funetion control gat i helpful in reducing gat-injction,

‘Combining ultra-thin metal Hloating-gate, high-k eontrol dielseie and deep

\work-function control gate, we enable the planar Tloating-gate cell as a scalable candidate

ny topic of work His suppor in encouraging his stunts to explore a range a topics,

is erie to the success and enjoyable experince that his students have T have been very fortunate to have had the best advisor anyone could ope for and it has been an honor tobe part of his itistrious research group

| would ike to express my sincere gratitude to my co-advisor Prof Yoshio Nishi Ihave received many valuable suggestions and feedback from him đường the course of my time at Stanford Tam very pateful 1 have been acquainted with bm

1am indebted to Prof Tejas Krishsamohan for

Acknowledgements

boon exttomely riieal to my progress, I am especially thankful for the long diseussions that we fen hai late in the nigh, n spite of his ineredibly busy schedule

am extremely fortunate 0 have had the opportunity tobe mentred by him

{ wold fke to thank Prof, Pierre Khuri-Yakub for agreeing o hale my oral

am very grtefu t Dr Ann Marshall for her help with TEM imaging {would tke to express my geatitade to Dr fim MeVite and Dr, Erie Pesozelo forall ther help in the lb, Ham very thankful to Pm Teẻ Kamins For the many useful discussions aad

——

All my experimental work was polomned ai the Sunlorl Nanolthieation Fast I would ike wo thank the staf for enabling a world-class esearch elly

Lam very gratefil @ Dr, Prana Kalavade, Dr Krishna Parat, Dr Kiran

Đangal, Dr, Prashant Damle and Dr Sanjay’ Ranga for guidance and support ding my intemsip at Ite

1 have been fortunate «0 have had the support of amazing trends and colleagues over the as fow yeas at Stanford: Abhijit, Albert, Ali, Ammar, Aneesh, Ans, Arunanshu, Arvind, Bob, Caner, ChiOn, Crystal, David, Debbie, Dongtk, Donghyun, Donkoun, Duygu, Ed, Elmer, Emel, BricP, Eunji, Flip, Gail, Gaurav, Girish, Gunhan, Hai, Hemant, Hiro, Hoon, Hoyoe!, Hyun-Yong, Ine, J, ae, Jason, Jeannie, Jenny, Sa, Jim, Jir-hong John, Jungyup, Kavya, Kiran, Kishore, Krishna,

Kycongran, Kyung-hoa - Lan, Mabnaz, Manat, Manoj, Marika, Mary, Masshara, Masato, Maurice, Mihir, Munchiro, Nancy, Nevran, Nishant, Onue, Paul, Pawan, Peter, Pranav, Prasanthi, Prashant, Raghav, Raja, Rajesh, Ray, Rishi, Robin, Rohit, Rostam, Roozbeh, Sangbum, Sanjay, Sarves, Shankar, Serene, Shreekar, Simon,

Acknowledgements

Suman, Sunantà, Suyog Swaroop, Szu-lin, Shen, Ted, Ui, Wooshtk, Yasuhio, Yeul, Yuan, Yuniano,Z

No womds would ever do justi to express my deepest thanks an gratitude 0

my most wonderful family ~ my parents and my’ sister Their unconditional love, sacrifice, support aad encouragement have allowed me to pursue my ambitions,

Acknowledgements

“This page is intentionally let blank

(Chapter 2~ Flash Memory: Operation and Seal

1

‘Table of Contents

Table of Contents

5.3 Ballistic Component in Metal Foating-Gates ss 105,

63 _ Choice of high-k dielectri for IPD application 125

66 Combe

List of Tables

List of Tables

“Table 2.1: Major differences between NOR and NAND flash memories Table 5.1: Work-funetions and Fermi energies of some elements [5.11, 5.12] Table 6.1: Commou high-k dieleeties [6.14]

List of Figures

List of Figures

Figure IL Applications of Mash memory

Figure 1,2: Demand for NAND flash memory (Souree: Gartner May 2008,

Semiconductor Forecast Database (SEQS-WW-DB) 1.21)

Figure 2.2: Semiconductor memory market for flash, DRAM and SRAM (Source

Figure 24 Band diagrams for the neutral state (eft) snd charged state (ight of the

Figure 2.9: NOR Mash progeamoning using CHEE injection [Source nel 22 Figure 2.10: A sohematic energy band diagram describing the three presses

Figure 2.11: AN tuneling of electrons fom the poly-Si BG nto the Si substrate through the angular energy barter posed by the tno (Source: 2.12) 24 Figure 2.12: BN oneling current asa function of elec fet tSouce: (2.12)

List of Figures Figure 2,18; NOR flash ITRS Sealing Projection [2.36} 33

Figure 2.19: TRS Sealing projections for floatng-gate NAND Hash, [23MJ 36 Five 32: Foaing-gate interference eauses undesirable shi in tnesbold voltage of

Figure 3.3: This figure depicts the shifting of threshold vohage of Cell 1 when Celt? _s programmed duc to the porstic coupling between the adjacent cells, Source:

Figure 3.8: Interference along BL direction and WL diteston [3.11] a7 Figure 39: CG no longer hs space io wrap around BG thereby leading a serious

Figure 3.10 Image showing that the distance between cols s extremely less (Source:

Figure 3.17; Erasing characteristics of 15 nm naype polysilicon longa 58

Figure 3.18; Programming characteristics for various thicknesses of n-type poly=

Figure 3.20: Retention for n-type poly

Figure 4.1: Schematic hand diagram of balls € transport and emission via multiple lunneling through intercongected nanoerysiallites in porous silicon under a high

Figure 4.2: Band diagram deseribing balistie transport during programinitg 10 Figure 4,3: Test Structure used 10 study ballistic transport 7 Figure 4.4: Band diagram during measurement at low FG bias, Substrate is grounded

Figure 4.5: Shows the IPD leakage current atthe star of measurement 4 Figure 46: Band diagram of measurernent at high FG bias, 15 Figure 4.7: Shows schematies of expected eurtents at mid-to-high loating-gatebins.75 Figure 4.8: Schematic of expected currents during the ballistic current measurement

‘gale sample for structures with ilferent active areas, 83

Figure 415: fnlatic mean free ath extraction by slope of ballistic component versus

Figure 4.16: Cyeting data (+ {4 V, 100 ms) on 75m, 10am and 7 nm polysilicon foating gate devices The 7m Hosting gate devices shaw more degradation 86 Figur 417: Cyeting ata (+17 V, 100 is and 14 V, 100s) on 75m and T0 an polysilicon Roating-gate devices, The 10 nm floaing-gate devices show more

Figure 4.18: Capacitanee-Vollage curves of eycied devices indicating more

degradation inthe 10 nn polysilicon floating-gate device compared to the 75 nen

gu 4 I; The poly-depieion le, Dục the depletion in the polysilicon get, the elfective onide thickness increases and the elective capacitance decreases, Source:

List of Figures

Figure 4.21: As result ofthe poly- depletion, there isa decreased field across the tunnel oxise which makes th erase slower: Souree: [4,15} ° igure 4.22: Shows the capacitance-voltage plots for poly-silieonfoating-gate

devices, The 7 nm device shows a charaeterstic poly depletion dip in the capacitance,

93 Figure 4.23 The poly-depietion effect is mich more pronounced for larger emolated

Figure 424: Medici simulation potential contours fr depleted and undepleted FO

‘Shows eee of emulated wrap i amplifying polý‹lepleion % Figure 425: Shows slower programming in 7 nm polysilicon loating-gate device de

Figure 5.1: Floating gate capacitor structure used to study programverase and

vcliabilty performance of meta ating: gate deviees la Figure 52: TEM of @ mealTiPU Hoating-gate device gate tack 103 Figur 5.5: Programming characterises of HP Moatng-zate device os Figure $4: Erasing characteristics of Ti loating-pate device 10s Figure 8.5: Siete with floating gate conte! used to meas te ballistic

Figure 5.46: Balisti component measurement data on 7 nm TiPE metal floating-gate sample, The metal as moh lower halistie component compare to polysilicon of

List of Figures

Figur 87: Povcentageof ballistic curent pled versus flosting-gte thickness fora

‘variety of materials In general it ean be observed that metals have lowerballisie

‘component compared to polysilicon defo inereased inelastic electron seaterng 107 Figure 5.8: Shows the definition of work-funetion and Fermi energy in a metal Also shows the density of states (DOS) versus energy 108 Figure 59; Capacitance Voltage pot of 3 nm TIN FG capacitor showing no

Figure 510; Flacand voltage versus programming time for 3 now TIN FG sample

‘There sno low-down in the beginning as observed with depleted polysilicon

Figure 8: Band digrams showing that deeper Work-funeton FG leads to slower

«ase, Top figure shows shallower work-function BG device and bots igure shows deeper work function FO device Deeper work- function FG has larger bares to

Tai 5 1: Band diegrams shoving hat deeper work-funetion FG leads to better retention, Top figure shows shallower work-funetion FG deviee and bottom Figure shows deeper work-funeton FG deviee, Deeper wark-funetion FG device stores

Figure 5.13: Shows deeper work-funetion (Pt) FG device erase slower than shallower

Figure 5.1: Programming characteristics of 3am TIN EG device showing excellent

Figure 62: CG no longer has space to wrap around FG thereby leading toa seiows

Figure 6.3: Image shows that the distance between cll is very less (Source: [6.12])

124 Figure 6.4: Shows erae-sturation occuring as a result of gatedinjection A larger conduction hari height of the IPD would reduce ijetion fom the conzo-gate, 126 Figure 65: Common high-k dieletis In general, larger the dielectrie constant,

Figure 66: TEM image of the gatestck a polysilicon FG ALO: high-k IPD

Figure 67: Program characteristics oF 60m polysilicon oating-gate deviees with

Figure 6: Erase characterises of 0 nm polysilicon Hetin-gte devices with

Figure 69: Cyetng data on 60 nn poly-siticon FG ALOs high-k IPD samples with

and without nitride inte

List of Figures

Figure 6.11; Program eharacteristes of polysilicon FG devices of various thicknesses

Figure 612; rose characterises of poy-silicon FG deviees of sarious thicknesses

Figure 6.13: Cycling data of 60 nm and 7 nm poly-silicon FG devices with

nitrides ALO high-k IPD, The 7m polysilicon FG sample performs worse

Figure 64s TEM image of «TIN Hosting-gate device with ALO) high-k IPD 135 Figure 615: Program characterises of TaN FG compared to polysilicon FG, both

Figure 616: Erase of TAN FG compared to ply silicon PO, oth wit high IPD 137 Figure 6.17: Retention of TaN FG device with high-k IPD 137 Figure 618: Endurance data for TaN FG deviee with ALOs high-k IPD 138 Figure 6.19: Band diagrams depicting deeper work function metal with lesser pate

Figure 6.20; PLCG (deeper work-funetion) showing improved erase saturation

Figure 7.1: The planar (no wrap) floating- gate device 146 Figure 7.2: Non-volatle memory potential solutions (Source: TRS 209) "g

Common Abbreviations Used

Common Abbreviations Used

EN | FowerNonheim GER | Galesoupling ratio SSD | Solid-state dive

MLC ‘MulicTevel ceil

Flash Memory Applications

‘a 2

lá

Chapter |= Introduction

FD,

eat manne

Figue Word-wie data centr power savings wth SSD compe Yo HDD (Source: Samsung

In order to Keep up with the demand for inereased memory’ capacities, flash memory has been continuously sealed (Figure 1.5) to smaller and smaller dimensions

Figure LS: Sang of NAND fas nemory The pe is 2X yo your ‘eng lo Moore's a (Sour Simsing) pose 02K every 1S years

Further scaling of NAND flash memory faces serious roadblocks Some of the biggest challenges include increased parasitic Hoaing:gate (FG) interferences and decreased gate-coupling rato (due to lack of space for conro-gate (CG) wrap around the loating-gate) [1.5] These arise due othe ulira-high density-scaling requirements

‘of NAND flash memory This thesis deals with these serious challenges in the continued sealing of NAND flash memory technology and demonstates novel

solutions to overcome them,

Chapter | Intolueion 1.2 Thesis Organization

‘This thesis organized into seven chapters, ieluding this intoduetion chapter

ln chapter 2, bref overviews of flash memory history, operation and seating s1e presented The “eating ate tansistr* cell is intxduced with its operation Principle, The types of flash memory are described and the main charge injection mechanisms ave discussed Then, reliability considerations of flash memory are biely deserted, followed by the sealing tends and the main seting challenges of fash

Chapter 3 studies polysilicon flaating-ate devices with vertical sealing ofthe floaing-gate In the Fist section, the celltowel interference challenge in scaling NAND flash memory is discussed, which motivates thickness scaling ofthe Noating-

fale, Subsequenlly the test structure use for (hs study, and the fabrication of sealed

poly-silicon floating-yate devices are deseribed This i followed by detailed analysis, for the correlation in progeamferase/etention characteristics between devices with poly silicon Moating-gatethieknesses eanging from 75 nm to ưa tin 7 an,

In chapter 4, important challenges to the sealing of the poly icon faking: pate thickness are discussed, A new reliability concen, arising from the programming current increasingly going ballisically ehough the ulưedhin hating gate, is described, A new test structure is developed 10 experimentally investigate this phenomenon Experimental resus are presented which quantitatively desribe the

‘magnitude of the effect, The implication of this effect is shown by means of endurance

(Chapter | - Introduction

data, whieh show thinner Mloating-gate devices degrading faster ‘This setiablity concen poses a major sealing challenge Following the discussion of this problem, other sues of doping that fit ulte-thin polysilicon Mloating-gates are discussed,

In chapter 5, the use of 4 metal floaing-gate a8 a replacement for polysilicon

is explored, The metal floating-gate is experimentally demonstrated to provide excellent electrical performance The metal floatng-gate can also provide soltion to

te balisie cmer and ply-depletion issues discussed in chapter The factors underlying the choice of metal are discussed in detail Prom the various options available, THN (or TaN) i ehosen asthe prefered lating-gate, The THN Haaing-ge

is scaled downto ultesthin 3 nn, with excellent electrical performance a even such thicknesses Usilization of an ultra-thin neal Hating gate greatly seduces cello

`

fn chaper 6, the replacement of the conventional oxide-nitide cont! dielectric with high dietetic is explored The motivation to use high-k eontol {ictecti sto improve the gate-coupling ratio (GCR), which i lowored as a result of the inabitty 1 wrap the conto gate around the floatng-gate, The requirements ofthe

high mae I for contro dielectric appliestion are enumerated ALO, is chosen as the high-k contol dietetic material for experimental demonsteation Poly-siieon Aoatng-gate devices are integrated with Al,O; contot dices, and their electrical characteristics are presented, The usefniness of a silicon nitride interlayer is proven, and metal (TaN) floaing-gnte is integrated with ALO, control diclece Finally, the

role ofthe coniol-pate work-funetion is discussed.

Chapter | - Introduction

In chapter 7, the conclusions and future directions ate discussed, in whieh the planar flating-gate device is proposed with ultrs-thin metal Hoating-gate, high-k contol dieletic and deep work-funetion conirol-gote Finally, directions for future research ate discussed,

[14] Hiang’s Law was named afier Hwang Chang-gy, former head of

Samsung Bleetonies’ semiconductor business

[15] K.kim et, al, "Memory Technology in the future", Mieroslectconic Engineering, vol84, p.1976, 2007,

(Chapter 2 ~ Flash Memory: Operation and Scaling

scaling trends and main sealing challenges,

2.2 What is Flash Memory?

Flash memory isa type of non-volatile memory [2.1] A non-volatile memory deviee is one that can reain stored information in the absence of power (figure 2.1)

Chapter 2 ~ Flash Memory: Operation nd Sealing

Other examples of non-volatile memory include read-only-memory (ROM), hard disk drives, floppy disk, optical dises ete

trea [FLASH — ]9S9wmmbsed ‘mabe nyse

17 /cott [EPROM | Proganmaie ret

ceerenlyeresie ROM] Na deetcdlyproganrsske neusagy

tực 31: Natsolatle MOS memory quae comparison othe Mexico plane From 2.1)

The first category of non-volatile MOS memories consists of ROMS, in which

te dâm is penmamemly wdHen dường manalaetơine While these ate very inexpensive, they completely lack flexibility a8 the data cant be altered hy wer

‘The firs oating-pate memory deve was inialaced by Kahog and Sze [2.2] i 1967

In 1970, Prohman-Bentchikowsky (2.3) developed a polysilicon Moating-gte

twansisor In this device, hot electrons are injected into the Hoang gate and removed

by ulleavotet (UV) photoemission, This device was called the erasable programmable read-only memory (EPROM) or UV-EPROM, While this deviee provided more Aesiility, it needed to be removed from the system 10 e1ase it by exposure 10 UV lig

Following this, there was & Jot of effort te develop clecrically erasable

programmable ROMs (EEPROMs) (2

5) The EEPROM ell, consisting of wo

(Chapter 2 ~ Flash Memory: Operation and Scaling

transistors and a tuanel oxide was developed, While this had byte-rewrite and erase

<apabiliy, it as a larger el since it consisted oF two tassios,

Subsequently, the fssh-EEPROM was developed by Toshiba [2.6] in 1984, A single-transistor cell was achieved by means of hot earier programming and tunnel

‘erase, Acconding to Toshiba, the same “Rash” was suggested because the erasure process of the mieory contents feminde then ofthe Hash ofa camera,

The fies commercial ash memory chip was produced by Intel in 1988 (2.7, 2.8) This wasa NOR-Iype flash memory chip where theres dresses to each cl

‘The fist NAND-ype Mash memory optimized for higher density was developed by

“Toshiba in 1987 [29] The growth of fash memory was sluggish initially due to reliability problems but took off dramatically ater 2000 due to iyprovements in

manufacturing process and reliability echnolagy (igure 2.2),

[Chapter 2~ Flash Memory: Operation and Sealing

2.3 The Floating-gate Cell

[A simple floating: gate transistor cells shown in Figure 23

‘The name originates from the fact thatthe erase operation and in some cases, the program operation, occurs through this oxide using quantum mechanical tunneling.

(Chapter 2 ~ Flash Memory: Operation and Scaling

‘The source and drain are typically nt ype and the substrate is prype (NMOS transistor

"The oating-gsie serves as the charge storage node, This electrode is capacitively coupled to the eontol-gate and other nodes During the programing

‘operation, charge is injeted into the (loaing-gate from the substrate using some meshsiem, usally hotelectron injection or teaneing The charge i sense as sift

in the threshold voltage the turn-on voltage) of the wamsstor The charge is removed from the oatng-gate by tuning through the tunnel oxide back into the substrate Figure 2.5 shows the band diagrams forthe charged and neutral sates ofthe Maating-

Chapter 2 ~ Flash Memory: Operation nd Sealing

the charged state, there ae eleetons on the Heating: gate which raises the potential of the fToating-gate, The potential well toxmed hy the dielecties on either side of the Aoating-pate, enables ito retain charge

Figure 25: Schema hing the cate coupling he sting (Some (2.12)

Figure 2.5 is a simple schematic of the oating-gate trnsisior whese the various capacitive couplings lo the Moating-gate are shown, The floating gate is capacitively coupled not only to the contol gate, but also to the source, drain and body of the transistor Folfowing [2.12] consider the ease when thee is no charge on

Cols the capacitance between Moating-gate and dein

(Chapter 2 ~ Flash Memory: Operation and Scaling

Css the capacitance betwen Hoating-gete and body

Voc is the potential ofthe floating-zate

eas the potent ofthe contol gate

Vis the potent ofthe drain

Vis the potential ofthe source

Vo isthe potential of the boxy

MCrae= Cre # Co Ce-4 Cy = Total FG capacitance,

Then

Vio=GCR Veo + DCR Vo+ SCR Vs # BCR Va Where

GR = Gate coupling ratio= Cref'Cru

DCR = Drain coupling ratio= Caf Cre

SCR ure coupling ratio= C= Cre

BOR = Body coupling ratio = Cy Cx

2.3.1 Gate coupling ratio (GCR)

‘The Gate coupling ratio (GCR) is very important parameter inthe design of fash memories, I is a measure of how sieongly the contzol gate is coupled 10 the foating-gate and as a consequence, it determines the electric fields across the tunnel

‘oxide and the conteol oxide, The fied across the tunnel oxide is tical to the speed of

‘operation of the deviee, A device with a lower GCR would operate at lower unset

Chapter 2 ~ Flash Memory: Operation nd Sealing

oxide fells compared t a device with higher GCR, at he same votages Thereloe the deviee with lower GCR neods higher vollages 1 eperste atthe same speed (the same tunel oxide fick This also means thatthe fe inthe HPD would be larger Which is undesirable

The GOR has been increased in flash memories by wapping the control-zate around! the flowing-ate ((2.13) However, dục to increasing density of ells in NANDuype ays, there i no longer enough space 10 wrap the contolgate around the floatng-gate,thezehy leading to a large decrease in GCR This probless and the solution wil be disused nthe following chapters

An important point to note is that, i today's high density arrays, the floating

pate is also capacitvely coupled © adjacent foating-gates and other electrodes of adjacent eels esusing interference in their operation, This has not been considered in the simple mathematical approach desevibed above, This parasitic capacitive coupling boteen neighboring cells has started to become a significant fection af the overall coupling and this is one of the biggest eallonges Facing high-density NAND flash

‘memory technology today

2.4 Read Operation

“The state of the Moating-gate transistor is ascertained ftom the threshold valiage of the FG MOS transistor From elementary MOS theory [2.14}, itis known