Tài liệu How semiconductors are made doc

Photomask Creation After design of the logic circuit and the layout, a photomask is required to transcribe the design onto the wafer for use during front-end processing.. Process 2:Dep

How semiconductors are made

Minhhuan4_9@yahoo.com

 Part 1: Mask design creation

 Part 2: Front end Processing

 Part 3: Back end processing

Design/mask creation

 Circuit design

 Photomask creation

Logic Circuit Design / Layout Design

 Based on the development plan, the IC's function and

performance are first decided, and the logic circuit is

designed During logic circuit design, a logic circuit diagram

is drawn to determine the electronic circuit required for the requested function Once the logic circuit diagram is

complete, simulations are performed multiple times to test the circuit’s operation If there is no issue with the

operation, the actual layout pattern for the devices and the interconnects is designed by computer-aided design(CAD), and a mask pattern is drawn

Logic Circuit Design / Layout Design

Photomask Creation

 After design of the logic circuit and the layout, a photomask

is required to transcribe the design onto the wafer for use during front-end processing The photomask is a copy of the circuit pattern, drawn on a glass plate coated with a metallic film The glass plate lets light pass, but the metallic film

does not A state-of-the-art mask drawing system is used

for the pattern exposure of the photomask Due to

increasingly high integration and miniaturization of the

pattern, the size of the photomask is usually magnified four

to ten times the actual size, depending on the irradiation

equipment

Photomask creation

Front end processing

 Wafer fabrication

 Deposition

Process 1: Wafer Fab

 A thin, circular slice of semiconductor material is

called a "wafer", and is used as the substrate in IC manufacturing A high-purity, single-crystal silicon called "99.999999999% (eleven-nine)" is grown

from a seed to an ingot, after which its ends and individual wafer discs are sliced off The wafers are generally available in diameters of 150 mm, 200

mm, or 300 mm, and are mirror-polished and

rinsed before shipment from the wafer

manufacturer

Wafer Fab

Process 2:Deposition

 When the wafer is ready, the next step is the patterning of the circuit pattern designed in the "design / mask creation" step Before patterning, the wafer is placed in a high-temperature furnace to make the silicon react with oxygen or water vapor, and to develop oxide films on the wafer surface (thermal

oxidation) These oxide films are used for the insulation of

transistor gates and for the insulation of interconnect layers

To develop nitride films and polysilicon films, the chemical

vapor deposition (CVD) method is used, in which a gaseous reactant is introduced to the silicon substrate, and chemical reaction with the substrate surface is prompted by high

temperature or plasma The metallic layers used in the wiring

of the circuit are also formed by CVD, spattering (PVD:

physical vapor deposition), or other plating methods

Film oxide

 At 900-1200 C with H2O or O2 in oxidation furnace

2 2

2

2 2

H 2 SiO

O H 2 Si

SiO O

Deposition

Process 3: Photoresist Coating

 The lithography method, which irradiates (cho anh sáng rọi vào)the wafer past a photomask, is used for patterning In preparation for this process, a

resin(nhựa) called "photoresist" is coated over the entire wafer Photoresist is a special resin similar in behavior to photography films that changes

properties when exposed to light A drop of liquid photoresist is dripped onto the wafer surface as

the wafer is rotated at high speed on the coating machine, resulting in an approximately 1μm thick m thick coating

Photoresist Coating

Masking / Exposure

The photomask created in the "design / mask creation" step

is placed over the photoresist-coated wafer, which is then irradiated to have the circuit diagram transcribed(sao chép) onto it The positions of the wafer and the mask are

adjusted, and then an irradiation device called the "stepper"

is used to irradiate the wafer through the mask with

ultraviolet (UV) light Where unmasked, the wafer is

exposed to the UV light, and the exposed photoresist

changes chemically The mask is four to ten times larger

than the actual size of the circuit, so the stepper lens must

be adjusted to 1/4 to 1/10 magnification before being

projected onto the wafer The procedure is repeated for the entire surface of the wafer

The photoresist chemically reacts and dissolves

in the developing solution, only on the parts that were not masked during exposure

(positive method) Development is performed with an alkaline developing solution The

developing solution dissolves the parts of

photoresist that were chemically changed by exposure to light After the development,

photoresist is left on the wafer surface in the shape of the mask pattern This is called the

"resist pattern"

Development

 Etching" refers to the physical or

chemical etching of oxide films and

metallic films using the resist pattern as

a mask Etching with liquid chemicals is called "wet etching" and etching with

gas is called "dry etching" The oxide

films are etched with chemicals (HF

acid), and the metallic films are etched with plasma

Etching

Photoresist Stripping

 The photoresist remaining on the wafer

surface is no longer necessary after etching is complete Ashing by oxygen plasma or the

likes is performed to remove the residual

photoresist The wafer is also rinsed with an acidic solution to remove any impurities, such

as metals and organic matters The steps

from deposition to photoresist stripping are repeated multiple times to form a complex

circuit pattern on the wafer

Photoresist Stripping

• n-well formed with diffusion or ion implant

• Diffusion

– Place wafer in furnace with arsenic gas

– Heat until As atoms diffuse into exposed Si

• Ion Implantation

– Blast wafer with beam of As ions

– Ions blocked by SiO2, only enter exposed Si

Strip Oxide

Strip off the remaining oxide using HF

• Back to bare wafer with n-well

• Subsequent steps involve similar series of steps

 Deposit very thin layer of gate oxide

 – < 20 Å (6-7 atomic layers)

 • Chemical Vapor Deposition (CVD) of Si layer

 – Place wafer in furnace with Silane gas (SiH4)

 – Forms many small crystals called polysilicon

 – Heavily doped to be good conductor

Polysilicon Patterning

 Use same lithography process to pattern polysilicon

• Pattern oxide and form n+ regions

• Polysilicon is better than metal for self aligned gates because it doesn’t melt during later processing

N-diffusion, Cont’d

• Historically dopants were diffused

• Usually ion implantation today

• But regions are still called diffusion

N-diffusion, Cont’d

 Strip off oxide to complete patterning step

• Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

Now we need to wire together the devices

• Cover chip with thick field oxide

• Etch oxide where contact cuts are needed

- Sputter on aluminum over whole wafer

- Pattern to remove excess metal, leaving wires

Wafer Inspection

 Each IC on the completed wafer is

electronically tested by the tester After this inspection, the front-end processing is

complete The tester checks the operation of the IC chips by sending electronic signals

through a set of probes called the "prober", that are connected to the bonding pads

(terminals) of the IC chips

 In back end processing, a wafer completed in front end processing is cut into individual IC chips and encapsulated into packages The cutting of the IC chips is called "dicing" The wafer is first ground to a thickness suitable for cutting (approximately 300μm thick m), after

which a piece of UV tape is adhered to its

backside, fixing it to a table An extremely

thin circular blade covered with diamond

grains (dicing saw) is used to cut the wafer apart

 After the IC chips are cut apart, they are sealed into packages The IC chips must first be attached

to a platform called the "lead frame" This

procedure is called "mounting" A lead frame

consists of a mount for the IC chip (the "island") and connections for the chip's terminals (the

"leads") Silver paste resin is applied onto the

island, and then the IC chip is adhered by lightly pressing it onto the island

terminals are connected to the lead frame leads with gold fine wires

Encapsulation and

Decoupling

 The IC chips and the lead frame islands are

encapsulated with molding resin for protection This keeps the IC chips safe from dust and

moisture The lead frames with an IC chip

mounted are placed on a mold, and then

encapsulated with resin made liquid at high

temperature Finally, the lead frames are cut apart into individual packages

Characteristic Selection

 The packaged IC chips are tested and

selected The IC chips are tested by direct current (DC) characteristics and function

characteristics The IC chip packages are

individually set on a tester, and their DC

characteristics and function characteristics are tested according to a program prepared

in advance

Printing and Lead Finish

 The final step of IC chip manufacturing is the

printing onto the package surface and the finishing

of leads After this step, the IC chips are complete Printing is performed by engraving the top few

micrometers of the package surface with a laser Information such as manufacturer name and

product code is printed Finally, the leads

protruding from the packages are shaped into the final product form

Printing and Lead Finish

 Before the IC chips are shipped, several

final inspections are performed as sampling inspection The exterior is checked for

scratches and stains, dimensions and

shape of leads, and prints Final inspection

of electrical characteristics is also

performed

Packing and Shipment

 IC chips are packed for shipment

Inspected IC chips are stored in trays and magazines Cushioning materials are placed between external packages to prevent

degradation of quality from impacts while

in transport The outer boxes are labeled

with the name and quantity of the product, and then shipped

Packing and Shipment