The binary logic operations are carried out in the statement list using the AND, OR, and exclusive OR statements. The binary tags for the logic operation can be scanned for signal state “1” or “0”. The binary operations can be “nested” using parenthe- sized expressions and thus influence the processing sequence (Table 9.1).
9.2.1 Processing of a binary logic operation, operation step
A binary logic operation consists of scan operations and conditional operations.
The sequence of scan operations and subsequent conditional operations is referred to as an operation step (Fig. 9.3).
The first scan operation processed following a conditional operation is the first input bit scan. This is of special significance because the control processor directly imports the scan result of this statement as the result of logic operation. The “old” result of Fig. 9.2 Components of an STL statement
M001: L %IW 12 //Load analog value 1
Structure of an STL statement
logic operation is thus lost. The first input bit scan always represents the beginning of a logic operation. The logic operation (AND, OR, exclusive OR) specified in the first input bit scan does not play any role here.
The result of logic operation is generated by the scan operations. You scan the signal state of a binary operand for “1” or “0” and link it according to AND, OR or exclusive OR.
The result of this logic operation is saved by the control processor as the new result of logic operation.
Table 9.1 Binary logic operations with STL Operation Operand Function A
AN O ON X XN
Binary operand Binary operand Binary operand Binary operand Binary operand Binary operand
Scan for signal state “1” and link according to AND logic operation Scan for signal state “0” and link according to AND logic operation Scan for signal state “1” and link according to OR logic operation Scan for signal state “0” and link according to OR logic operation Scan for signal state “1” and link according to exclusive OR logic operation Scan for signal state “0” and link according to exclusive OR logic operation A(
AN(
O(
ON(
X(
XN(
)
– Left parenthesis with AND logic operation
Left parenthesis with negation and AND logic operation Left parenthesis with OR logic operation
Left parenthesis with negation and OR logic operation Left parenthesis with exclusive OR logic operation
Left parenthesis with negation and exclusive OR logic operation Right parenthesis
O – ORing of AND functions
NOT SET CLR
– Negation of result of logic operation Set result of logic operation to “1”
Set result of logic operation to “0”
Fig. 9.3 Binary logic operation with STL, definition of operation step
operation step
first scan
scan operations
conditional operations Operation step
= "Fan1"
...
U "Auto_on"
U "Manual_on"
= "Display"
O ...
U "Fan1"
U "Manual mode"
S "Fan2"
...
UN "Manual mode"
U "Enable"
...
Conditional operations are operations whose execution depends on the result of logic operation. These are operations for assigning, setting and resetting binary operands, for starting timers and counters, etc. The conditional operations (apart from a few exceptions) are executed if the result of logic operation (RLO) is “1” and not executed if RLO is “0”. They do not change the RLO (apart from a few excep- tions), and therefore the RLO is the same for several successive conditional opera- tions.
Understandable programming
The logic operation specified for a first input bit scan is of no importance since the result of the scan is imported directly as the result of logic operation. To make the programming understandable, the logic operation specified for a first input bit scan should be identical to the desired function.
As an example, the sequence of statements
represents two AND functions, where you should prefer the programming of the second AND function in which both scans are programmed according to AND.
For individual scan statements, the AND function is preferred, for example with
9.2.2 Scanning for signal states “1” and “0”
Before the scan operations link the signal states together, they scan the status of the associated binary tags.
The status of a binary tag is identical to the signal state of the binary tag. This can be “0” or “1”. The physical variable at the module terminal for which an input has signal state “1” or “0” depends on the type of input module (see Chapter 12.1.2
“Working with binary signals” on page 462).
Strictly speaking, the control processor does not link the signal state of the binary tag scanned, it initially generates a scan result. When scanning for signal state “1”,
...
= #Fan1.start O #Enable A #Fan2.on S #Fan2.start
//First AND function
A #Enable A #Fan2.off R #Fan2.start
//Second AND function
...
...
= #Fan1.display A #Fan2.running
= #Fan2.display
//Scan of #Fan2.running with //assignment to #Fan2.display ...
the scan result is identical to the signal state of the binary tag scanned. When scan- ning for signal state “0”, the scan result is the negated signal state of the binary tag scanned. Scans for signal state “0” have an “N” following the specified logic opera- tion (AN, ON, XN). The control processor generates the result of logic operation from the logic operation of the scan results.
The result of logic operation (RLO) is the signal state used by the control processor for further binary signal processing. The RLO contains the state of the binary logic operation: “1” means that the operation is fulfilled; “0” means that the operation is not fulfilled. The result of logic operation is used to set or reset binary tags.
The example in Fig. 9.4 shows the two “Start” and “Stop” pushbuttons. When pressed, they output the signal state “1” in the case of an input module with sinking input. The SR function is set or reset with this signal state.
The “/Fault” signal is not active in the normal case. Signal state “1” is then present and is negated by scanning for signal state “0”, and the reset operation therefore remains uninfluenced. If “/Fault” becomes active, the “Fan” tag is to be reset. The ac- tive signal “/Fault” delivers signal state “0”, which by scanning for signal state “0”
activates the reset operation as signal state “1”.
9.2.3 Programming a binary logic operation in the statement list
The program editor creates a two-line input field in an empty network into which you can enter the STL statements.
Following input of the operation in a line, enter a space and then – if necessary – the operand; in the case of a binary logic operation, enter a binary tag from the op- erand areas: inputs, outputs, bit memories, and data. Binary logic operations can Fig. 9.4 Scanning for signal states “1” and “0”
"Fan"
%I1.3 %I1.2 %I1.1
%Q4.
L+
G 1
"Start"
"Stop"
"/Fault"
Example of scans for signal state "1" and signal state "0"
U "Start"
O "Stop"
ON "/Fault"
S "Fan"
R "Fan"
also be used to scan SIMATIC timer and counter functions, and status bits. The pro- gram editor supports you during input of operands by displaying all suitable, previously programmed tags following input of the first character.
In the same line you can enter a comment, separated by two slashes, up to the end of the line.
You terminate the binary logic operation with one or more conditional operations.
You can start the next logic operation directly in the next line, or you can leave an empty line for clarity reasons. You can also commence a new network.
9.2.4 AND function
An AND function is fulfilled if all binary tags have the scan result “1”. A description of the AND function is provided in Chapter 12.1.3 “AND function, series connection”
on page 464.
Fig. 9.5 shows an example of an AND function. The #Fan1.running and
#Fan2.running tags are scanned for signal state “1”, and the two results of the scans are linked according to an AND logic operation. The AND function is fulfilled (deliv- ers signal state “1”) if both fans are running.
9.2.5 OR function
An OR function is fulfilled if one or more inputs have the scan result “1”. A descrip- tion of the OR function is provided in Chapter 12.1.4 “OR function, parallel connec- tion” on page 465.
Fig. 9.5 shows an example of an OR function. The #Fan1.running and #Fan2.running tags are scanned for signal state “1”, and the two results of the scans are linked according to an OR logic operation. The OR function is fulfilled (delivers signal state
“1”) if one of the fans is running or if both fans are running.
9.2.6 Exclusive OR function
An exclusive OR function (antivalence function) is fulfilled if an odd number of inputs has the scan result “1”. A description of the exclusive OR function is provided
A #Fan1.running A #Fan2.running
= #Display.twoFans //Two fans are running O #Fan1.running
O #Fan2.running
= #Display.MinOneFan //At least one fan is running X #Fan1.running
X #Fan2.running
= #Display.oneFan //Only one fan is running Fig. 9.5 Example of binary logic operations with STL
in Chapter 12.1.5 “Exclusive OR function, non-equivalence function” on page 465.
Fig. 9.5 shows an example of an exclusive OR function. The #Fan1.running and
#Fan2.running tags are scanned for signal state “1”, and the two results of the scans are linked by an exclusive OR logic operation. The exclusive OR function is fulfilled (delivers signal state “1”) if only one of the fans is running.
9.2.7 Combined binary logic operations
The AND, OR, and exclusive OR functions can be freely combined with one another.
The control processor processes an AND function with higher priority than an OR function (ANDing before ORing, like in the notation of Boolean algebra). The exclu- sive OR function has the same priority as an OR function.
The parentheses operations and the individual OR logic operation are available to bypass this processing priority.
ORing of AND functions
The individual OR logic operation O links the results of two AND functions.
Fig. 9.6 shows two AND functions with two inputs each, and the results of the logic operation are linked according to an OR logic operation. The first AND function is fulfilled if fan 1 is running and fan 2 is not running, the second function if fan 1 is not running and fan 2 is running. The #Display.oneFan_1 tag is set if the first AND function is fulfilled or if the second AND function is fulfilled (or if both are fulfilled, but this is not the case in this example).
ANDing of OR functions
A parenthesized expression is required for the ANDing of OR functions. The OR functions are written in parentheses, and their results of the logic operation are linked to the operation present next to the parentheses (the AND function in this case).
Fig. 9.7 shows two OR functions: The first one is fulfilled if at least one fan is run- ning or if both fans are running, the second one if at least one fan is not running or if neither fan is running. Each OR function itself stands in a parenthesized expres- sion. The logic operation results of the OR functions are – due to the operation “A(”
A #Fan1.running AN #Fan2.running O
AN #Fan1.running A #Fan2.running
= #Display.oneFan_1
//ORing of AND functions
//Only one fan is running Fig. 9.6 Example of ORing of AND functions
– connected according to AND. The #Display.oneFan_2 tag is set if only one of the fans is running.
Parenthesized expressions in binary logic operations
The example in Fig. 9.7 clearly indicates the generally applicable schema for binary parenthesized expressions. The function to be processed “first” is present in a pa- renthesis. How the result of the logic operation of the parenthesis is to be processed further is shown by the logic operation specified in front of the left parenthesis operation. Fig. 9.8 is a general representation of this schema.
A parenthesized expression can be linked by the operation “A(” according to AND, by the operation “O(” according to OR, and by the operation “X(” according to ex- clusive OR. Just like with scanning for signal state “0”, implicit negation of the sig- nal state is also possible here: The operation “AN(” negates the signal state of the parenthesized expression prior to linking, as do the operations “ON(” and “XN(”.
Any logic operations can be present within the parenthesized expression, including operations with parenthesized expressions. The nesting depth has a value of seven, i.e. a parenthesized expression can be commenced up to seven times without it be- ing necessary to first terminate a parenthesized expression. Any number of paren- thesized expressions can be programmed “in succession” (on one level).
Conditional operations in parenthesized expressions
All STL operations can be programmed within a parenthesized expression. The use of conditional operations such as assignment or setting/resetting is of interest in association with binary logic operations. Note that only the result of logic operation may be linked further which is valid with the right parenthesis operation.
In Fig. 9.9, a memory function is programmed with set and reset operations within a parenthesized expression. The signal state of the memory function must be scanned in order to link it further; this is carried out using the scan operation in front of the right parenthesis operation. The resulting AND function has three in-
A(
O #Fan1.running O #Fan2.running )
A(
ON #Fan1.running ON #Fan2.running )
= #Display.oneFan_2
//ANDing of OR functions
//Only one fan is running Fig. 9.7 Example of ANDing of OR functions
puts: the OR function in front of the parenthesis, the signal state of the memory function in the parenthesis, and the last scan operation with the flashing frequency.
9.2.8 Control of result of logic operation Negate RLO
The NOT operation negates the result of logic operation at any position in an oper- ation. Using the NOT operation it is possible in a simple manner to obtain:
b a NAND function, i.e. a negated AND function, which is fulfilled if at least one in- put has the scan result “0”,
Fig. 9.8 Generally applicable schema for the processing of binary parenthesized expressions
A(
O #Enable_manual O #Enable_auto
) //OR function is first AND input
A(
A #Fan1.start S #Fan1.drive O #Fan1.stop ON #Fan1.fault R #Fan1.drive A #Fan1.drive )
//Set memory
//Reset memory //Scan memory!
//Memory state is second AND input A “Clock 0.5 Hz”
= #Fan1.display1
//Flashing pulse is third AND input
Fig. 9.9 Example with conditional operations in a parenthesized expression Processing a binary parenthesized expression
Logic operation 2 Logic operation 1
...
...
Parenthesis function (
Further logic operation ...
...
) ...
...
b a NOR function, i.e. a negated OR function, which is fulfilled if all inputs have the scan result “0”, and
b an inclusive OR function (equivalence function), i.e. a negated exclusive OR func- tion which is fulfilled if an even number of inputs has the scan result “1”.
The response of the negation is described in Chapter 12.1.6 “Negate result of logic operation, NOT contact” on page 466.
Fig. 9.10 shows a NOR function. The OR function is not fulfilled if none of the fans is running, and then delivers the signal state “0”. This is negated and assigned to the #Display.noFan tag.
Set and reset RLO
The SET operation sets the result of logic operation to “1”. The CLR operation sets the result of logic operation to “0”. SET and CLR terminate an operation step (Fig.
9.11).