You program a step together with the subsequent transition. These are always han- dled in pairs. The step can remain empty if no actions are envisaged at the current position in the sequencer. The subsequent transition is then valid immediately. It is also possible to program an “empty transition” without step enabling conditions.
This is then fulfilled immediately when processing.
Fig. 11.5 shows the components of a step/transition pair. With an alternative branch, the first transitions of the branches are counted to the previous step. When combining a simultaneous branch, the common transition is displayed in each case with the last step of a branch.
Interlock
An interlock condition is specific to a step. If the interlock condition is fulfilled (this is the “good case”), the actions depending on the interlock are carried out for the active step. If the interlock condition is not fulfilled, the actions depending on the Fig. 11.5 Components of a sequence step/transition pair
Functions in a step/transition pair
Interlock (step interlocking)
Supervision (step monitoring)
Actions
Step enabling conditions
( )C
( )V
E -(C)-
E -(C)-
Q Q
Operand Operand
Step
interlock are not carried out. The change in status of the interlock condition can be scanned with events.
The event L1 means that the interlock condition changes from the “fulfilled” state to the “not fulfilled” state (fault coming). Actions dependent on the interlock condi- tion are then no longer executed.
The event L0 means that the interlock condition changes from the “not fulfilled”
state to the “fulfilled” state (fault going). Actions dependent on the interlock condi- tion are then executed again.
The transition to the next step is independent of the state of the interlock condition.
When deactivating a step, a fulfilled interlock condition is automatically canceled.
You program an interlock condition as a logic operation in LAD or FBD. You can use a maximum of 32 program elements per interlock condition.
An interlock error is signaled if a non-fulfilled interlock condition occurs. You can activate or deactivate the acknowledgment requirement for signaling of the inter- lock error. If the acknowledgment requirement is activated, processing of the se- quencer is only continued following acknowledgment.
Supervision
A monitoring condition specific to a step is referred to as supervision. If the super- vision condition is fulfilled, a fault is present which results in a fault signal. A non-fulfilled supervision condition is the “good case”. The change in status of the supervision condition can be scanned with events.
The event V1 means that the supervision condition changes from the “not fulfilled”
state to the “fulfilled” state. A fault is then present.
The event V0 means that the supervision condition changes from the “fulfilled”
state to the “not fulfilled” state. The fault then goes again.
In the case of a fulfilled supervision condition, the transition to the next step is omitted even if the following transition is fulfilled. The fault-free step activation time #Step_name.U is stopped and the complete step activation time #Step_name.T continues.
A fulfilled supervision condition is automatically reset when a step is deactivated (a deactivated step cannot be faulty, only activated steps are monitored). Therefore, monitoring can only be carried out for actions which are programmed in the asso- ciated step.
You program a supervision condition as a logic operation in LAD or FBD. You can use a maximum of 32 program elements per supervision condition.
A supervision error is signaled when a non-fulfilled supervision condition occurs.
You can activate or deactivate the acknowledgment requirement for signaling of the supervision error. If the acknowledgment requirement is activated, processing of the sequencer is only continued following acknowledgment.
Actions in general
An active step uses actions to control operands or tags, to call blocks, or to carry out arithmetic operations. An action can consist of the interlock condition, an event, and a statement.
A statement is, for example, the setting of a bit memory using the S operation. The statement is S %M12.0 and means: As long as the step is active, the bit memory
%M12.0 is set to signal state “1” in each processing cycle.
A statement can be linked to an interlock condition. For this purpose, the statement is preceded by the symbol -(C)- (condition). The action is then -(C)- S %M12.0 and means: As long as the step is active and as long as the condition is fulfilled, the bit memory %M12.0 is set to signal state “1” in each processing cycle.
A statement can be linked to an event. An event is a change in status, for example the activation of the sequence step with the start information S1. The event is specified in front of the statement. The action is then S1 S %M12.0 and means: If the step is active and if the event – in this case the step activation – occurs, the bit mem- ory %M12.0 is set once to signal state “1”.
Events, interlock conditions, and statements can be combined together. For the ex- ample, the action is then -(C)- S1 S %M12.0 and means: The bit memory is set once to signal state “1” if the step is activated and the interlock condition is fulfilled at the same time.
If the step does not contain any actions, it is an “empty step” which reacts like an ac- tive step. The following transition is then processed immediately.
Events
An event controls an action. The change in status of a step, a supervision or an interlock condition is used to execute a statement once (Table 11.1).
The statements provided by the GRAPH programming language in actions, and how they can be combined with events, are described in the next Chapter 11.2.7
“Processing of actions”.
Table 11.1 Events for actions
Identifier Event The action is carried out once if ...
S1 S0
Incoming step Outgoing step
the step is processed for the first time the step is processed for the last time V1
V0
Incoming monitoring error Outgoing monitoring error
the supervision error (fault) occurs the supervision error is removed L1
L0
Outgoing interlock condition Incoming interlock condition
the interlock condition changes to “not fulfilled” (fault) the interlock condition changes to “fulfilled”
A1 Alarm acknowledgement an alarm is acknowledged R1 Incoming registration a registration comes
(rising edge at parameter REG_EF or REG_S)
Transitions
A transition contains the step enabling conditions to the next step. A transition is processed (the transition is “valid”) if the previous step is processed (the step is
“active”). The transition is “fulfilled” if the step enabling condition has signal state
“1”. The previous active step is then processed for a last time with the event S0 (the step is “deactivated”) and the following step is processed. The first processing takes place with the event S1 (the step is “activated”).
In the case of simultaneous branching, a transition is followed by two or more steps which are all activated in the case of a fulfilled transition. During the combination of the simultaneous branching, all last steps of the branches must be active before the common transition becomes valid.
In the case of alternative branching, the first transitions are all valid if the step prior to the branch is active. If one of the transitions is fulfilled, the following step is ac- tivated. The transitions of the other branches are then no longer valid and therefore only one branch is processed. If two or more transitions are fulfilled simultaneous- ly, the branch which is on the furthest left is processed. During the combination of alternative branching, all last transitions must be fulfilled before the following common step is activated.
A jump following a transition leads to a step which does not directly follow the tran- sition in the graphic representation. This step is activated if the transition is ful- filled.
If a transition is followed by a sequence end, processing of the sequencer is termi- nated if the transition is fulfilled.
If a transition does not contain a step enabling condition, it is an “empty transition”.
A valid empty transition is fulfilled immediately and activates the following step.