design of cmos operational amplifiers pdf

Contents Chapter 1 Basic Specifications of Op Amps 1 Chapter 2 CMOS Technology and Physics 15 2.1 Basic Processes in MOS Transistor Fabrication 152.2 Principles of MOS Transistor Functio

Design of CMOS

Oper

ational

Amplifiers Rasoul Dehghani

CMOS operational amplifiers (op amps) are one of the most important building

blocks in many of today’s integrated circuits This cutting-edge volume provides

professionals and students with an analytical method for designing CMOS op amp

circuits, placing emphasis on the practical aspects of the design process Readers

take an in-depth look at CMOS differential amplifiers and learn why and how they

serve as the main part of any op amp.

This book presents important details and design methodologies for different

architectures of single-ended op amps Complete chapters are dedicated to

the critical issues of CMOS output stages, fully differential op amps, and CMOS

reference generators Also included is an introduction to CMOS technology and a

discussion of the basics of the physical aspects of MOS transistors, providing the

foundation needed to fully master the material.

Rasoul Dehghani is an assistant professor in the Department of Electrical and

Computer Engineering at Isfahan University of Technology in Iran He holds a

Ph.D in electronics from Sharif University, Tehran, Iran He is a well-published and

frequently cited author in the field.

Design of CMOS Operational Amplifi ers

Artech House Microwave Library,

Design of CMOS Operational Amplifi ers

Rasoul Dehghani

A catalog record for this book is available from the U.S Library of Congress.

British Library Cataloguing in Publication Data

A catalogue record for this book is available from the British Library

Cover design by Adam Renvoize

in writing from the publisher

All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized Artech House cannot attest to the accuracy of this information Use of

a term in this book should not be regarded as affecting the validity of any trademark or service mark

10 9 8 7 6 5 4 3 2 1

Contents

Chapter 1 Basic Specifications of Op Amps 1

Chapter 2 CMOS Technology and Physics 15

2.1 Basic Processes in MOS Transistor Fabrication 152.2 Principles of MOS Transistor Functioning 172.2.1 MOS Transistor Operating in Saturation Region 172.2.2 MOS Transistor Operating in Subthreshold Regime 21

2.3.2 Gate to Source/Drain Capacitance 262.3.3 Source/Drain to Bulk Capacitance 27

Chapter 3 CMOS Differential Amplifiers 33

3.1 Source-Coupled Differential Pair Characteristic 333.2 CMOS Differential Amplifier with Active Load 363.2.1 Large-Signal Characteristic of CMOS

3.2.2 Offset Voltage of CMOS Differential Amplifier 383.3 Common-Mode Behavior of CMOS Differential Amplifier 423.4 CMOS Differential Amplifier Frequency Response 433.5 Noise Calculations in CMOS Differential Amplifier 47

Chapter 4 CMOS Single-Ended Output Op Amps 55

4.1.2 Two-Stage Op Amp Frequency Response 594.1.3 CMOS Two-Stage Op Amp Design Procedure 65

Chapter 5 CMOS Fully Differential Op Amps 107

5.1 Advantages of Fully Differential Op Amps 107

5.3.1 Common-Mode Feedback Circuit with Resistive

6.1.1 Source-Follower as an Output Stage 135

6.2 Drain-Coupled Complementary Transistors as Output Stage 142

6.4 Class AB Output Stage Using a Translinear Loop 153

7.1.1 Bandgap Voltage Reference Generator 168

7.1.2 Low-Voltage Bandgap Reference Generator 173

7.1.3 CMOS Voltage Reference Generator without Resistors 176

Chapter 1

Basic Specifications of Op Amps

An operational amplifier is one of the most important building blocks in many analog systems For instance, in an integrated analog filter such as a switched-capacitor or a Gm-C filter, the op amp is an integral part of the circuit Data converters including both analog-to-digital and digital-to-analog converters are other categories in which the op amp plays a fundamental role to achieve the desirable performance In voltage and current reference generators an op amp has remarkable influence on the operation of these circuits In the enumerated instances many parameters of the system are extensively dependent on the specifications of the op amps used in that system It should be noted that the criteria applied to the design of an op amp employed in such systems are usually different from those used for designing a general-purpose op amp that is to be available as a stand-alone component in discrete circuitries In general, the behavior of an op amp is described by many different parameters in which some of them might be more important than others in a particular analog system In this chapter we introduce the main op amp parameters that have significant impact on the behavior of an analog system where an op amp has been exploited

1.1 Op Amp Parameters

DC gain: Ideally the value of this parameter is considered infinity but in reality,

due to the limited intrinsic voltage gain of each device used in the op amp circuit, the entire gain of an op amp has a finite value in the typical range of to (40 dB-100 dB) Exploiting an op amp in a linear amplifier involves putting the op amp in a negative-feedback loop In this situation a high dc gain of the op amp could be essential In the following we demonstrate the reason for such an assertion Supposing that the open-loop gain of the feedback is quite high, we can calculate the closed-loop gain of the circuit based on the values of the feedback network components independent of the op amp parameters As an example consider the inverting feedback amplifier shown in Figure 1.1 Denoting the low-frequency voltage gain of the op amp as , we can calculate the exact

closed-loop voltage gain as

2 with an error less than 0.1% is achievable provided that

or if we have Thus, in order to achieve more accurate feedback gain the dc gain of the op amp needs to be quite high

Limited linearity range For a certain level of the input and output signal

variations, the internal devices of op amp operate in the linear part of their characteristics At input, the devices remain in their active operation region when the variation range of the input common-mode voltage is limited to a particular range known as input common-mode range (ICMR) [1] This parameter depends

on the op amp structure and the type and biasing conditions of the input devices The linear operation range for a differential input signal in an open-loop state is much more limited Of course when an op amp is used in a negative-feedback loop, the linearity behavior is significantly improved by the feedback mechanism

An amplified signal at the output of an op amp can also swing in the limited range

at the most between two supply rails, although its precise level depends on the particular structure utilized as the output stage

Common-mode rejection ratio One of the most outstanding advantages of an op

amp is its capability to amplify the difference of two input signals without output being affected significantly by the changes in the input common-mode level This property results in immunity against any common-mode undesirable signal that

Figure 1.1 Inverting feedback amplifier

− +

vi

vo

C 1

C 2

1.1 Op Amp Parameters 3

might appear at the inputs of the op amp The parameter of common-mode rejection ratio (CMRR) is used to quantify this performance [2] The definition of this parameter is a little bit different for the two types of op amp In a fully differential op amp in which both input and output signals are differential, the differential-mode and common-mode components of the output voltage are expressed as a linear combination of the corresponding input voltages as follows

!"# $#!%$ ##!%# (1.2a)

!"$ $$!%$ #$!%# (1.2b) where ## and $$ are differential-mode and common-mode voltage gains, respectively $# and #$ exhibit the contribution of the common-mode and differential-mode of the input; that is, !%$ and !%# in their corresponding components in the output voltage, respectively In an ideal differential op amp with a fully symmetrical structure, we have $# #$ but in reality, due to the device mismatches in the path of each input to two other outputs, this is not the case In this situation, CMRR is defined as the ratio of the differential voltage gain ## to the common-mode to differential-mode voltage gain $# as

where & ''() denotes the fully differential CMRR To measure the & ''(),

we might exploit the circuit illustrated in Figure 1.2 The fully differential op amp

is configured as a unity voltage gain amplifier in a negative-feedback loop The internal common-feedback circuit and the external negative-feedback cause the output common-mode voltage and also the dc level of each output to be kept on the common-mode reference voltage denoted by -$. Representing the voltages at the inverting and noninverting inputs of the op amp as !/ and ! , respectively, we

can easily find these voltages as follows

!/ !" -$. -$0 (1.4a)

! !"/ -$. -$0 (1.4b) From the above relations, the input differential-mode and common-mode voltages are obtained

!%$ ! !/ !"$ -$. -$0 (1.5b)

By substituting (1.5a) and (1.5b) into (1.2a) and simplifying the result, we get

!"#

1,+

2 1++

2 !"$ -$. -$0 (1.6) Now when the input voltage of -$0 is changed by 3-$0, the terms of !"$ and -$.have no variation and thus we have 3!"$ 3-$. That gives

3!"#

1,+

2 1++

be used to calculate the typical & ''() As an example, in a fully differential op amp, 100 runs of Monte Carlo analysis give 3!"# 3-$0 ;< = >? as the mean

value of the data with a standard deviation of @ A = >? and thus for this op amp

Figure 1.2 Test circuit used to measure the CMRR for a fully differential op amp

+-

+-

V cr

+

-+R

-1.1 Op Amp Parameters 5

the typical value of the CMRR becomes ;< = >? The worst-case value could

reach B >? in the range of C@

In an op amp with single-ended output the output voltage is represented by

!" #0!%# $0!%$ (1.9) where #0 and $0 are differential-mode and common-mode voltage gains, respectively Here CMRR is defined as

where & ''DE indicates the CMRR of a single-ended output op amp As it will

be shown in the next chapters, in a fully differential op amp a high CMRR is achievable by implementing a fully symmetrical circuit to minimize $# In a single-ended one, even when the op amp has a perfect symmetry in an ideal condition, the CMRR would be limited by the output resistance of the tail current source used in the differential pair One method to measure the CMRR for a single-ended output op amp is shown in Figure 1.3 [3] In this circuit we have

! -$0 and !/ !" -$0 Since !%# ! !/ and !%$ ! !/ , by

substituting these relationships into (1.9), we can write the output voltage as

!" #0!" $0F-$0 G (1.11) Rearranging (1.11), we obtain the transfer function as

Offset voltage The device mismatches in the input stage have the most

Figure 1.3 Measurement of the CMRR parameter for a single-ended output op amp

− +

contribution in this parameter It is interesting that the nonzero common-mode voltage gain of an op amp also contributes to the input offset voltage [4] To see that, from (1.9) for !%# , we have !" $0!%$ This means the op amp output voltage varies in response to the input common-mode voltage variation in spite of the fact that the differential mode of the input voltage has no variation In this situation, the op amp can be thought of as an ideal op amp in a sense that it just reacts to the differential mode of the input voltage and the effect of the input common-mode changes is attributed to an equivalent differential input voltage with the value of -%HIJ !" #0 or -%HIJ $0!%$ #0 Therefore in an op amp with nonzero common-mode voltage gain, the voltage of -%HIJ -%$ & '' is

added to the input-referred offset voltage The main parameters of an op amp that affect the offset voltage will be discussed in more detail in the next chapters Figure 1.4 represents two circuits to measure the offset voltage of single-ended and fully differential op amps Both op amps are configured as a voltage follower without any external input The left-side circuits depict the real op amps including mismatches with finite CMRR

All nonideal effects that create the offset voltage such as mismatches and nonzero common-mode voltage gains of $0 and $# have been modeled by a dc voltage source denoted by -"K that is placed in series with the input of an ideal op amp Hence, the output voltage relationships for two types in an ideal case are

!" #0!%# and !"# ##!%# Summing voltages around the loop from the output to the input yields !%# -"K !" for the single-ended op amp and

!%# -"K !"# for the other one Substituting these relationships into the corresponding equations of the output voltages gives us the offset voltages as

Figure 1.4 Test circuits for (a) single-ended (b) fully differential op amp offset voltage

−+

+ -

+ -

v od

−+

+ -

+ -

Real includes mismatches

Real includes mismatches

Ideal

Ideal

1.1 Op Amp Parameters 7

!"HDE -"K #0 #0 and !"H() -"K ## ## for single-ended and fully differential types, respectively Since #0H ## , the output voltages of both circuits nearly represent the offset voltage It should be pointed out that similar to the method used for measuring CMRR of a fully differential op amp, the

op amp offset voltage can be obtained by running several Monte Carlo analyses on the circuits of Figure 1.4 and taking the standard value of the data as the op amp offset voltage In the absence of systematic errors the mean value of the offset voltage is almost zero

Frequency bandwidth The open-loop voltage gain of an op amp begins to drop

as frequency increases This happens because of internal parasitic capacitances in the op amp circuit The bandwidth parameter is important because by dropping the

op amp voltage gain, the closed-loop gain would not be independent of the op amp parameter anymore In fact, the frequency bandwidth expresses how fast an op amp can follow the time variations in the input signal It is obvious that to amplify fast signals we need to employ an op amp with adequate large bandwidth in such a way that it can provide enough loop gain at maximum operating frequency The speed performance of an op amp is usually measured by the unity gain bandwidth parameter denoted by LM, as illustrated in Figure 1.5 As its name suggests, LM is a frequency at which the magnitude of the gain reaches unity When an op amp is used as a voltage follower in a negative-feedback loop, it might suffer from the instability problem at frequencies near LM Thus the op amp should be properly designed to have an acceptable amount of stability in the frequency domain [5]

Slew rate This parameter is used to express the time speed limitation of an op

Figure 1.5 Op amp voltage gain versus frequency

ωp1

ωp2 ωu

A v (jω)

A v0

amp output When an op amp is placed in a negative-feedback loop and a rather large-signal is applied to its input, the output cannot follow the rapid changes in the input signal This is another speed limitation in op amps that is raised in conjunction with the large-signal behavior of op amps Indeed, unity gain bandwidth indicates the limitation of an op amp to follow the fast input signals with very small amplitude while slew rate is considered an index of op amp large-signal time response [6] In some applications such as pipeline analog-to-digital converters, both parameters play a key role in determining the maximum achievable speed for the converter [7] The response of a voltage follower to a step voltage applied as input is plotted in Figure 1.6(b) As it can be seen, the output time response consists of two parts The first part is the time duration that the output voltage changes from its initial value to approach its final level This part is associated with the limited op amp slew rate The second part starts when the difference between input and output voltages is small Now the small-signal frequency response of the op amp determines how long it takes to reach its steady state This time, known as settling time, is illustrated in Figure 1.6(b)

Noise A complementary metal oxide semiconductor (CMOS) op amp is made of

several numbers of n-type MOS (NMOS) and p-type MOS (PMOS) transistors Channel thermal noise and flicker noise are two main noise sources in each MOS device [8] The total noise generated by each device is represented by two generally correlated noise voltage and noise current generators at the input of an

op amp Flicker noise has a higher level of energy at low frequencies while thermal noise has a flat spectrum in the frequency domain The variation of the spectral density of the input-referred noise voltage including both flicker and thermal noises is plotted in Figure 1.7 In this plot the thermal noise and flicker

Figure 1.6 (a) Voltage follower, and (b) time response of voltage follower to input step voltage

−+

Output response

1.1 Op Amp Parameters 9

noise asymptotes intersect each other at a frequency called the flicker noise corner frequency that is denoted by $ In submicron CMOS technology, due to some physical effects such as the hot electron effect, the level of the thermal noise in the MOS device increases According to Figure 1.7, the part of the frequency band that is less than $ is mostly influenced by the flicker noise At the frequencies near zero there is no noticeable difference between the input offset voltage and the flicker noise at the input

Power supply rejection ratio The amount of supply noise or any other

disturbances on the supply rail that can find its way to the op amp output depends

on this parameter [9] Mathematically the power supply rejection ratio (PSRR) in

Figure 1.7 Spectral of input-referred noise voltage

in which the corresponding voltage gain from positive and negative supply is denoted by R and R/, respectively In an integrated analog mixed-mode circuit where different analog and digital blocks are fabricated on the same chip, special attention should be paid to the PSRR parameter of op amps used in the circuit [10] For example, if the PSRR of an op amp is not good enough, any existent noise on the supply rail such as digital noise created by the system clock can reach the op amp output and amplified by the next stages can easily corrupt the quality

of the ultimate output signal In addition, the behavior of PSRR at higher frequencies is also important In fact, the magnitude of this parameter at high frequencies determines the amount of high-frequency supply noise that impacts on the op amp output signal In practice, PSRR can be measured by employing the circuit shown in Figure 1.8 Assuming a finite differential voltage gain of # for

op amp and denoting the voltage gain from supply to the output by R, we can write

!" R!R #!" (1.15) Rearranging (1.15), we have

Figure 1.8 Circuit used to measure PSRR

− +

1.1 Op Amp Parameters 11

PSRR in a fully differential op amp has a similar relationship given in (1.13)

in which # is replaced with ## It should be pointed out that if the circuit of the fully differential op amp has perfect symmetry in an ideal case, the noise of supply appears equally on both outputs and as a result there is no differential output voltage In reality, device mismatches in the op amp circuit reveal their contributions as nonzero differential output voltage Thus the mismatch is responsible for nonzero PSRR in fully differential op amps This means that to measure PSRR we have to follow the procedure that was given to measure

placed in series with the supply while just common-mode voltage reference -$. is applied to the input Repeating the given method for CMRR calculation, we obtain

3!"# 1++Q

Equation (1.18) represents the change in the differential output owing to the variation in the supply voltage The parameter R denotes the voltage gain from supply to the output Since ## , from (1.18), PSRR is given by

Q 3S + 3SQ

(1.19)

By performing Monte Carlo analysis we can obtain the voltage gain from supply

to the differential output in different runs Such simulation on the previous example given for CMRR calculation produces the result of

3!"# 3!R A T >? as the mean value of data that based on (1.19) gives

that in the op amp of our example, the supply noise compared to the input common-mode voltage variation is more effectively passed to the op amp output

in the presence of mismatches

Offset

voltage -"K

Depends on mismatches in threshold voltage and sizing

Zero ^^ _ `ab ; `ab c[ d`a

1.2 Conclusion 13

1.2 Conclusion

In this chapter, several important dc and ac parameters of op amps were introduced and some methods were presented that can be used to measure these parameters The discussed parameters are associated with both single-ended output and fully differential op amps We have summarized some main parameters of a typical CMOS op amp that were briefly discussed in this chapter as illustrated in Table 1.1 It is worth keeping in mind that the exact relationship for each parameter in this table depends extensively on the particular structure used in the

op amp circuit that will be the subject of the next chapters The given numerical data for some parameters indicate typical values that are usually observed in currently designed CMOS op amps

References

[1] Huijsing, J., Operational Amplifiers: Theory and Design, Second Ed, Springer, 2011

[2] Baker, R J., CMOS: Circuit Design, Layout, and Simulation, Third Ed, John Wiley & Sons,

2010

[3] Allen, P E., Holberg, D R., CMOS Analog Circuit Design, Second Ed, Oxford University Press,

2002

[4] Mancini, R., Carter, B., Op Amps for Everyone, Third Ed, Elsevier Inc., 2009

[5] Ivanov, V., Filanovsky, M., Operational Amplifier Speed and Accuracy Improvement: Analog

Circuit Design with Structural Methodology, Kluwer, 2004

[6] Baher, H., Signal Processing and Integrated Circuits, John Wiley & Sons, 2012

[7] Plassche, R., V., D., CMOS Integrated Analog-to-Digital and Digital-to-Analog, Second Ed,

Boston, Kluwer Academic Publisher, 2003

[8] Bhattacharyya, A B., Compact MOSFET Models for VLSI Design, John Wiley & Sons, 2009

[9] Shepherd, P R., Integrated Circuit Design, Fabrication and Test, McGraw-Hill, 1996

[10] Gejji, V P., Analog and Mixed Mode VLSI Design, PHI Learning Private Limited, New Delhi,

2011

Chapter 2

CMOS Technology and Physics

A part of the limitation in the performance of a CMOS circuit is related to how it

is implemented Therefore a comprehensive perception of the CMOS circuit fabrication and the required steps to get the final desirable circuit can significantly aid in achieving a successful design Furthermore, the advanced semiconductor industry necessitates a close and tight collaboration between circuit designers and process engineers, who need to understand their languages in order to exchange information about possible technological capabilities and also existent constraints

in the fabrication process In this chapter, we briefly describe the main sequence of steps that are followed in the fabrication of an MOS transistor Next, we introduce the electric current equation for this kind of transistor and based on the physical operation we present a complete small-signal model of the device In the given analysis we will refer to some physical effects such as short-channel behavior, and subthreshold operation region and their impact on the circuit design Interested readers are referred to the references at the end of the chapter for deeper discussions

2.1 Basic Processes in MOS Transistor Fabrication

In an n-well process in which all PMOS transistors are to be put inside the n-wells, the first step is to create an n-well inside the substrate of a p-type The ion implantation technique is usually used to create an n-well region The next step is

to create isolation areas between adjacent transistors by growing a thick oxide layer under which an extra ion implantation called channel-stop is done to increase the effective threshold voltage of this area After applying some trimming on the threshold voltage of the active area, the gate pattern is defined and then the source/drain junctions and also p-substrate and n-well contacts are formed by two individual ion implantations for two NMOS and PMOS devices After source/drain ion implantation, a thermal process needs to be done and thereby the damaged lattice structure is fixed This process is known as annealing Because of the thermal process in the annealing, the impurity atoms in these areas penetrate

underneath the gate electrode due to lateral diffusion The overlapped part of the gate with the extended part of the source/drain regions creates an overlap parasitic capacitance between the source/drain and gate terminals These capacitances, especially one that is formed between the gate and drain, can affect significantly the frequency response of the circuits particularly in analog designs Figure 2.1 summarizes the main steps mentioned above to fabricate two types of MOS devices The subject of CMOS technology and the fabrication process can be found in [1-5] in much more detail

Figure 2.1 Main steps of MOS device fabrication

Creation of n-well

in p-substrate

n-well

n-well p-substrate

sio2

sio2p-substrate

Channel-stop and threshold

adjust implant and

growth of field oxide

n-well

sio2p-substrate

Deposition of polysilicon gate

of NMOS and PMOS devices

n-well

sio2Field Oxide p-substrate

Channel-Stop

Implantation of source, drain, and

n-well contacts using two

individual masks in two steps for

NMOS and PMOS devices

n + n + p + p + n +

Channel-Stop Field Oxide

Field Oxide Channel-Stop

(1)

(2)

(3)

(4)

2.2 Principles of MOS Transistor Functioning 17

2.2 Principles of MOS Transistor Functioning

Shown in Figure 2.2 is the cross-section view of an NMOS transistor When a positive voltage is applied to the gate, since the majority carries of the substrate are the holes, they are repelled toward the bulk and as a result, a charge space of the negative ions leaves behind at the surface In device physics this operating area

of the device is known as the depletion mode By increasing the gate voltage in the positive direction the proper condition is provided for the majority carriers in the source region to be injected into the substrate More positive gate voltage causes growth of electrons and at the same time reduction of the number of holes This ultimately leads to inverting the type of the semiconductor from p-type to n-type at the surface For a certain level of the gate-source voltage, the density of electrons

in the created inversion layer would be that of the substrate holes In this situation the transistor operates at the edge of a state called strong inversion The corresponding gate-source voltage that puts the device at the edge of the strong inversion condition is known as the threshold voltage and is denoted by -e For

-fD -e, the electrons concentration of the inversion layer is less than that of the substrate holes and the transistor is in a state called weak inversion This operating area is known as the subthreshold region In the following sections we deal with the MOS functioning in these two operating areas

2.2.1 MOS Transistor Operating in Saturation Region

In the presence of the conductive layer in a strong inversion state, an applied voltage between the drain and source creates an electric field along the channel and makes the current flow from the source to the drain By utilizing Ohm’s law and writing the channel conductivity in terms of inversion charge g%Y , it is shown that [6] for a long-channel device the drain current equation in the triode region can be approximated by a quadratic relationship that is a function of the gate-

Figure 2.2 Cross section of an NMOS device

n+

p_substrateFOX

inversion layer

source and drain-source voltages

respectively At a given -fD -e, increasing the drain-source voltage causes the density of the free electrons of the inversion layer at the drain side to decrease, and ultimately for -f) -e the electron charges at drain almost disappear such that the device is put at the edge of the saturation region The certain value of the drain-source voltage at which the device is at the edge of saturation will be

Figure 2.3 MOS operation in a saturation region

V DS -V DS,sat

+ -

2.2 Principles of MOS Transistor Functioning 19

-)D -)DHKUq across the drain to bulk junction increases, which results in extending the depletion area toward the source region This causes the effective length of the inversion layer to decrease, and as a result, the inversion layer resistance slightly reduces This effect leads to gradually increase the drain current, which is known as channel length modulation This phenomenon shows itself as a small positive slope on the MOS output characteristic, as depicted in Figure 2.4

The drain current equation including the channel length modulation effect is a quadratic equation in which channel length is replaced by an effective length as

W) hY "VZirss -fD -e (2.3) where pI p 3p with 3p as the depletion region width of the one-sided drain

junction [7]

Jwvxy -)D -)DHKUq (2.4)

The slope of the curve shown in Figure 2.4 in saturation is denoted by X#K and can

be calculated by taking the derivation of (2.3) in terms of implicit variable -)D

X#K z4z{:k: zZz{rss: zZz4rss:k (2.5)Using (2.3) and (2.4) and after some simple manipulations on (2.5), we have

X#K |W) where the parameter | defined as

Figure 2.4 MOS characteristic in saturation with channel length modulation effect

| }#K€~ pI t-)D -)DHKUq• (2.6) where }#K • mK ‚ƒKM„ Supposing 3p … p, (2.6) can be approximated as

Zt4 :k /4:kHvˆ‰ F‡+v

The parameter X#K is the dynamic conductance between drain and source terminals

of an MOS device and plays an important role in all MOS amplifiers In fact, for a given MOS transconductance, the maximum achievable voltage gain is determined

by this parameter In a CMOS current source, high output resistance is achievable

if the exploited MOS devices have minimum possible | For a particular drain

current, a practical way to minimize | is to use the maximum possible channel

length for MOS devices and also to increase the drain-source biasing voltage based on (2.7) It is interesting that PMOS transistors at the same channel length and drain biasing conditions have usually less X#K in comparison to their NMOS counterparts This is because PMOS devices are fabricated inside the n-well and doping concentration of the n-well is usually greater than the impurity density in the p_substrate of NMOS devices Consequently at the same condition in terms of channel length and biasing condition, }#K is smaller for the PMOS device As an example, in a 0.25-\Š CMOS technology the impurity concentration in the

p_substrate is ƒKM„ <C ‹ Œ•Š/Ž and the doping density in n-well is

ƒ• I•• T = ‹ Œ•Š/Ž, and as a result, factor ‘#K of the NMOS device is about < times of its corresponding factor in a PMOS device that leads to the

same increase in the parameter of | in the NMOS transistor

Any potential difference between the source and bulk in an MOS device increases the effective threshold voltage of the device according to the following relationship [8]

2.3 Small-Signal Model of MOS Device 21

concentration in an intrinsic silicon and equals = ‹ •Š/Ž at C žœ The

parameter ’ depends on the technology parameters For example, in a 0.18- Š

CMOS technology with n"V T cŠ and ƒKM„ C ; ‹ Œ•Š/Ž (2.9) gives

difference of -D• =[ between source and bulk, with ’ TCd[, the effective

threshold voltage due to body effect changes to -e ==[ according to (2.8)

2.2.2 MOS Transistor Operating in Subthreshold Regime

For -fD -e, an MOS device works in weak inversion with the low density

of free carriers inside the inversion layer under the gate In this situation, by applying a drain-source voltage we will have a current with different nature Here the main cause of current flow is the diffusion effect that occurs due to nonuniform distribution of the free carriers inside the inversion layer In device physics contexts [8], it is proven that the drain current follows an exponential relationship similar to BJTs as

W) W FiZG Ÿ ¡k¢ £¤ ‰¥ (2.11) where W is the reverse saturation current and for an NMOS device is given by

§¨ © Ÿ/ª :k«£ ¬ (2.12)

In (2.11) o and p are the transistor channel width and length, respectively - is

equal to #IR "V with #IR as the depletion capacitance per unit area and -q¦

is the thermal voltage

2.3 Small-Signal Model of MOS Device

In the preceding drain current equations, the drain current generally changes as a function of the voltages of the drain, substrate, and gate with respect to the source (i.e., !)D, !fD, and !D•)

In (2.13) the instantaneous total value of each voltage has been indicated by lowercase letters with uppercase subscripts Supposing the amplitude of the ac

components is small enough in comparison to the bias values, we can write the variation of the drain current as a linear combination of the voltage variations

4 ¡k3!fD zz%:k:*

4 :k3!)D zz%k¨:*

4 k¨3!D• (2.14) The bias quantities are shown by capital letters for both voltage notations and their subscripts All derivatives are calculated at the bias points The first and last terms

in (2.14) indicate the influence of gate-source and substrate-source voltage variations on the drain current and thus are modeled by two different voltage-controlled current sources The second term represents the channel length modulation that is modeled as a resistor across the drain-source in the equivalent small-signal circuit Denoting the ac component of each voltage by lowercase letters for voltage name and its subscript, the drain current variation around its quiescent value can be written in terms of ac components of the gate-source, drain-source, and bulk-source voltages as

®# X0!¯K X#K!#K X0„!K„ (2.15)

If the strong inversion state is held and the transistor operates in saturation region, using (2.3) we can obtain the transconductance relationship in terms of the transistor parameters as

(2.11) becomes greater than W), -fD becomes less than -e and thus transistor enters the subthreshold region in which the transconductance does not increase anymore

by raising the transistor sizing We can get a rough estimation of the onset of entering the subthreshold regime by equating the MOS transconductance

2.3 Small-Signal Model of MOS Device 23

corresponding to two regions to arrive at the following relationship

{:

F²³G h "V q¦ (2.18)where o p is the transistor size for that (2.16) and (2.17) are equal Equation

(2.18) gives a rough criterion to find the correct MOS operating area in terms of the given process parameters At a certain dc drain current, when we have

equivalent to the transition from the strong inversion to the weak inversion state

In reality, this transition does not happen sharply but the transistor passes through

a moderate inversion state Bearing this point in mind, the ratio of W) o p

should be by far less than h "V q¦ in order to be sure that the transistor works in the subthreshold region At the same drain current level if a PMOS transistor is supposed to operate in the subthreshold region it needs to have a larger aspect ratio by the factor of hY hR, compared to its NMOS counterpart This means that in the similar condition from current and sizing standpoints, NMOS devices usually enter the subthreshold prior to PMOS transistors The condition given by (2.18) is independent of the drain current or transistor sizing and just depends on the technology parameters For instance, consider a 0.25- Š

CMOS technology in which for an NMOS device we have hY C= •Š ´ ],

"V < T ‹ /Œµ •Š , and - T By substituting the given data into (2.18),

we can see if the left-side term (i.e., the normalized drain current to the device aspect ratio) is adequately less than < \¶, the NMOS will enter the subthreshold

region As a numerical example, an NMOS transistor with the drain current of

The drain-source dynamic conductance X#K is given by X#K |W) and X0„that shows the effect of source-bulk voltage variation on the drain current can be determined by substituting (2.8) in (2.3) and differentiating the drain current with respect to the source-bulk voltage around the bias point

4k¨

z%:z4£

The negative sign in (2.20) indicates the drain current drops for the nonzero source

to bulk potential This is because the effective threshold voltage rises due to the body effect

Based on the obtained parameters for an MOS transistor, the low-frequency small-signal equivalent circuit for such device is obtained as shown in Figure 2.5 The derived small-signal circuit is valid at low-frequency For adequate high frequencies, we need to consider the effect of internal MOS capacitances Generally there are five main capacitances that should be inserted inside the circuit

of Figure 2.5 Three out of five of these capacitances are the capacitances that are formed between gate and three other terminals (i.e., drain, source, and bulk) and the latter two are associated with the junction capacitance of the drain and source area with the substrate In the following section, we will deal with each capacitance and study its behavior in different operation areas of the MOS transistor

2.3.1 Gate to Substrate Capacitance

In the NMOS structure illustrated in Figure 2.6, the gate voltage drops across the oxide and the surface of the semiconductor In MOS physics contexts it is shown

Figure 2.5 Low-frequency small-signal MOS device equivalent circuit

Figure 2.6 NMOS device structure

gds

D G

S

B

+ -

-

- - -

2.3 Small-Signal Model of MOS Device 25

that the created electric charge at the surface, denoted by gD, changes with the surface potential ”K, as depicted in Figure 2.7 [8] The gate to substrate capacitance consists of the series connection of the gate oxide capacitance and the semiconductor capacitance at the surface of the silicon For ”D corresponding

to negative gate-source voltage, the transistor operates in accumulation mode in which the surface charge is an exponential function of the surface potential ”D and thus the semiconductor capacitance K$ ·¹gD¹ ·”K is much greater than the gate oxide capacitance This results in the total capacitance between the gate, and the substrate almost becomes ¯„ op "V in which p is the channel length

without the overlap length ofp" , as indicated in Figure 2.6

For -fD -e, the surface potential varies between ”D ”• and the depletion negative ion charges underneath the gate form the main part of gD In this situation, ¯„ is the series combination of "V and #IR mK o# with o# as the depth of the depletion layer under the gate, as shown in Figure 2.6 When -fDgoes up before it reaches -e, o# increases and thus #IR decreases, which results

in lowering ¯„ For -fD -e, in the event that the transistor works in the triode region, an inversion layer of free electrons extends from the source to drain at the surface to form a capacitor in which one electrode is the gate and the other one consists of the n-type regions including source, drain, and inversion layer As discussed later, this capacitance is split up equally between the source and drain that forms a part of the gate to the source/drain capacitance In the triode region,

¯„ is a very small capacitance that is only related to a part of the gate polysilicon that overlays on the field oxide When the transistor works in saturation there is a

Figure 2.7 Electric charge vs surface potential in an NMOS device

depletion area near the drain junction so that it creates a partial depletion capacitance at the surface of the semiconductor at the drain side, as depicted in Figure 2.8 Hence, the total ¯„ capacitance in saturation will be

¯„ Žop 6— 6+rQ4+y

where #IR -#„ is the drain-side depletion capacitance at the reverse voltage -#„

In (2.21) the coefficient of 1/3 appears because in saturation it can be proven that the total charge under the gate is given by [8]

g$¦ Žop "V -fD -e (2.22)Comparing (2.22) with the same relationship for the charge in the triode region (i.e., g$¦ op "V -fD -e ) we can deduce that the effective channel length containing the inversion charge is two-thirds of the total length and one-third forms the depletion area near the drain junction; thus, one-third of #IR becomes a series connected with one-third of the gate oxide capacitance forming (2.21)

2.3.2 Gate to Source/Drain Capacitance

Here we introduce the gate to the source/drain capacitance of an NMOS device in different operation areas When the transistor is off there is no free carriers under the gate and the only significant capacitance between the gate and source/drain is due to the overlap between the gate electrode and the source/drain diffusion area The overlap is made because of lateral diffusion of the source/drain region in the annealing phase of the fabrication process From Figure 2.6 the overlap gate to source/drain capacitance is given by

Figure 2.8 NMOS device structure in saturation

- -

-

-

- - -

- -

- - - -

- -

- -

-depletion areainversion layer

2.3 Small-Signal Model of MOS Device 27

fD p" o "V (2.23) where p" is the overlap length that depends on the used technology In fact the quantity p" "V fD" is determined by the technology and because of the symmetrical structure of the MOS device, it is almost the same for both the source and drain areas In practice, the thickness of the polysilicon gate is much greater than that of both the gate oxide thickness and overlap length so that the fringing capacitance due to the fringing field lines is remarkable This shows that the value

of the gate to the source/drain overlap capacitance should be larger than that given

in (2.23) When the transistor works in the triode, as discussed earlier, there is a common capacitance between the gate and three of the same n-type areas of source, drain, and inversion layer This capacitance is divided equally between the source and drain regions with the value of =op "V Thus the total gate-source and gate-drain capacitance in the triode region will be

¯K ¯# o "V p p" (2.24)The gate-source capacitance in the saturation region can be derived by differentiating (2.22) versus -fD and adding the fixed gate overlap capacitance

fD to it

¯K o "V Žp p" (2.25)The gate overlap of the drain is the only capacitance between the drain and gate in the saturation region so that we have ¯# o "Vp" Although ¯# is small in saturation, in a common-source amplifier its effect on the circuit frequency response is significant because of the Miller effect [7]

2.3.3 Source/Drain to Bulk Capacitance

The capacitance between the source/drain and bulk depends on the operating region of the device For -fD -e, the device is off and thus this capacitance is actually the junction capacitance of the source/drain regions with the MOS body

In this case the junction capacitance itself consists of two components One is related to the bottom part of the junction and the other is the sidewall junction capacitance

and ºK• is the capacitance per unit length of the junction sidewalls

»# t mK ‚ƒKM„ -„% -D ) • is the depletion width of the source (drain) to the bulk junction and -„% is the built-in potential of the junction For -fD -ewhen the NMOS device works in the triode region, as mentioned earlier, an inversion layer consisting of free electron carriers connects two • source and

drain regions together In this situation, the capacitance of the depletion region under the gate as a parallel capacitance will be added to the junction capacitances given by (2.26) Figure 2.9 helps to make clear the contribution of the channel depletion capacitance The depletion capacitance op # with # mK o# is equally split up between drain and source junction capacitances and thus the total

ND ) o pD ) in which one side of the source (drain) area adjacent to the inversion layer is omitted from the perimeter calculation because the source (drain) diffusion area and inversion layer are the same type at this area and there is

no PN junction at that place For -fD -e and if the device works in the saturation region, two-thirds of the depletion capacitance is added to the source junction capacitance such that the total source to bulk capacitance will be

p_substrate

- - -

- - - -

C j

C jsw

- -- - - - - -

- - -

-

-

-depletionlayer

2.3 Small-Signal Model of MOS Device 29

At the drain side, we have only the drain junction capacitance according to the relationship given by (2.26) in which º and ºK• should be calculated at the drain-to-bulk bias voltage The main capacitances formed between the gate and three other terminals in an MOS device (i.e., ¯„, ¯K, and ¯#) in different operating regions of the device are plotted in Figure 2.10 The small-signal model of an MOS device including the main device parasitic capacitances is illustrated in Figure 2.11 This model is usually used to analyze MOS circuits in high frequencies

One important high-frequency parameter that indicates the merit of a transistor for high-frequency applications is known as transition frequency, which

is denoted by Le and defined as a frequency at which the current gain of the device becomes unity In order to find the Le for an MOS device, we obtain its current gain when the transistor is used in a common-source configuration, as depicted in Figure 2.12 Summing all currents at the drain node, we get

Figure 2.10 Plot of main MOS capacitances in different operating regions

Figure 2.11 High-frequency small-signal model of an MOS device

+ -

D

®# X0 ½ ¯# ! (2.29) Since ®¯ ½ ¯! with ¯ ¯„ ¯K ¯#, the current gain defined as

In practice ¯#… ¯ and ¯ ¯K so we can arrive at a simple relationship of

Le X0 ¯K Assuming the square law is held for the device, we substitute the values of X0 and ¯K into the Le relationship to obtain Le for an NMOS transistor

as follows

As it is obvious from (2.32) by scaling down the technology dimensions, the transistor transition frequency increases as a quadratic function of the device channel length For a particular technology the bias condition also affects Lethrough the overdrive voltage of the device Based on (2.32), for the same biasing condition in a given CMOS technology, NMOS transistors have better frequency response in comparison to their PMOS counterpart This is because of the higher electron mobility in NMOS transistors

Figure 2.12 Circuit used to calculate MOS transition frequency

VDS

+ - -

2.4 Conclusion 31

2.4 Conclusion

Familiarity with the basic fabrication process of MOS transistors can significantly help to give more practical insight about circuit design in CMOS technology In this chapter, we first briefly introduced the fundamental steps involved in the fabrication of two NMOS and PMOS transistors Then the MOS drain current relationships and some physical aspects of the device were briefly discussed Different operation regions of an MOS device including triode, saturation and subthreshold, and their corresponding drain current relationships were introduced Since the nature of the formation drain current in saturation and subthreshold region is totally different with completely distinct current equations, we derived a relation that can be used as an index to distinguish the correct operating region of the device This greatly helps the designer to employ true relationships to calculate the device parameters Based on concepts of device physics and the given relations, the small-signal equivalent circuit for both NMOS and PMOS transistors

in low and high frequencies were developed

References

[1] Franssila, S., Introduction to Microfabrication, John Wiley & Sons, 2010

[2] May, G S., and Spanos, C J., Fundamentals of Semiconductor Manufacturing and Process

Control, John Wiley & Sons, 2006

[3] El-Kareh, B., Fundamentals of Semiconductor Processing Technology, Kluwer Academic

Publishers, 1995

[4] Bagad, V S., Fundamentals of CMOS VLSI, Technical Publications, Pune, India, 2009

[5] Chang, C Y., and Sze, S M., ULSI Technology, McGraw-Hill, 1996

[6] Muller, R S., and Kamins, T I., with Chan, M., Device Electronics for Integrated Circuits, Third

Edition, John Wiley & Sons, 2003

[7] Gray, P R., Hurst, P J., Lewis, S H and Meyer, R G., Analysis and Design of Analog

Integrated Circuits, Fourth Edition, John Wiley & Sons, Inc., 2001

[8] Sze, S M., Ng, K K., Physics of Semiconductor Devices, Third Edition, Hoboken, New Jersey,

John Wiley & Sons, Inc., 2007.

Chapter 3

CMOS Differential Amplifiers

As its name suggests, in a differential amplifier the output signal generally is the amplified version of the difference of two inputs of the amplifier Because of the exclusive properties of this type of amplifier, it is considered as one of the most important building blocks in many analog circuits In this chapter, we first analyze

a source-coupled circuit as a differential voltage-to-current converter and then deal with the CMOS differential amplifier in which a current mirror circuit is employed

as an active load for the source-coupled pair This amplifier is regarded as an integral part at the input of most single-ended output operational amplifiers so that many properties of an op amp depend on the parameters of this block We study the large-signal characteristics of this amplifier in detail Offset voltage, frequency response, and noise behavior of the amplifier are the subjects for the rest of this chapter

3.1 Source-Coupled Differential Pair Characteristic

In the differential pair shown in Figure 3.1, it is assumed that M1 and M2 are exactly the same and both operate in saturation Furthermore, the channel length modulation effect is ignored and it is presumed that the drain current of each

Figure 3.1 Differential pair amplifier

I0

+-

v i

M1 M2