Design of CMOS receivers and building blocks for ultra wideband radio

Name: TONG YAN Degree: Master of Engineering Department: Electrical and Computer Engineering, NUS Thesis Title: Design of CMOS Receivers and Building Blocks for Ultra-Wideband Radio Abst

DESIGN OF CMOS RECEIVERS AND BUILDING BLOCKS FOR ULTRA-WIDEBAND RADIO

TONG YAN

(B Eng , Zhejiang University)

A THESIS SUBMITTED FOR THE DEGREE OF MASTER OF ENGINEERING DEPARTMENT OF ELECTRICAL AND COMPUTER

ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE

2006

Name: TONG YAN

Degree: Master of Engineering

Department: Electrical and Computer Engineering, NUS

Thesis Title: Design of CMOS Receivers and Building Blocks for Ultra-Wideband Radio

Abstract

In this thesis, receiver systems and CMOS integrated circuits design for Ultra-Wideband (UWB) communication are proposed

Several building blocks for the receivers are designed in a 0.18-µm CMOS

technology Cross-coupled transistors with source followers are used to implement the multiplier Inductor peaking technique is employed to enhance multiplier bandwidth with more than 7 GHz bandwidth A continuous-time negative feedback loop is employed in the VGA to suppress DC-offset by 15 dB while obtaining 45 dB dynamic range The integrator employs G m− −C OTA structure

to obtain a unit gain frequency of around 1 GHz and low -3 dB bandwidth of less than 1MHz

Two UWB receiver architectures are proposed and implemented using the proposed building blocks The coherent receiver achieves simulated transmission rate of 100 MHz and sensitivity of -80 MHz, and the non-coherent receiver achieves measured transmission rate of 50 MHz and sensitivity of -65 dBm

Keywords: ultra-wideband, receiver, DC-offset, multiplier, variable gain amplifier, integrator

Acknowledgements

I would like to express my deepest gratitude to my supervisor, Dr Zheng Yuanjin, for the opportunity to work on an interesting research topic and his encouragement, guidance and many invaluable ideas during the research I am also extremely grateful to my associate supervisor, Assoc Prof Xu Yong Ping, for his guidance and patience His invaluable comments has made breakthrough to the whole research project

I would also like to take this opportunity to thank the Institute of Microelectronics for the award of a research scholarship under Joint Microelectronics Laboratory with National University of Singapore and Integrated Circuits and System Laboratory for providing excellent facilities, without which the present work would not have been possible Thanks also go to the National University of Singapore for giving me the opportunity to pursue postgraduate study

I am grateful to Mr Wong Sheng Jau, and Mr Oh Boon Hwee for their numerous extended discussions, clear thoughts and generous assistance provided throughout the project

I would like to thank my friends Cao Rui, Zhou Qiaoer, Yan Jiangnan and Yang Liu, Wei Xiaoqian and Cao Mingzheng who are working together with me

in IME The relaxed and inspiring team atmosphere with them is very helpful to the completion of this work

I want to express my gratitude to my colleagues Zhou Lei, Chen Jianzhong,

Pu Yu, Yu Rui, Yu Jianghong, Gu Jun, Hu Yingpin, He Ying, Wei Ying, Wu Hong Lei and M Umashankar at the NUS Signal Processing and VLSI Design laboratory for creating a relaxed and pleasant working atmosphere

Finally, I am deeply indebted to my family for their unconditional love, encouragement and support They have been extremely important not only in making me who I am, but also in helping me through the highs and lows that have accompanied my academic endeavor

Table of Contents

Abstract ii

Acknowledgements iii

Table of Contents v

Summary viii

List of Tables x

List of Figures xi

List of Symbols and Abbreviations xiv

Chapter 1 Introduction 1

1.1 Background and Motivation 1

1.1.1 Overview of Ultra-Wideband System 1

1.1.2 Motivation 4

1.2 Organization of the Thesis 5

Chapter 2 UWB Receiver Architectures 7

2.1 Overview of Receiver Architectures 7

2.1.1 An Overview of Direct Conversion Receiver Architecture 7

2.2.2 DS-UWB Receiver Architectures in the Literature 11

2.2 Proposed UWB Modulation Schemes and Receiver Architectures 14

2.2.1 Antipodal Modulation and Coherent Receiver Architecture 14

2.2.2 On-Off Keying Modulation and Non-Coherent Receiver Architecture 21

Chapter 3 UWB Receiver Building Blocks Design 25

3.1 Multiplier 26

3.1.1 CMOS Transconductance Analog Multiplier 26

3.1.2 Proposed Multiplier for Ultra-Wideband Receiver 33

3.2 Variable Gain Amplifier 39

3.2.1 General Consideration 39

3.2.2 Existing Gain Varying Techniques 40

3.2.3 DC-Offset Cancellation Techniques 42

3.2.4 Proposed VGA Circuits with DC-offset Suppression Loop and Simulated Performance 45

3.3 Integrator 51

3.3.1 Integrators in the Literature 51

3.3.2 Proposed Integrator Structure 55

3.3.3 Circuits implementation and Performance 61

3.4 Comparator 66

3.5 A Brief Overview of Other Receiver Building Blocks 68

3.5.1 Low Noise Amplifier 68

3.5.2 Pulse Generator 69

3.5.3 Demodulation Drive Amplifier 70

3.5.4 Low Pass Filter 71

Chapter 4 UWB Receiver Integration and Performance 72

4.1 Coherent Receiver Implementation and Performance 72

4.1.1 Coherent Receiver Integration 72

4.1.2 Simulated Performance of the Coherent Receiver 74

4.2 Non-Coherent Receiver Implementation and Performance 76

4.2.1 Non-Coherent Receiver Integration 76

4.2.2 Measured Performance of the Non-Coherent Receiver 76

4.3 Layout Considerations 79

Chapter 5 Conclusions and Future Directions 81

5.1 Conclusions 81

5.2 Future Directions 82

Bibliography 83

Appendix A Layout of the Coherent Receiver Chip 94 Appendix B Die Micrograph of the Non-Coherent Receiver chip 95 Appendix C Publications 96

The multiplier has achieved a -3 dB bandwidth larger than 7 GHz and maximum gain larger than 13 dB With a DC-offset suppression feedback loop, the VGA has more than 15 dB offset suppression, 45 dB gain variation range, and 178 MHz -3

dB bandwidth The integrator employs G m− −C OTA structure to obtain unit gain frequency of around 1 GHz and low -3 dB bandwidth of less than 1 MHz It can perform the integration on narrow pulses within 1ns and hold for 10 ns with less than 3% discharge error A comparator with 90 mV hysteresis and 400 ps propagational delay is designed

Based on the proposed receiver architectures and building blocks as well as a low noise amplifier, a demodulation drive amplifier, a lowpass filter and a local pulse generator designed by group members, a coherent and a non-coherent UWB receivers are implemented The coherent receiver achieves 100 MHz data transmission rate, 80 dB gain and -80 dBm sensitivity in simulation The non-coherent receiver has a measured transmission rate up to 50 MHz, 70 dB gain and -65 dBm sensitivity

List of Tables

Table 1: Summary of Simulated Coherent Receiver Performance 75 Table 2: Summary of Non-Coherent Receiver Performance 79

Fig 3.1: Principle of transconductance multiplier 27

Fig 3.2: Four-quadrant multiplier architecture using single-quadrant multipliers 27

Fig 3.3: Four-quadrant multiplier architecture using square-law devices 28

Fig 3.4: Type I transconductance multiplier topology 30

Fig 3.5: Type II transconductance multiplier topology 30

Fig 3.6: Type III transconductance multiplier topology 31

Fig 3.7: Proposed multiplier for UWB receiver 33

Fig 3.8: Bandwidth and gain of the multiplier from RF input to output 36

Fig 3.9: DC transfer characteristic of the multiplier from RF input to output 36

Fig 3.10: Bandwidth and gain of the multiplier from LO input to output 37

Fig 3.11: DC transfer characteristic of the multiplier from LO input to output 37

Fig 3.12: Transient simulation of the multiplier 38

Fig 3.13: Measured multiplier performance 38

Fig 3.14: Gain control by vary loading or bias current 41

Fig 3.15: AC-coupling to block DC-offset 43

Fig 3.16: DC-offset subtraction technique 43

Fig 3.17: Analog feedback technique: (a) Conceptual diagram (b) Frequency response 45

Fig 3.18: Block Diagram of the VGA 46

Fig 3.19: Schematic of VGA core circuits 46

Fig 3.20: VGA core circuits with DC-offset suppression loop 48

Fig 3.21: Frequency response of the VGA 50

Fig 3.22: Frequency response of an integrator (a) ideal case (b) practical implementation 52

Fig 3.23: Five common integrator structures 53

Fig 3.24: Two types of capacitor connection 55

Fig 3.25: The chosen integrator structure: G m− −C OTA structure 58

Fig 3.26: Equivalent model of the G m− −C OTA integrator structure 59

Fig 3.27: Proposed integrator structure with feedforward path 61

Fig 3.28: The schematic of transconductor used in the integrator 62

Fig 3.29: The schematic of OTA used in the integrator 63

Fig 3.30: Frequency response of the integrator 65

Fig 3.31: Transient Simulation of the integrator 65

Fig 3.32: The measured integrator response to a pulse input 66

Fig 3.33: Schematic of the comparator 67

Fig 3.34: The hysteresis characteristic of the comparator 67

Fig 3.35: Schematic of the UWB LNA 69

Fig 3.36: Schematic of the differential pulse generator without buffers 69

Fig 3.37: Schematic of the demodulation drive amplifier 70

Fig 3.38: Schematic of the low pass filter 71

Fig 4.1: The implemented coherent UWB receiver 73

Fig 4.2: Timing of clocks for pulse generator and integrator 73

Fig 4.3: Transient simulation results of the coherent receiver 74

Fig 4.4: The implemented coherent UWB receiver 76

Fig 4.5: Measured real time waveforms of data patterns (Above: transmitted data pattern, Middle: modulated pulse signal, Below: demodulated and recovered pattern) 78

List of Symbols and Abbreviations

I Bias current of MOSFET

X, Y Bias of multiplier input

x, y Small signal at multiplier input

V Drain-source voltage of MOSFET

K Transconductance parameter of MOSFET

g , g mb Transconductance of MOSFETs in VGA

Q Quality factor of low pass filter

R Resistor in common mode feedback loop

ADS Advanced Design System

AC Alternating Current

BER Bit Error Rate

BPSK Bi-Phase Shift Keying CDMA Code-Division Multiple Access

CMOS Complementary Metal-oxide semiconductor COB Chip-On-Board

CSM Chartered Semiconductor Manufacturing

DA Driver Amplifier

DAC Digital-to-Analog Converter

DCR Direct Conversion Receiver

DDA Demodulation Driving Amplifier DS-UWB Direct-Sequence UWB

DSP Digital Signal Processing

ESD Electrostatic Discharge

GSG Ground Signal Ground

FCC Federal Communication Committee

MOS Metallic Oxide Semiconductor

MOSFET Metallic Oxide Semiconductor Field Effect

Transistor MAC Media Access Control

NMOS N-type MOS

OOK On-Off Keying

OTA Operational Transconductance Amplifier

PPM Pulse Position Modulation

PSRR Power Supply Rejection Ratio

RAKE RAKE receiver

RF Radio Frequency

RX Receiver

SAW Surface Acoustic Wave device SFDR Spurious-Free Dynamic Range SNR Signal to Noise Ratio

SRD Step Recovery Diodes

THD Total Harmonic Distortion UWB Ultra-Wide Band

VGA Variable Gain Amplifier

WPAN Wireless Personal Area Network

Chapter 1

Introduction

1.1 Background and Motivation

1.1.1 Overview of Ultra-Wideband System

Ultra wideband (UWB) systems are a new wireless technology capable of transmitting data over a wide frequency spectrum with very low power and high data rates Among the possible applications, UWB technology may be used for high speed data communication systems, vehicular and ground penetrating radars, and imaging systems One of its most promising application areas is Wireless Personal Area Network (WPAN), in which UWB technology is envisioned to replace almost every cable at home or in an office with a wireless connection that features hundreds of megabits of data per second [1]

Although the UWB standard for high data rate communication (IEEE 802.15.3a [2]) has not been completely defined, most of the proposed applications are allowed to transmit in a band between 3.1 – 10.6 GHz The federal

Communication Committee (FCC) has defined the spectral mask for UWB indoor communication systems, as shown in Fig.1.1 According to FCC’s regulation [3], UWB transmission is defined as the occupied fraction bandwidth > 20 % or larger than 500 MHz of absolute bandwidth

The benefit of UWB can be explained by Shannon’s channel capacity formula

Fig 1.1: FCC Spectral Mask for UWB Communication Systems [4]

There are two main categories of UWB signaling schemes: Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) [4] based scheme and Direct-Sequence UWB (DS-UWB) [5] [6] [7] based scheme The former divides the whole UWB spectrum into sub-bands with bandwidth of several hundred of Megahertz, and in each band a conventional carrier based approach is used The latter is a carrier-less impulse radio based system in nature, in which either very narrow impulse signals occupying the whole UWB frequency band (3.1 – 10.6 GHz) can be used, or alternatively several types of impulse signals with different widths can be used, each occupying a sub-band of the whole UWB spectrum [2]

In this thesis, only impulse radio type UWB (DS-UWB) communication system is discussed

The typical UWB impulse signal is a Gaussian monocycle pulse, which is the second order derivative of Gaussian function as shown in Fig.1.2

The Gaussian monocycle pulse signal can be expressed mathematically as [8]:

Fig 1 2: Typical UWB monocycle pulse signal

1.1.2 Motivation

Implementation of low cost UWB transceiver integrated circuits is a key success factor for UWB communication systems to be widely adopted The UWB receiver chip design is particularly challenging in that it must provide sensitivity lower than -80 dBm and consume low power to enable longer battery life The impulse radio type UWB receiver is quite different from conventional carrier based wireless receivers Building blocks which are common in carrier based receiver system, such as local oscillators and channel select bandpass filters, are not present in an impulse radio type UWB (DS-UWB) receiver, and almost all of conventional receiver architectures can not be directly applied to DS-UWB receivers As a result, innovations on novel system architecture as well as new circuits techniques are needed

In this thesis various key building blocks of impulse radio type UWB wireless

receivers such as multiplier, integrator, VGA and comparator are investigated and two UWB receiver systems are built in 0.18 µm CMOS technology based on the proposed building blocks and some other available circuit blocks The two receivers achieve transmission rates of 100 Mbps and 50 Mbps respectively, and sensitivity of -85 dBm and -65 dBm respectively The goal is to solve several critical problems in DS-UWB receiver design such as correlator design and DC-offset suppression, and to use simulation and experimental results to verify the feasibility of integrated UWB receiver solution in low cost CMOS technology

1.2 Organization of the Thesis

In chapter 2, conventional receiver architectures are briefly reviewed The modulation schemes for UWB impulse radio such as Pulse Position Modulation (PPM), pulse On-Off Keying (OOK) Modulation and Bi-Phase Shift Keying (BPSK) Modulation are discussed Based on the adopted BPSK and Pulse OOK modulation schemes, the correlator based coherent UWB receiver architecture and the self-synchronized non-coherent UWB receiver architecture are proposed Chapter 3 concentrates on design of UWB receiver building blocks for ultra-wideband application and their performance Blocks including multiplier, integrator, VGA and comparator are discussed Blocks designed by group members are briefly introduced

In chapter 4, a coherent UWB receiver and its simulation results are described The measurement of a non-coherent UWB receiver integrated by other team

member is performed and the results are presented The two versions of receiver ICs are based on building blocks described in Chapter 3

Conclusions from this work are given in Chapter 5 along with suggestions for future work

Appendix of Chapter One: Publication List

P1: Yuanjin Zheng, Yan Tong, Yongping Xu, Wooi Gan Yeoh, "A CMOS UWB Transceiver for WPAN,” IEEE Radio Frequency Integrated Circuits Symposium, Long Beach, CA United States, June 2005

P2: Yan Tong, Yuanjin Zheng, Yongping Xu, "A Coherent UWB Receiver IC System for WPAN Application,” IEEE International Conference on Ultra-Wideband, Zurich, Switzerland, September 2005

Chapter 2

UWB Receiver Architectures

This chapter deals with UWB receiver architectures The first section briefly reviews the direct conversion receiver architecture for conventional wireless communication systems The second section proposes two DS-UWB modulation schemes together with their corresponding receiver architectures used in this project

2.1 Overview of Receiver Architectures

2.1.1 An Overview of Direct Conversion Receiver Architecture

A radio receiver architecture strongly depends on its modulation scheme and system requirements such as carrier frequency, sensitivity, selectivity, linearity, noise, as well as constraints of power consumption and numbers of off-chip components Since the modulation scheme of an impulse based UWB system is significantly different from the conventional systems, the architecture for

DS-UWB receiver should also be different However, in DS-UWB systems, modulated Gaussian pulse signals are correlated and demodulated like in direct conversion receivers, since in both cases multiplication of two signals in the same

or nearby frequency range are involved [9] As a result, the direct conversion receiver is discussed for better understanding of UWB receiver architecture and related design issues

The typical block diagram for a Direct Conversion Receiver (DCR) is shown

in Fig 2.1 In this architecture, both IF and image-rejection filters are eliminated compared to superheterodyne architecture The entire RF spectrum is translated directly to the baseband since LO and RF signals are at the same frequency Compared to the commonly used superheterodyne receivers, direct conversion receivers are more suitable for the high level integration due to the elimination of

IF SAW filters [10] Besides, the problem of image rejection is circumvented since the IF is zero [11] However, a direct conversion receiver has several drawbacks which either do not exist or are not as serious in other receivers

Fig 2.1: Direct Conversion Receiver Architecture

z DC-offsets

Perhaps this is the most serious problem in direct conversion receiver Because

of capacitive and substrate coupling and, the leakage signal of LO appears at inputs of the LNA and the mixer This leakage is mixed with the LO signal, thus producing a DC component at the output of the mixer (shown in Fig 2.2 (a)) Similarly, a large interferer may leak from LNA or mixer inputs to LO thus also producing a DC component (shown in Fig 2.2 (b)) This DC-offset signal can be amplified by a following VGA to considerably large amplitude (if direct connections are used between cascaded stages) and thus corrupt the desired signal and saturate the following stages [12] Since the downconverted signal is in the baseband near DC, it is much more difficult to remove the offset component from the desired signal using a bandpass filter in the direct conversion receiver than in superheterodyne receiver Various DC-offset canceling techniques have been employed in integrated direct conversion receiver designs [12] [13]

(a)

(b) Fig 2.2: Generation of DC-offsets in Direct Conversion Receiver

(a) LO leakage (b) Interferer leakage

z Even Order Distortion

Since in a direct conversion receiver the desired signal after the mixer is around zero frequency, any two adjacent strong RF interferers will generate a low

frequency distortion to the desired signal in the presence of even-order distortion

z LO leakage

In addition to introducing DC offsets, leakage of the LO signal to the antenna radiates and thus creates interference in the band of other receivers To avoid such interference, the signal level of the radiated LO leakage should be kept as low as -50 to -80 dBm

2.2.2 DS-UWB Receiver Architectures in the Literature

Compared with carrier-based receiver system, architectures for DS-UWB receivers are much simpler Fig 2.3 shows a simple DS-UWB receiver architecture [16], which consists of only four blocks including baseband No matter what modulation scheme is adopted, the received signals are amplified by the LNA and VGA and converted to the digital domain by the ADC, and then the demodulation is performed in the baseband Despite the simple architecture, however, the ADC should be able to sample and digitize the received signal at least at the Nyquist rate of several Gigahertz, which is beyond 10 GHz and is not feasible for IC implementation

Fig 2.3: A simple DS-UWB receiver architecture

Some more complicated DS-UWB receiver architectures also appear in the literature Fig 2.4 shows a UWB receiver employing correlators and RAKE

receiver [17] In this architecture each RAKE branch correlates the receiver pulse and a template pulse with different delay An adaptive algorithm is used to determine the optimum values for coefficients 1c , 2 c …etc, in order to mitigate

the multipath effects and obtain maximum SNR This architecture has much better performance than the one shown in Fig 2.3, however, at the cost of significantly higher system complexity

Fig 2.4: DS-UWB receiver architecture employing correlators and RAKE

In order to reduce the system complexity and to avoid an ADC sampling rate beyond 10 GHz, receiver architectures without RAKE, template generator and timing circuits are explored [20] [21] Fig 2.5 shows an Autocorrelation Receiver for DS-UWB [20] In this architecture, two pulses per symbol are received with a chosen delay τ between them The receiver delays the first pulse by the delay τ , multiplies it with the second pulse and integrates the result over one delay length,

which in fact correlates the two pulses Using a NRZ modulation, the information can be encoded as the polarity of the second pulse, which determines the polarity

of the correlation value Alternatively, it is also possible to use the pulse for the previous symbol as the reference and send only one pulse for each symbol, resulting in differential coding Although this architecture is quite simple, however,

it is very difficult to implement a delay cell with high linearity, constant phase delay over the whole UWB band, low phase noise and accurate delay time

Fig 2 5: Autocorrelation DS-UWB receiver architecture

Another DS-UWB receiver architecture with low system complexity is shown

in Fig 2.6 [21] In this architecture, a matched filter is used and its sampled output

is exactly the value obtained using the optimal receiver approach The frequency response of this matched filter is designed to match the conjugate of the frequency spectrum of the impulse signal Since the exact pulse location is unknown, in each period a square-law device and a integrator average the matched filter output so that the averaged correlation value can be sampled at a fixed time point The problem of this architecture is that, the matched filter design is a great challenge

to circuit implementation

Fig 2.6: DS-UWB receiver architecture employing matched filter

2.2 Proposed UWB Modulation Schemes and Receiver Architectures

In general, the impulse radio UWB system directly modulates an impulse-like waveform with sharp rising and falling edges, which occupies several GHz of bandwidth The information can be modulated by several different techniques: the pulse can be modulated with ±1 amplitude variations (BPSK or antipodal

signaling) or ±M variations (M-ary pulse amplitude modulations or M-PAM), or

turning the pulse on and off (known as on/off keying or OOK), or dithering the pulse position (known as pulse position modulation or PPM)

2.2.1 Antipodal Modulation and Coherent Receiver Architecture

Antipodal (BPSK) is perhaps the most straightforward modulation scheme for impulse radio type UWB wireless communication systems The digital

information +1 and -1 are represented by Gaussian pulses with positive and negative polarities respectively, as shown in Fig 2.7 In each time period one Gaussian pulse is sent so that one information bit is transmitted

Fig 2.7: Antipodal (BPSK) Modulation for DS-UWB

The demodulation of BPSK modulated signal involves an analog UWB correlator The UWB correlator consists of an analog multiplier and a time-domain integrator, as shown in Fig 2.8

Fig 2.8: Structure of an analog UWB correlator

The correlator generates the correlation value between the received impulse signals and a local template signals in each time period The template signal is a perfect Gaussian impulse signal generated by the receiver The output of a UWB correlator can be described mathematically as:

where K is a gain factor, ( ) r t is the received signal, ( ) v t is the template

signal, τ is the timing error between the received signal and the template, and

T is the time period (chip duration) The output correlation value is sampled and

reset to zero at t =nT, t= +(n 1)T , etc

The noise at the input of the correlator, which can be considered as white and Gaussian and with variance of N [14], is also correlated with the template 0

signal The noise component of the correlator output is a zero-mean Gaussian

random variable N , with a variance of

E N ( 2) = N0⋅ Rvv(0) (2.2) where Rvv( ) τ is the auto-correlation of the template signal ( )v t

Therefore the signal-to-noise ratio of the correlator output is

which is a function of time error τ

When the timing error is zero, the maximum SNR can be obtained [14] If the incoming signal is a scaled version of template, which can be expressed as

r t ( ) = ⋅ h v t ( ) , (2.4) (in most practical cases h  ), then the maximum SNR can be expressed as 1

The output SNR normalized by the noise and signal power versus timing error

is plotted in Fig 2.9 (Gaussian impulses covering the whole UWB band 3.1 ~ 10.6

GHz are used to plot this curve) It is clear that accurate alignment between the incoming signal and the template signal is crucial for successful reception in this modulation scheme [14]

Fig 2 9: Output SNR degradation (dB) when the timing error becomes larger

Fig 2.10 shows the normalized output correlation versus the correlation time, assuming that the timing alignment is ideally achieved The correlator requires at least 0.6 ns to perform the correlation operation, for pulses occupying the whole UWB band The correlation time is a fundamental limit to the maximum chip rate

or the minimum period adopted, which should be much more than the required correlation time The current proposals for IEEE 802.15a.3 standard set the maximum date rage as 480 Mbps, which translates to a time period of approximately 2.08 ns

Fig 2.10: The relation of the correlation function and the correlation time

Some other demodulation schemes employ sinusoidal template signals to correlate with incoming signals As shown in Fig 2.11, if the peak of a Gaussian impulse aligns accurately with the peak of a sinusoidal signal at the appropriate frequency, a maximum correlation value can also be attained The advantage is that the sinusoidal LO signal is much easier to generate than the impulse templates, however, timing is a much more severe problem in such schemes and the correlation function is very sensitive to the LO frequency

Direct-Sequence Code-Division Multiple Access technique can be employed

to further spread the spectrum of impulse signals as a mean of multiple accesses

In this case, certain set of orthogonal CDMA codes are used to modulate the pulse train

Fig 2.11: Sinusoidal template overlapped with the Gaussian impulse

The proposed UWB receiver architecture for the antipodal/BPSK modulation scheme is shown in Fig 2.12, which is a coherent receiver in nature This type of UWB receiver requires accurate synchronization between transmitter and receiver clocks [15] [16]

Fig 2.12: System architecture of coherent UWB receiver for BPSK modulation

The receiver consists of a low noise amplifier (LNA), an analog demodulator (correlator), and an Analog-to-Digital Converter (ADC) The weak received pulses

are a BPSK modulated pulse train The LNA amplifies the incoming pulses and subsequently the pulses are correlated with the local pulse templates in the multiplier and integrator The integrator outputs a constant correlation level in each period for A/D conversion A discharging clock sets the integrator output to zero at the end of each period, so that the output correlation values in the adjacent periods do not affect with each other The variable gain amplifier (VGA) is inserted between the multiplier and the integrator to maintain a large dynamic range To address the DC-offset associated with the direct-conversion-like architecture, the VGA gain stage employs a feedback loop to suppress the offset The ADC is operating under a symbol-by-symbol sampling rate

The clocks for the integrator, ADC and local pulse generator are provided by a clock generator (PLL) In this project a 100 Mbps transmission rate is adopted for the coherent receiver system, so all the clocks are at the frequency of 100 MHz Synchronization is implemented with a specific function block Control signals for various blocks such as VGA, PLL and integrator as well as various backend DSP operations such as equalization, de-spreading and decoding are provided by the baseband processor

In this receiver architecture the most severe problem is the DC-offsets The coherent UWB receiver architecture is similar to direct conversion receiver [9], in that the analog multiplier in the correlator multiplies two identical impulse signals

so that the output of mixer has significant DC and low frequency components As

a result, similar to the case in the direct conversion receiver, DC-offsets due to

leakage and self-mixing overlap with the desired signals Besides, various stages are connected with each other directly without coupling capacitors, so mismatch between differential paths in each stage also contributes to the DC-offset Since the integrator has a very large DC gain, a small amount of DC-offset at the multiplier output can be amplified to a significant level thus blocking the ADC sampling circuits

2.2.2 On-Off Keying Modulation and Non-Coherent Receiver Architecture

Although coherent demodulation can achieve very high transmission rates, it needs precise timing synchronization between transmitter and receiver, which is a challenge and greatly increases the system complexity [18] An alternative solution is non-coherent demodulation, which usually needs the special devices such as Step Recovery Diodes (SRD) to generate pulses and detect the pulses [19]

A lot of effort has been devoted to non-coherent demodulation techniques for impulse based UWB system [20] [21], however, the system complexities of these architectures are still not low enough to enable low power implementations In this project, a pulse On-Off Keying (OOK) modulation and non-coherent demodulation schemes are proposed, as shown in Fig 2.13 and Fig 2.14 Although no synchronization system and no special diode devices are required for this architecture, a considerably high data rate transmission can still be attained

Fig 2.13: Non-coherent transceiver system with pulse OOK modulation

Fig 2.14: Modulation and Demodulation: (a) Binary modulation signal (b) UWB pulse train (c) Modulated signal (d) Squared signal (e) Lowpass filtered signal

Fig 2.13 shows the block diagram of the proposed impulse based UWB transmitter and receiver The transmitter consists of a pulse generator, a pulse