Tài liệu EMICONDUCTOR ( P N JUNCTION ) D IODES ppt

An ideal diode is a two-terminal device defined by the following non-linear current-voltage iv-characteristic: + v -i Circuit Symbol "brick wall" "arrowhead" 0 Reverse Bias Forward Bias

ELEC 254

S EMICONDUCTOR ( P N J UNCTION ) D IODES

Physically, diodes are formed by the interface between two regions of oppositely doped

semiconductor (i.e., pn junction) and are thus, structurally, the simplest semiconductor

devices used in electronics

An ideal diode is a two-terminal device defined by the following non-linear (current-voltage) iv-characteristic:

+ v

-i

Circuit Symbol

"brick wall"

"arrowhead"

0

Reverse Bias

Forward Bias

i

v

"electronic check valve"

"FB"

"RB"

Forward Biased Regime (v>0): Zero voltage drop occurs across a forward-biased ideal diode (i.e., the diode behaves like an ideal short circuit).

Reverse Bias Regime (v≤0): Zero current flows in a reverse-biased ideal diode (i.e., the

diode behaves like an open circuit)

Note: From the above, it follows that zero power dissipation occurs in an ideal diode

The physics of real pn junctions leads to the following (non-ideal) iv-characteristics:

(see Figs 3.7, 3.8 in S&S 4th ed - Real Diode current-voltage characteristics)

Forward Bias Regime (v>0):

The iv-characteristic in this region is closely approximated by

i =Is(e v / nVT −1)

where Is=Reverse Saturation Current (also called Scale Current in S&S text, since

Is∝A) Typically, Is is very small: pA for small Si diodes, fA for IC diodes

1

Sedra & Smith, 4th Ed.

Is= Aq D p

L p N D+ D n

L n N A



 





 n i2=constant for a given diode at a given temperature

n=empirical constant (typically 1≤n≤2, depending on the type of diode and its physical structure), which accounts for carrier gen/recomb in the depletion region

(higher J's and fewer centers in IC's, so n is closer to 1, cf 2 for discrete devices) Actually n depends on the magnitude of v & so is not strictly constant.

VT=Volt-Equivalent of Temperature or Thermal Voltage.

The Thermal Voltage can also be written explicitly as

VT=kT/q

where k=Boltzmann's constant (also written kB)=1.38x10-23 J/K

T=Absolute Temperature (K)

q=Electronic Charge=1.602x10-19 C

e.g At 20 ˚C, VT=25.2 mV ≈25 mV (used throughout S&S text and this course)

Clearly, for larger currents (where i>>Is or v>10nVT)

i ≅Ise v / nVT

which has been found to hold over several (≈7) decades of current

The diode equation has 2 parameters and hence 2 measurements are required to determine Is and n empirically

Consider the change in diode voltage drop due to a change in diode current:

Let I1=IseV1 /nV T and I2=IseV2 /nV T ,

then I1/I2=e(V1 − V2)/nVT

or V1−V2=2.303nVTlog(I1/I2) - so slope of log plot yields value of n

i.e., the diode voltage changes by ≈2.3nVT for every decade change in diode current

(e.g., ≈60 mV for n=1 @20 ˚C).

In practice, if n is unknown, a common "rule of thumb" is to assume V1-V2≈100

mV/decade @ 20 ˚C, which yields n≈1.7 (in this course, if n is unknown, use n=1) Reverse Bias Regime (VZK≤ v≤0):

The reverse diode current is also described by

i =Is(e v / nVT −1)

but, since e v /nVT →0 when v<<0, this expression reduces to

i≈-Is

so the current "saturates" at -Is when the diode is significantly reverse biased (and hence the

name Reverse Saturation Current).

Note that the actual reverse current may be mA due to leakage over the surface of the diode and additional carriers generated by collisions in the depletion region

Breakdown Regime (v≤VZK):

A reversible breakdown occurs when v<VZK, which gives rise to the steep gradient in the

iv-characteristic in this region.

There are actually two distinct breakdown mechanisms:

1 Zener breakdown (predominates if -5≤VZK≤-2 V) - does not involve collisions (direct disruption

of covalent bonds due to E across depletion region; occurs in heavily doped semiconductors, since higher doping results in narrower depletion region

2 Avalanche Breakdown (predominates if VZK<-7 V) - lightly doped semiconductors

A combination of these mechanisms is usually responsible in diodes where -7≤VZK≤-5 V Diodes specifically designed to be operated in this breakdown regime are typically called

Zener diodes, regardless of which mechanism dominates.

(see Fig 3.31 in S&S 4th ed - Zener diode characteristic & circuit symbol - note "reverse"

polarity compared to signal diodes)

Temperature Dependence:

Forward Bias Regime: At a given (constant) diode current, v exhibits a linear temperature

dependence due to the dependence of Is and VT on temp

Rule of Thumb: Typically, the iv-characteristic shifts approx -2 mV/˚C.

i

v

-2 mV/˚C

T2>T1

Reverse Bias Regime: The temp dependence of the reverse current is that of Is

Rule of Thumb: Typically, Is approx doubles for every 10 ˚C increase in Temp

Sedra & Smith, 4th Ed.

Breakdown Regime: The temperature coefficient of Zener diodes depends on both

voltage and current Note: sometimes "TC" is called "Temco"

i

Vz=6.8 V

Vz=5.1 V 0

Note: A 6.8 V Zener diode exhibits a TC≈+2 mV/˚C, which is complementary to a

forward biased diode!

0.7 V 6.8 V

≈7.5 V

-← nearly independent of T (over a useful range of i)

e.g Consider the following circuit:

R

10 kΩ

V +

-10 V

V

I

VDD=IR+V (1)

I= IS(eV/ nVT −1) (2)

DD

Exact Solution: If Is and n for the diode are known, then (1) and (2) can be solved

simultaneously to obtain I and V

Graphical Solution: If data are available, then (1) and (2) could be plotted and I and V could be obtained from the intersection

/R

v

i

0 I

V

Load Line

Quiescent (Operating) Point, Q

a similar graphical method is used for the analysis of transistors - later

VDD V

DD

Approximate Solution: If an exact solution is not required, an approximation can be found using an iterative approach:

e.g. Suppose the diode is specified as exhibiting a 0.7 V drop at 1 mA (in the text, this

is sometimes called "a 1-mA diode" for short), with n=1.8

step 0) Assume that the diode can be adequately described by I≅IseV/nVT (2')

Substitute I=1 mA and V=0.7 V (from specs.) to calculate Is

Is=10− 3

e− 0.7/nV T

which yields

I=10− 3

e(V− 0.7)/nVT

or V=nVTln(I /10− 3

step 1) As a first guess/approximation, assume V=0.7 V,

then I=VDD−V

R =10 V - 0.7 V

10 kW =0.93 mA The accuracy can be improved by iterating between (1) and (2'') as follows:

step 2) Substitute the value of I found in step 1 into (2'') to calculate a new value for V

V=(1.8)(0.025)ln(0.93)+0.7=696.7 mV

step 3) Substitute this value back into (1), to calculate a new value for I

I=10 V - 0.697 V

10 kW =0.9303 mA

step 4) Continue iterating between (1) and (2'') until

(In−In− 1)

In ≤1% (arbitrary precision)

Graphical representation of iterative method:

V /R

V

v

i

0

Load Line (1)

1 2

5

.7 697 93

.9303

(2)

DD

DD

Alternatively, appropriate simplifying assumptions can yield an approximate solution Diode Models (for approximate analyses):

1 Exponential Model (ID =IseVD /nV T)

4 Piecewise-Linear (or Battery-plus-Resistance) Model 

5 Small-Signal Model (later)

(see Figs 3.1, 3.24, 3.21 of S&S 4th ed - linearized "Large-Signal" diode models) The choice of which model to apply in a given design/analysis depends on the operating point of the diode and the magnitude of the other voltages and currents in the circuit

e.g. Ideal Diode: may be adequate if VD is negligible compared to other voltages &

currents in the circuit

Constant-Voltage-Drop: gives a reasonable approximation at higher currents Piecewise-Linear: is useful at smaller currents (gives significant error at higher currents)

Small-Signal Model:

Consider the following prototype circuit:

v (t)

+

-V

i (t)

iD(t )=I

Se vD( t ) / nVT

D D

The expression for iD(t) can be expanded in a Taylor series about the operating point to

obtain

iD(t)≈ ID 1+ vd(t)

nVT



 





(Recall:

f (x)= f(x o)

0! +(x−x o)

1! f '( x o)+ (x− x o)2

2! f (x′ ′ o)+L) where ID =IseVD /nV T = diode current when vd(t)≡0,

which remains a good approximation provided

v d

nVT <<1 (e.g., vd<10mV at 20 ˚C)

Thus superimposed on the dc current ID, is a small-signal ac current id(t) such that

iD(t)=ID+id(t)

where

id(t)= ID

nVTvd(t) Note that the term ID/nVT has the dimensions of conductance, and hence

gd≡ ID

nVT = Small-Signal Conductance

and

rd ≡ nVT

ID = Small-Signal (or Incremental) Resistance

(see Fig 3.25 of S&S 4th ed - graphical representation of the Small-Signal diode model)

4 Rectifiers and Power Supplies

(see Fig 3.36 of S&S 4th ed - block diagram of a generalized DC Power Supply)

Objective: To transform an ac waveform applied to the input, to a rectified dc at the output

Rectifier Circuit

vi

t

vo

t 0

vo

vi

VDO

Simple Half-Wave Rectifiers:

R +

-rD

Ideal

VDO

+

Real Diode

-V DO could be any

dc bias voltage!

R+rD



 





 (vi−VD0) ; vi ≥ VD0

=0 ; vi<VD0

Peak Inverse Voltage, PIV = Maximum reverse bias voltage that D must withstand

without breakdown (e.g., vi for the circuit above)

Conduction Angle, 2θ =2cos−1(V D0 / V) (describes what fraction of ωΤ diode is "on")

0

0

ωt

ωt

2θ

V

V

V−VDO

RL+rD

v i =Vsinω t

v o

-V

Conduction Angle

VDO

If D is Ideal

If D is Real

Vcosθ =VDO or Vsin (π2 - ) θ

Threshold for conduction occurs at

v o

cos

∴ 2θ = -1 VDO V

=VDO 2

Aside: Effect of non-ideal characteristic is to cause distortion in the output waveform

In practise, vi is usually taken from the secondary winding of an appropriate transformer in order to efficiently set the desired amplitude and ensure isolation from the power

distribution system

9 Simple Full-Wave Rectifiers:

(see Figs 3.38, 3.39 of S&S 4th ed - FW Rectifiers )

Rectifier Circuits with Peak Detection:

Consider the following HW rectifier circuit with the load resistance replaced by a capacitor:

+

+

-D

C

v i

Vp

v o

Vp

This circuit can be viewed as a peak detector with an infinite load resistance If the diode is

considered to be ideal, then vo is clamped at Vp

In practical circuits, some finite load resistance always exists (e.g., input impedance of

subsequent stages), through which C can discharge during the diode "off cycle"

v

+

-D

+

vi(t)=Vp cos(ωt)

assuming the capacitor and resistor are ideal, and that a steady-state is reached prior to t=0

v o

Vp

Vr

v i

τ=RLC

If RLC>>2π/ω, then Vr<<Vp

Peak Rectifiers:

(see separate set of notes focusing on analysis of HW Peak Rectifier)

5 Other Diode-Capacitor Circuits

Clamped Capacitor (dc Restorer)

RL

+

+

C

1) If RL→∞ and the diode & capacitor are ideal:

D is forward biased only when vi<vc Hence, C charges to the most negative peak of vi

(during the first few cycles) and D remains reverse biased thereafter

Restores dc component that may have been filtered out of a signal—hence "dc Restorer" (dumb name, since you don't necessarily get back exactly what was filtered out; a better name would be "bipolar-to-monopolar converter", since the waveshape is maintained, but the dc level is shifted so that the signal is just monopolar)

0

t +Vp

-Vp'

vi

0

t

+Vp-Vp'

vo

+4V

-6V

+10V

2) If RL<∞ and rd>0, but the capacitor is still ideal:

During the positive part of the input waveform (when D is reverse biased), C discharges through RL During the negative part of the input waveform ("null output" part of the cycle), C recharges through rd Normally, one would try to arrange that rd<<RL

0

t

+Vp-Vp'

vo

+Vp-Vp'

Voltage Doubler:

Consider a clamped capacitor "module" cascaded with a peak-detector "module" as shown:

+

+

-vc

D1

C2

The clamping circuit determines VD1, which becomes the input to the peak

rectifier/detector

0 ωt

v i

Vs

v i =Vssinω t

v D1

Vs

2

Vs

v o

Vs

2

Vs

If C1 and D1 are ideal, then C1 will charge to -Vs, which provides a dc offset of Vs to the signal passed to the peak rectifier and C2 will charge to 2Vs (i.e., the "peak" voltage passed

from the clamp) If C2 and D2 are ideal, then Vo= 2Vs=constant

Alternatively,

+

+

C2

If C1 and D1 are ideal, then C1 will charge to Vs, which provides a dc offset of -Vs to the signal passed to the peak rectifier and C2 will charge to -2Vs (i.e., the negative "peak"

voltage passed from the clamp) If C2 and D2 are ideal, then Vo=-2Vs=constant

Limiting or Clipping Circuits:

The general transfer characteristic of a limiter circuit is described by

vo = Kvi ; L-/K ≤ vi ≤ L+/K (i.e., linear)

= L+ ; vi > L+/K

= L- ; vi < L-/K

or, graphically

v i

v o

1 K

L+/K L-/K

L+

L-"soft" limiting

"hard" limiting

Passive Limiter: 0 < |K| < 1

Active Limiter: 0 < |K| (more about this later!)

Limiting circuits can be realized using regular or Zener diodes and resistors in various configurations

(see Fig 3.46 of S&S 4th ed - various basic limiter circuits)