Tài liệu Arithmetic Circuits ppt

Express Sum and Carry as a function of P, G, DDefine 3 new variable which ONLY depend on A, B... The Ripple-Carry AdderWorst case delay linear with the number of bits Goal: Make the fast

Digital Integrated Circuits

A Design Perspective

Arithmetic Circuits

Jan M Rabaey Anantha Chandrakasan Borivoje Nikolic

January, 2003

A Generic Digital Processor

Building Blocks for Digital Architectures

b

s0 s1

g64

LU : Logical Unit

Bit-Sliced Design

Bit 3Bit 2Bit 1Bit 0

Bit-Sliced Datapath

Adder stage 1 Wiring Adder stage 2

Itanium Integer Datapath

Adders

Cout Sum

adder

The Binary Adder

Cin Full

adder

Express Sum and Carry as a function of P, G, D

Define 3 new variable which ONLY depend on A, B

The Ripple-Carry Adder

Worst case delay linear with the number of bits

Goal: Make the fastest possible carry path circuit

Complimentary Static CMOS Full Adder

28 Transistors

B A

C i

C i A B

C o

V DD

Minimize Critical Path by Reducing Inverting Stages

Exploit Inversion Property

A Better Structure: The Mirror Adder

V DD

C i

A B B

A

B A

C i

A B B

The Mirror Adder

A maximum of two series transistors can be observed in the generation circuitry.

carry-•When laying out the cell, the most critical issue is the

minimization of the capacitance at node Co The reduction of the diffusion capacitances is particularly important.

capacitances, two internal gate capacitances, and six gate

capacitances in the connecting adder cell

•Only the transistors in the carry stage have to be optimized for

optimal speed All transistors in the sum stage can be minimal

Transmission Gate Full Adder

A

B P

P

Sum Generation

Carry Generation

Setup

Manchester Carry Chain

Manchester Carry Chain

Manchester Carry Chain

Carry-Bypass Adder (cont.)

Carry propagation

Setup Bit 0–3

Setup Bit 4–7

Sum

t bypass

Carry propagation

Setup Bit 8–11

Sum

Carry propagation

Setup Bit 12–15

Sum

Carry Ripple versus Carry Bypass

Carry Select Adder: Critical Path

0

1

Sum Generation

Multiplexer 1-Carry 0-Carry Setup

0

1

Sum Generation Multiplexer 1-Carry

S

Linear Carry Select

Square Root Carry Select

Adder Delays - Comparison

Square root select

Linear selectRipple adder

100

20304050

LookAhead - Basic Idea

Look-Ahead: Topology

Co k, = Gk+ Pk( Gk 1– + Pk 1– Co k 2, – )

Expanding Lookahead equations:

All the way:

Logarithmic Look-Ahead Adder

Carry Lookahead Trees

Example: Domino Adder

Example: Domino Adder

Example: Domino Sum

Multipliers

The Binary Multiplication

The Binary Multiplication

x

+

Partial products

Multiplicand Multiplier

The Array Multiplier

The MxN Array Multiplier

— Critical Path

HA FA FA HA

HA FA

FA FA

FA

Critical Path 1 Critical Path 2

Critical Path 1 & 2

Carry-Save Multiplier

FA FA

FA HA

Multiplier Floorplan

S C S

C S

C S

C

S C S

C S

C S

C

S C S

C S

C S

C

S

C S

C S

C S

Multipliers —Summary

• Optimization Goals Different Vs Binary Adder

• Once Again: Identify Critical Path

• Other possible techniques

- Data encoding (Booth)

- Pipelining FIRST GLIMPSE AT SYSTEM LEVEL OPTIMIZATION

- Logarithmic versus Linear (Wallace Tree Mult)

Shifters

The Binary Shifter

The Barrel Shifter

Sh3 Sh2

Sh1 Sh0

Sh3 Sh2

Area Dominated by Wiring

4x4 barrel shifter

Buffer

Sh3 Sh2

Sh1 Sh0