MSI MS 7928 rev 1 1 схема

MICRO-START INT'L CO.,LTD.Clock Distribution CTitle MICRO-START INT'L CO.,LTD.. Clock Distribution CTitle MICRO-START INT'L CO.,LTD... MICRO-START INT'L CO.,LTD.GPIO/MSIC/ TABLE CTitle M

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A A

Title

MICRO-START INT'L CO.,LTD.

COVER SHEET

CustomTitle

COVER SHEET

CustomTitle

DDR III * 2 (max 16G)

PCI Express X1 Slot * 2

Controller - Intersil 62773+6208/4+2 Phase PCI Express X16 Slot * 1

12

14~18

21

29 30 31

7 1

BLOCK DIAGRAM

DDR REF POWER AND CAPS

PWRGD&RESET Map

24 25

Auto BOM manual

ATX/F_Panel/EMI/LED

FCH CORE & DDR POWER

ACPI UPI & SYS POWER

SUPER I/O IT8728F

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Rear USB 3.0

USB 2.0 USB

2.0

28

i-SATA 4 SERIAL ATA 3.0

DP1

DVI-D CON

PCIE INTERFACE

31 SUPER I/O ITE8728F

31 PORT2 SERIAL

25 RTL8111E-VC

DDR3 DRAM POWER

FCH CORE POWER

Intersil ISL6208

NB CORE POWER ACPI CONTROLLER

32

20 16

31 TPM GPIO

30 FAN

31 PS2

31 LPC

PCIE x16 PCIE GFX x16

22

DP2

DP CON 19

31 LPT

31 SERIAL PORT1

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Power Deliver Chart

CustomTitle

Power Deliver Chart

CustomTitle

+5VA Linear REGULATOR

VDD 5VDual VDD

5VDual

USB 2.0 X2 FR

ENTHERNET

+3.3V (S0, S1) +3.3VDUAL (S3)

SUPER I/O

VCC3_SB SW

1.1V_SB Linear REGULATOR+1.1VDUAL(S0,S1,S3,S5) VCC3_SB (S0, S1, S3, S5)

AUDIO CODEC

5V ANALOG 3.3V CORE

SVCC Linear REGULATOR

CPU_VDDP FM2+:1.05V;FM2:1.2A

AMD FM2 CPU

VDDA FM2+:1.8V ;FM2:2.5V 0.9A

5A

CPU PW 12V +/-5%

VCCP (S0, S1) / VCC_NB (S0, S1) VRM SW

REGUALTOR

2.5V Shunt Regulator

VDDA25 (S0, S1)

DDR3 MEM I/F 1.5V VCC_DDR 0.8~2.3V 1.5V-5A; 1.35-4.9A;

0.1A

0.01A 0.01A

1.0A 1.0A

VDDNBCORE

VDDCORE 0.8-2V 120A

CPU_VDDP (S0, S1)

1.1V VCCP SW REGULATOR

NB_VCC1P1 (S0, S1)

300mA 3.3V 1.05V

1.2V VDDR REGULATOR

CPU_VDDR (S0, S1)

VCC3 (S0, S1)

VCC3_WAKE Linear REGULATOR

VCC5_SB FET REGULATOR

VDDAN_11_ML VDDCR_11

VDDIO_33_S VDDAN_11_SATA

5VDual VDD

USB 3.0 X2 FR

5VDual VDD

USB 3.0 X2 RL

+12V VCC5

12V +/-5%

-12V +/-5%

ATX P/S WITH 1A STBY CURRENT 5VSB

+/-5%

5V +/-5%

3.3V +/-5%

5VDual VDD

USB 2.0 X2 FR

1.0A

2XPS/2

5VDual 0.5A

USB 2.0 X2 RL

5VDual VDD

1.0A

USB 2.0 X2 RL

1.0A VDD 5VDual

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Clock Distribution

CTitle

Clock Distribution

CTitle

14M_25M_48M_OSC

24MHZ AZ_BIT_CLK

xxHZ SPI_CLKSPI ROM & HEADER

HD AUDIO

LPCCLK0 RTCCLK

PCICLK3

PCICLK0

LPC_CLK0 33MHZ

33MHZ

PCICLK0

PCI_CLK3 33MHZ

UNUSED CLOCKSSIO ITE8733FSTRAPS SETTING,

LPCCLK1

AMD HudsonD3

STRAPS SETTING,LPCCLK1

FCH_DISP_CLKP

FCH_GFX_CLKP/NFCH_GPP_CLK0P/N

FCH_GPP_CLK2P/N

INTERNAL CLOCK MODE

PCIE GPP SLOT2 (BoltonD3, 1 LANE) PCIE X1 SLOTPCIE GPP SLOT3 (BoltonD3, 1 LANE) Mini PCIE X1 SLOT PE1_GPP_CLK0/PE1_GPP_CLK0#

100MHZ PE_MINI_CLK/PE_MINI_CLK#

PE1_GPP_CLK1/PE1_GPP_CLK1#

100MHZ 100MHZ 100MHZ PE16_GXF_CLK/PE16_GXF_CLK#

PCIE GPP SLOT1 (BoltonD3, 1 LANE)PCIE GFX SLOT (FM2+, 16 LANES) PCIEX16 SLOT

PCICLK4

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PWRGD&RESET MAP

CustomTitle

PWRGD&RESET MAP

CustomTitle

BoltonD3,

HUDSON D3/D2

APU_PWRGDAPU_PG(Pin E26)

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GPIO/MSIC/ TABLE

CTitle

GPIO/MSIC/ TABLE

CTitle

DIMMs SCLK0/SDATA0 FCH

LINKED DEVICE SINGLE NAME

Pin Function

USB_EN

GP22 GP67

PS2_EN LPT_DET#

LANPWR_EN PWR_LED

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NB_VSUM-SVC

VRM_PWRGD_RVCORE_EN

VSUM-PH2_NB

LG2_NB

NB_VSUM+

NB_ISEN1BOOT2_NB PH2_NB

PWM2_NB

ISEN2

NB_ISEN2UG1

NB_ISEN2

SVC

VRM_PWROKSVDSVT

PWM2_NBBOOT2_NB

BOOT3

PWMY

PWMYPH2

CPU_VDDNB

VCC5

CPU_VDDNBVCCP

VCC5 VCC5

VCCPVIN

VIN

CPU_VDDNBVCC5

VCCPVCCP

VIN

VCCPVIN

VCC5

CPU_VDDNBVIN

Size Document Number Rev

ISL62773+6208

CustomTitle

ISL62773+6208

CustomTitle

ISL62773+6208

Custom

Make sure +12VIN

Q18N-2N7002P_SOT23-3-HFQ18N-2N7002P_SOT23-3-HF

BOOT2FCCM7PWM3UGATE1PHASE8VCC6LGATE5GND

Q16

N-PK516BA_PDFN8-HF

Q16

N-PK516BA_PDFN8-HF2

C57C2.2u6.3X5C57C2.2u6.3X5

Q11

N-PK510BA_PDFN8-HFQ11

VR_HOT_L5SVD6

VDDIO7SVT8

ENABLE9

PWROK10

IMON11NTC12

ISEN313ISNE214ISNE115ISUMP

16

ISUMN17

VSEN18

RTN19

FB220COMP22

PGOOD23

VSEN_NB45

ISUMN_NB46ISUMP_NB

FB_NB44

34

R260R0805R260R0805SP1

Q27

N-PK510BA_PDFN8-HFQ27

Q22

N-PK516BA_PDFN8-HF

Q22

N-PK516BA_PDFN8-HF2

BOOT2FCCM7PWM3UGATE1PHASE8VCC6LGATE5GND

D6 S-RB751V-40_SOD323-RH

C3 C2.2u6.3X50402C3 C2.2u6.3X50402

C70

C1000p50X0402

C70

C1000p50X0402

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UMI_TX3N_APU UMI_TX3P_APU UMI_TX2P_APU UMI_TX2N_APU

APU_P_ZVDDP

GFX_TXP0 GFX_TXP1 GFX_TXP2 GFX_TXP3 GFX_TXP4 GFX_TXP5 GFX_TXP6 GFX_TXP7 GFX_TXP8 GFX_TXP9 GFX_TXP10 GFX_TXP11 GFX_TXP12 GFX_TXP13 GFX_TXP14 GFX_TXP15

LAN_RXP

CPU_VDDP

GFX_RX6P 22 GFX_RX6N 22

GFX_RX0P 22

GFX_RX0N 22

UMI_TX1P 14 UMI_TX1N 14

UMI_TX0P 14 UMI_TX0N 14 UMI_RX0P

14 UMI_RX0N 14 UMI_RX1P 14 UMI_RX1N 14 UMI_RX2P 14 UMI_RX2N 14 UMI_RX3P 14 UMI_RX3N 14

GFX_TXC_13P 22 GFX_TXC_9P 22

GFX_TXC_13N 22 GFX_TXC_9N 22

GFX_TXC_0P 22 GFX_TXC_1P 22 GFX_TXC_2P 22 GFX_TXC_3P 22 GFX_TXC_4P 22 GFX_TXC_5P 22 GFX_TXC_6P 22

LAN_RXP 25 LAN_RXN

Title Size Document Number Rev

P_GPP_RXN3

AD6 P_GPP_RXP3 AD5 P_GPP_RXN2 AE8 P_GPP_RXP2 AE7 P_GPP_RXN1 AF9 P_GPP_RXP1 AF8 P_GPP_RXN0 AF6 P_GPP_RXP0 AF5

P_GFX_RXN15

P9 P_GFX_RXP15 P8 P_GFX_RXN14 P6 P_GFX_RXP14 P5 P_GFX_RXN13 R8 P_GFX_RXP13 R7 P_GFX_RXN12 T9 P_GFX_RXP12 T8 P_GFX_RXN11 T6 P_GFX_RXP11 T5 P_GFX_RXN10 U8 P_GFX_RXP10 U7 P_GFX_RXN9 V9 P_GFX_RXP9 V8 P_GFX_RXN8 V6 P_GFX_RXP8 V5 P_GFX_RXN7 W8 P_GFX_RXP7 W7 P_GFX_RXN6 Y9 P_GFX_RXP6 Y8 P_GFX_RXN5 Y6 P_GFX_RXP5 Y5 P_GFX_RXN4 AA8 P_GFX_RXP4 AA7 P_GFX_RXN3 AB9 P_GFX_RXP3 AB8 P_GFX_RXN2 AB6 P_GFX_RXP2 AB5 P_GFX_RXN1 AC8 P_GFX_RXP1 AC7 P_GFX_RXN0 AD9 P_GFX_RXP0 AD8

P_ZVSS AJ1

P_UMI_TXN3 AG4

P_UMI_TXP3 AG5 P_UMI_TXN2 AG2 P_UMI_TXP2 AG1 P_UMI_TXN1 AH2

P_UMI_TXP1 AH3

P_UMI_TXN0 AJ4

P_UMI_TXP0 AJ5 P_GPP_TXN3 AD3 P_GPP_TXP3 AD2

P_GPP_TXN2 AE5

P_GPP_TXP2 AE4

P_GPP_TXN1 AE1 P_GPP_TXP1 AE2 P_GPP_TXN0 AF3 P_GPP_TXP0 AF2

P_GFX_TXN15 N1

P_GFX_TXP15 N2 P_GFX_TXN14 P3 P_GFX_TXP14 P2 P_GFX_TXN13 R5

P_GFX_TXP13 R4

P_GFX_TXN12 R1 P_GFX_TXP12 R2 P_GFX_TXN11 T3 P_GFX_TXP11 T2 P_GFX_TXN10 U5

P_GFX_TXP10 P_GFX_TXN9 U4 U1

P_GFX_TXP9 U2 P_GFX_TXN8 V3 P_GFX_TXP8 V2 P_GFX_TXN7 W5

P_GFX_TXP7 W4

P_GFX_TXN6 W1

P_GFX_TXP6 W2 P_GFX_TXN5 Y3 P_GFX_TXP5 Y2

P_GFX_TXN4 AA5

P_GFX_TXP4 AA4

P_GFX_TXN3 AA1

P_GFX_TXP3 AA2 P_GFX_TXN2 AB3 P_GFX_TXP2 AB2

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MEM_MA_ADD10MEM_MA_ADD3

MEM_MA_BANK0

MEM_MA_DM0MEM_MA_DM3MEM_MA_DM6

MEM_MA_DQS_H0MEM_MA_DQS_L0MEM_MA_DQS_H1MEM_MA_DQS_L2MEM_MA_DQS_H3MEM_MA_DQS_L3MEM_MA_DQS_H4MEM_MA_DQS_L5MEM_MA_DQS_H6MEM_MA_DQS_L7

MEM_MA_DATA0MEM_MA_DATA3

MEM_MA_DATA7MEM_MA_DATA9MEM_MA_DATA11

MEM_MA_DATA17

MEM_MA_DATA57

MEM_MA_DATA49

MEM_MA_DATA41

MEM_MA_DATA33

MEM_MA_DATA25

MEM_MA_CAS_LMEM_MA_RESET#

MEM_MB_DQS_H5MEM_MB_DQS_L5

MEM_MB_DATA56MEM_MB_DATA59MEM_MB_DATA62

MEM_MB_DM0

MEM_MB1_CS_L0

APU_MB_VREFDQMEM_MB_DM1

MB_ZVDDIO

MEM_MB_DQS_H7MEM_MB_DQS_L7MEM_MB_DM2

MEM_MB_DATA0

MEM_MB_DM4MEM_MB_DM7

MEM_MB_CLK_L0MEM_MB_CLK_H0

MEM_MB_CLK_H3MEM_MB_CLK_L3

MEM_MB_DATA1

MEM_MB_DQS_H1MEM_MB_DQS_L1MEM_MB_BANK0

MEM_MB_DATA2MEM_MB_DATA5

MEM_MB_RAS_LMEM_MB_WE_LMEM_MB_RESET#

MEM_MB_HOT#

MEM_MB_ADD0MEM_MB_ADD3MEM_MB_ADD6MEM_MB_ADD9MEM_MB_ADD10MEM_MB_ADD13

MEM_MB_BANK1

MEM_MB_CKE0

MEM_MB_DATA32MEM_MB_DATA35MEM_MB_DATA38MEM_MB_DQS_L4

MEM_MB_DQS_H4MEM_MB_BANK2

MEM_MB1_ODT0MEM_MB_CKE1

MEM_MA_HOT#

MEM_MA1_ODT0

MEM_MA1_CS_L1

MEM_MA_CLK_L0MEM_MA_CLK_H0

MEM_MA_CLK_L3MEM_MA_CLK_H3

12MEM_MA_DQS_L[7 0]

12MEM_MB_DQS_L[7 0]

12

MEM_MB_ADD[15 0]

12MEM_MB_BANK012MEM_MB_BANK112MEM_MB_BANK212

MEM_MB_CKE012MEM_MB_CKE112

MEM_MB1_ODT012MEM_MB1_ODT112

MEM_MB1_CS_L112MEM_MB1_CS_L012

MEM_MB_DATA[63 0] 12

MEM_MB_CLK_H012MEM_MB_CLK_L012

MEM_MB_CLK_L312MEM_MB_CLK_H312

MEM_MB_CAS_L12MEM_MB_WE_L12MEM_MB_RAS_L12

MEM_MB_RESET#

12MEM_MB_HOT#

12APU_MB_VREFDQ13APU_MA_VREFDQ

FM2 DDR3 I/F

CTitle

FM2 DDR3 I/F

CTitle

MA_DATA63AD15MA_DATA62AG16MA_DATA61AF18MA_DATA60AD18MA_DATA59AG15MA_DATA58AF15MA_DATA57AE17MA_DATA56AG18MA_DATA55AD19MA_DATA54AE20MA_DATA53AE22MA_DATA52AD22MA_DATA51AG19MA_DATA50AE19MA_DATA49AD21MA_DATA48AG22MA_DATA47AD24MA_DATA46AF24MA_DATA45AE26MA_DATA44AD27MA_DATA43AE23MA_DATA42AF23MA_DATA41AD25MA_DATA40AF26MA_DATA39AD28MA_DATA38AG28MA_DATA37AE31MA_DATA36AD31MA_DATA35AF27MA_DATA34AG27MA_DATA33AF30MA_DATA32AD30MA_DATA31G31MA_DATA30F31MA_DATA29F28MA_DATA28H27MA_DATA27H30MA_DATA26H29MA_DATA25E29MA_DATA24G28MA_DATA23H26MA_DATA22E26MA_DATA21E24MA_DATA20H23MA_DATA19F27MA_DATA18E27MA_DATA17H24MA_DATA16F24MA_DATA15G22MA_DATA14F22MA_DATA13E20MA_DATA12G19MA_DATA11G23MA_DATA10MA_DATA9MA_DATA8 E23H20G20MA_DATA7 F18MA_DATA6 E18MA_DATA5 H15MA_DATA4 F15MA_DATA3 F19MA_DATA2 H18MA_DATA1 G16MA_DATA0 F16

MA_RESET_LJ25MA_RAS_LW25MA0_CS_L1AB26MA1_ODT1AC26

MA1_CS_L0W23

MA0_ODT0AA24

MA_EVENT_LU24

M_VREFK22

MA0_ODT1AC27

MA_CAS_LY24

MA_CKE0L23MA_CKE1K26

MA_ZVDDIO(FM2:M_ZVDDIO)J24

MA1_ODT0AA25

MA_WE_LY26MA1_CS_L1AB25MA0_CS_L0Y27

MA_VREFDQ(FM2:VSS)E15

MB_DATA63AH16MB_DATA62AK16MB_DATA61AK18MB_DATA60AH19MB_DATA59AK15MB_DATA58AJ15MB_DATA57AH17MB_DATA56AJ18MB_DATA55AL20MB_DATA54AH20MB_DATA53AL22MB_DATA52AL23MB_DATA51AK19MB_DATA50AL19MB_DATA49AH22MB_DATA48AK22MB_DATA47AK24MB_DATA46AJ24MB_DATA45AL26MB_DATA44AK27MB_DATA43AJ23MB_DATA42AH23MB_DATA41AH26MB_DATA40AJ26MB_DATA39AL28MB_DATA38AK28MB_DATA37AH31MB_DATA36AG30MB_DATA35AJ27MB_DATA34AH28MB_DATA33AK30MB_DATA32AJ30MB_DATA31C30MB_DATA30B30MB_DATA29A28MB_DATA28B27MB_DATA27D31MB_DATA26C31MB_DATA25D28MB_DATA24C28MB_DATA23A26MB_DATA22D26MB_DATA21B23MB_DATA20A23MB_DATA19C27MB_DATA18B26MB_DATA17B24MB_DATA16C24MB_DATA15C22MB_DATA14A22MB_DATA13D19MB_DATA12C19MB_DATA11D23MB_DATA10MB_DATA9MB_DATA8 D22A20D20MB_DATA7 C18MB_DATA6 D17MB_DATA5 B15MB_DATA4 C15MB_DATA3 A19MB_DATA2 B18MB_DATA1 C16MB_DATA0 A16

MB0_CS_L0Y29

MB_WE_LAA28MB1_CS_L1AB31

MB_RESET_LJ27

MB1_CS_L0Y30

MB_EVENT_LV28

MB0_CS_L1AB29

MB_RAS_LW28MB_CAS_LAA27

MB_VREFDQ(FM2:VSS)D14MB_ZVDDIO(FM2:RSVD5)K25

R141 1KR0402R141 1KR0402R153 1KR0402R153 1KR0402

R137 39.2R1%0402R137 39.2R1%0402

R139

1KR1%

R139

1KR1%

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APU_TEST20

APU_PWROK_BUF

CPU_TDICPU_TMSCPU_TCKCPU_TRST_LCPU_DBREQ_L

APU_THERMTRIP#

APU_PROCHOT#

APU_FM2R1FCH_DMA_ACTIVE#

APU_SIC_RAPU_SID

APU_RST#

APU_SVC

VDDR_SENSE

APU_SIC_RAPU_SIC

APU_SVT

APU_RST#

APU_PWRGDAPU_THERMTRIP#

APU_PROCHOT#

APU_ALERT#

CPU_TDO

CPU_DBRDYCPU_TDICPU_TMSCPU_TCKCPU_TRST_LCPU_DBREQ_L

VDDP_SENSE

DP_AUX_ZVSSAPU_BLONAPU_DIGONAPU_BLPWM

DP5_HPD

DP1_TX0P_APUDP1_TX0N_APUDP1_TX1P_APUDP1_TX1N_APUDP1_TX2P_APUDP1_TX2N_APUDP1_TX3P_APUDP1_TX3N_APU

DP0_TX0P_APUDP0_TX0N_APUDP0_TX1P_APUDP0_TX1N_APUDP0_TX2P_APUDP0_TX2N_APUDP0_TX3P_APUDP0_TX3N_APU

LDTSTOP_LFM_IDLEEXIT_L

APU_TEST17APU_TEST14

APU_TEST19APU_TEST25_HAPU_TEST4

APU_TEST32LAPU_TEST32_HAPU_TEST30_HAPU_TEST25_L

APU_TEST31APU_TEST28_H

APU_TEST35APU_TEST24

APU_FM2R1FCH_DMA_ACTIVE#

APU_TEST6APU_TEST10

DP2_TX2N_APUDP2_TX2P_APUDP2_TX1N_APUDP2_TX1P_APU

DP2_TX3N_APUDP2_TX3P_APU

COREFB- 7

APU_PWRGD7,1415 APU_RST#

DP0_AUXN_C16DP0_AUXP_C16

NB_SENSE+ 7

DP0_HPD_VGA_C 16DP1_HPD_DVI_C20

VDDIOFB+ 33

DP1_TX0P20DP1_TX0N20DP1_TX1P20DP1_TX1N20DP1_TX2P20DP1_TX2N20DP1_TX3P20DP1_TX3N20

DP0_TX0P16DP0_TX0N16DP0_TX1P16DP0_TX1N16DP0_TX2P16DP0_TX2N16DP0_TX3P16DP0_TX3N16

APU_CLK14APU_CLK#

14DISP_CLK14DISP_CLK#

14

APU_FM2R17,33FCH_DMA_ACTIVE# 14LDTSTOP_L14

FCH_IDLEEXIT_L 16

APU_SVC7APU_SVD7

NB_SENSE-7

VOLT_SELECT 13,19,32,33

DP2_TX0P_APU19DP2_TX0N_APU19DP2_TX1N_APU

19DP2_TX1P_APU19

DP2_TX3P_APU19DP2_TX2N_APU

19DP2_TX2P_APU19

DP2_TX3N_APU19

DP2_HPD_DP_C19

APU_PROCHOT#

14

APU_SVT7

Title

FM2 DISPLAY/MSIC

CTitle

FM2 DISPLAY/MSIC

CTitle

ROUTE PCIE AS 85OHM +/-10%

Layout: Place within 1.5'' of APU

HDT+ Connector

SCAN Conn,

FM1 DISPLAY I/F

GPU DEBUG WARM RESET

Layout: Place close to HDT header

Note: Several vias on the DP0 interface violate the minimum distance rules

for via to via spacing between diff pairs These violations have been reviewed and approved

on an individual basis, and pose no significant singal integrity issues for this implementation since

PULL UP

TEST2, TEST3, TEST6, TEST10, TEST23, TEST28_H TEST28_L, and any RSVD pins have no connections

TEST4, TEST5, TEST[17:14], TEST25_H/L,TEST30_H/L, and TEST32_H/L have onboard test points

Layout: Place within 1.5'' of APU

H:HDMI ENABLE

CORE TYPE LOGIC

For FM2+ colay

TN/RD KV TBD TBD

CORETYPE0 CORETYPE1

1 1 0 0 0 0

Display Port

Display PortDVI-D

DVI-D

FCHFCH

FCH

C121C0.1u10X0402C121C0.1u10X0402

R180 300R0402

TP23

Q31X_N-SST3904_SOT23Q31X_N-SST3904_SOT23

CE

R172 1KR0402R172 1KR0402

TP21

R701 X_1KR0402R701 X_1KR0402

TP22

R194 0R0402R194 0R0402

34

D

Q33N-2N7002

C126C0.1u10X0402C126C0.1u10X0402

R171 1KR0402R171 1KR0402

R158 1KR0402R158 1KR0402

C119C0.1u10X0402C119C0.1u10X0402

R195 0R0402R195 0R0402

TP11

C133C0.1u10X0402C133C0.1u10X0402

R776 X_1KR0402R776 X_1KR0402

R170 1KR0402R170 1KR0402

Q29AX_NN-CMKT3904_SOT363-6-RHQ29AX_NN-CMKT3904_SOT363-6-RH

61

C132C0.1u10X0402C132C0.1u10X0402

TP17

TP6

TP16

R147 100KR0402R147 100KR0402

R182 1KR0402

C134C0.1u10X0402C134C0.1u10X0402

Q34NN-CMKT3904_SOT363-6-RHQ34NN-CMKT3904_SOT363-6-RH

R166 10R0402

R174 0R0402R174 0R0402

D

Q32N-2N7002

D

Q32N-2N7002

R142 150R1%0402R142 150R1%0402

TP13

C125C0.1u10X0402C125C0.1u10X0402

R19310KR0402R19310KR0402

R143 X_0R0402R143 X_0R0402

R156 1KR0402R156 1KR0402

R188 20KR0402-2R188 20KR0402-2

R146 X_10KR0402R146 X_10KR0402

R148 100KR0402R148 100KR0402

R1781.8KR0402R1781.8KR0402

R173 1KR0402R173 1KR0402

R165 300R0402R165 300R0402

C130C0.1u10X0402C130C0.1u10X0402

C127C0.1u10X0402C127C0.1u10X0402

R183 1KR0402

R1671KR0402R1671KR0402

R149 100KR0402R149 100KR0402

R157 1KR0402R157 1KR0402R662 X_1KR0402R662 X_1KR0402

R175 0R0402R175 0R0402

R177 1KR0402

R1791.8KR0402R1791.8KR0402

C128C0.1u10X0402C128C0.1u10X0402

TP19

R169 1KR0402R169 1KR0402

VSS_SENSEB4VDDR_SENSEVDD_SENSE C4B3VDDIO_SENSEA4VDDNB_SENSEVDDP_SENSEA3C3RSVD8AG10RSVD7AC24RSVD6AB23RSVD4K23RSVD3AD12RSVD1(FM2:CORETYPE)F9CORETYPE0(FM2:RSVD1)BP5/IDLEEXIT_LDMAACTIVE_LLDTSTOP_LAJ13G12AD10AG14FM2R2(FM2:FM2R1)AC10TEST35AE14TEST32_LR22TEST32_HTEST31V22AG31TEST30_LU22TEST30_HT22TEST28_LJ10TEST28_HH10TEST25_LAH11TEST25_HTEST24AJ11E14TEST20F14TEST19G14TEST18G13TEST17E13TEST16F13TEST15E12TEST14F12TEST10TEST9R21P21TEST6AD14TEST5U21TEST4T21DP5_HPDG7DP4_HPDF7DP3_HPDE7DP2_HPDG3DP1_HPDF3DP0_HPDE3DP5_AUXNDP5_AUXPG6G5DP4_AUXNDP4_AUXPF6F5DP3_AUXNDP3_AUXPE6E5DP2_AUXNDP2_AUXPG2G1DP1_AUXNDP1_AUXPF2F1DP0_AUXNDP0_AUXPE2E1DP_VARY_BLDP_DIGONE8G8DP_BLONF8DP_AUX_ZVSSG9

CORETYPE1(FM2:RSVD2)AH13

Trang 11

CPU_VDDR

CPU_VDDNB

CPU_VDDPCPU_VDDRCPU_VDDNB

VDDNB = 0.8V (Variable)

BOTTOM SIDE DECOUPLING

VDDR = 1.2VVDDPCIE = 1.2VONLY ONE SIDE OF VDDPCIE & VDDR MUSTCONNECTED ON THE PCB.CONNECTING BOTH SIDESMUST BE DECOUPLED

Layout: Place close to Pins

1 1 99

/

/ 2

4 30

/

/ 2

VSS

2+2

1

TOTLE PINS

VDD

2 /

SPLIT

/

/ 4

1 nF/0603/X5R 22U/1206/X5R

180 pF/0603/X5R

10U/0805/X5R 4.7U/0805/X5R 0.22U/0603/X5R

/

1 2

/

/ /

2+1(B) 2

1 232

VDDNBCAP

2 /

Place across each VDDIO-GND plane seam

Layout: Place close to Pins

AC21VDD-20AC19VDD-19AC13VDD-18AC11AB4VDD-17VDD-16AB18VDD-15AB16VDD-14AB14VDD-13AB10AB1AA6AA3VDD-12VDD-11VDD-10VDD-9AA21VDD-8AA13W11M10AB7T20P10Y20VDD-7VDD-6VDD-5VDD-4VDD-3VDD-2VDD-1AA11

VDD-99K7VDD-98AF1VDD-97AH1VDD-96Y16VDD-95AA19VDD-94AA17VDD-93AA15VDD-92Y14VDD-91Y12VDD-90Y10VDD-89Y1VDD-88W21VDD-87AC15VDD-86AE6VDD-85U19VDD-84N21VDD-83J6VDD-82W19VDD-81W13VDD-80V7VDD-79V4VDD-78V12VDD-77V10VDD-76V1VDD-75U6VDD-74U3VDD-73V20VDD-72U11VDD-71T12VDD-70T10VDD-69R19VDD-68R13VDD-67R11VDD-66P7VDD-65P4VDD-64T1VDD-63P20VDD-62P12VDD-61P1VDD-60N3VDD-59N19VDD-58N11VDD-57N6VDD-56M20VDD-55M18VDD-54M16VDD-53M12VDD-52L21VDD-51L17

VDDP-9AK2VDDP-8AK6VDDP-7AK3VDDP-6AL6VDDP-5AL4VDDP-4AL3VDDP-3AL5VDDP-2AK5VDDP-1AK4VDDR-6AK10VDDR-5AL9VDDR-4AL8VDDR-3AK9VDDR-2AK8VDDR-1AL10VDDNB_CAP-2N13VDDNB_CAP-1VDDNB-30VDDNB-29VDDNB-28VDDNB-27VDDNB-26VDDNB-25VDDNB-24VDDNB-23VDDNB-22VDDNB-21VDDNB-20VDDNB-19VDDNB-18VDDNB-17VDDNB-16VDDNB-15VDDNB-14VDDNB-13VDDNB-12VDDNB-11VDDNB-10VDDNB-9VDDNB-8VDDNB-7VDDNB-6VDDNB-5VDDNB-4VDDNB-3VDDNB-2VDDNB-1M14A8C7C8C9C10C11C12C13C14C5B14B13B12B11B10B9B8B7B6B5A14A13A12A11A10C6A9A5A6A7

VDDA-2AD13VDDA-1AE13

MEC1MEC1MEC2MEC2MEC3MEC3MEC4MEC4

VSS-232AB11VSS-231J22VSS-230H1VSS-229M1VSS-228G4VSS-227K1VSS-226AK13VSS-225AK11VSS-224AE30VSS-223AE27VSS-222AE24VSS-221AE21VSS-220AE18VSS-219AE15VSS-218AE12VSS-217AE11VSS-216AE9VSS-215AJ22VSS-214AJ25VSS-213AJ28VSS-212AJ31VSS-211AK7VSS-210AD29VSS-209AD26VSS-208AD23VSS-207AD20VSS-206AD17VSS-205AJ19VSS-204AJ16VSS-203AJ12VSS-202AJ10VSS-201AJ9VSS-200AJ6VSS-199AJ3VSS-198AH30VSS-197AH27VSS-196AH24VSS-195AH21VSS-194AH18VSS-193AH15VSS-192AH12VSS-191AH10VSS-190AH4VSS-189AG29VSS-188AG26VSS-187AG23VSS-186AG20VSS-185AG17VSS-184AG13VSS-183AG11VSS-182AG9VSS-181AG3VSS-180AF31VSS-179AF28VSS-178AF25VSS-177AF22VSS-176AF11VSS-175AF13VSS-174AF16

C182C180p50N0402C182C180p50N0402

VSS-35E4VSS-34D30VSS-33D27VSS-32D24VSS-31D21VSS-30D18VSS-29D15VSS-27D13VSS-26D12VSS-25D11VSS-24D10D9D8D7D6D5D4D3D2VSS-23VSS-22VSS-21VSS-20VSS-19VSS-18VSS-17VSS-16VSS-15

C29VSS-14C26VSS-13C23VSS-12C20VSS-11C17VSS-10B28VSS-9B25VSS-8N22VSS-7B22VSS-6B19VSS-5B16VSS-4A27VSS-3A24VSS-2A21VSS-1A18

VSS-114AL13VSS-113AL15VSS-112AL11VSS-111AK17VSS-110A15VSS-109AL27VSS-108AL7VSS-107L22VSS-106L20VSS-105L18VSS-104L16VSS-103L14VSS-102L12VSS-101L10VSS-100VSS-99VSS-98VSS-97VSS-96VSS-95VSS-94VSS-93VSS-92VSS-91VSS-90VSS-89VSS-88VSS-87VSS-86VSS-85VSS-84VSS-83VSS-82VSS-81VSS-80VSS-79VSS-78VSS-77VSS-76VSS-75VSS-74VSS-73VSS-72VSS-71VSS-70VSS-69VSS-68VSS-67VSS-66VSS-65VSS-64VSS-63VSS-62VSS-61VSS-60VSS-59VSS-58L9L6J3K21K17K15K13K11J23J20J18J16J14J12N20N12N10N9M21M17M15M11M7H31H28H25H22H19H16H13H11H9H7H6H5H4G30G27R9M4R3P19P13

Trang 12

MEM_MA_DM5MEM_MA_DM0

MEM_MA_DQS_L7MEM_MA_DQS_L5

MEM_MA_DQS_H1

MEM_MA_DQS_H3MEM_MA_DQS_H0

MEM_MA_DQS_H4

MEM_MA_DQS_H6

MEM_MA_ADD13

MEM_MA_ADD5

MEM_MA_ADD8

MEM_SDATAMEM_SCLK

MEM_MB_DATA61

MEM_MB_DATA33

MEM_MB_DATA40

MEM_MB_DATA39

MEM_MB_DATA15

MEM_MB_DATA17

MEM_MB_DATA45

MEM_MB_DATA23

MEM_MB_DATA25

MEM_MB_DATA53

MEM_MB_DATA31

MEM_MB_DATA0

MEM_MB_DQS_L5MEM_MB_DQS_L0

MEM_MB_DATA63

MEM_MB_DQS_H3

MEM_MB_DQS_H7MEM_MB_DQS_H5MEM_MB_DQS_H2

MEM_MB_DM1

MEM_MB_DM6MEM_MB_DM4

MEM_MB_DM7

MEM_VREF_CAMEM_VREF_DQ_B

MEM_MB_HOT#

MEM_MB_ADD1

MEM_MB_ADD11MEM_MB_ADD2

MEM_SCLKMEM_SDATA

MEM_MB_BANK2MEM_MB_CKE0

MEM_MB_RAS_LMEM_MB_WE_L

MEM_MB1_ODT1MEM_MB_CKE1

MEM_MB_RESET#

MEM_MA_BANK1MEM_MA1_ODT1

MEM_MA_RAS_L

MEM_MA1_ODT0

MEM_MA1_CS_L1

MEM_MA_WE_LMEM_MA_CKE0

MEM_MA_CLK_L0MEM_MA_RESET#

VCC_DDR VCC3VTT_DDR

MEM_VREF_CA

VCC3VCC_DDR VCC3VTT_DDR

MEM_VREF_CAMEM_VREF_DQ_BMEM_VREF_DQ_A

SCLK0 15SDATA015

MEM_MB1_ODT0 9

MEM_MB1_CS_L0 9MEM_MB_CKE0 9

MEM_MB1_CS_L1 9MEM_MB_BANK0 9

MEM_MB_RAS_L 9MEM_MB1_ODT1 9

MEM_MB_WE_L 9MEM_MB_CKE1 9

MEM_MB_CLK_H0 9

MEM_MB_CLK_L3 9

MEM_MB_HOT# 9MEM_MB_DQS_H[7 0]

9MEM_MB_DQS_L[7 0]

9

MEM_MB_DATA[63 0]

9

MEM_MB_DM[7 0] 9MEM_MB_ADD[15 0]9

MEM_MB_RESET# 9MEM_MA_BANK2 9

MEM_MA1_CS_L1 9MEM_MA_BANK1 9

MEM_MA_CAS_L 9

MEM_MA_CKE0 9MEM_MA1_ODT0 9

MEM_MA_CLK_H3 9

MEM_MA_WE_L 9MEM_MA_RAS_L 9

MEM_MA_CLK_L0 9MEM_MA_CLK_H0 9

MEM_MA_CKE1 9MEM_MA1_ODT1 9

RESET#(Output) : A synchronously forces all registered output LOW when RESET# is LOW

This signal can be used during power up to ensure that CKE is LOW and DQs are High-Z.

Vref-DQ : Reference voltage for DQ0–DQ63, CB0–CB7 and PAR_IN When in single ended mode used for DQS0–DQS7.

Vref-CA : Reference voltage for A0-A15, BA0–BA2, RAS#, CAS#, WE#, S0#, S01#, CKE0, CKE1, ODT0 and ODT1.

CS0#193CS1#76

DQS07DQS116DQS225DQS334DQS485DQS594DQS6103DQS7112DQS843

BA071BA1190BA252

SCL118SDA238SA0117SA1237

A0188A1181A2180A4178A7177A9175A10/AP70A1155A12174A13196

CB039CB140CB245CB346CB4158CB5159CB6164CB7165

CK0184CK0#185CK1(NU)63CK1#(NU)64

ODT0195ODT177CKE050CKE1169

CAS#74RAS#192

DM0/DQS9125DM1/DQS10 134DM2/DQS11 143DM3/DQS12 152DM4/DQS13 203DM5/DQS14 212DM6/DQS15 221DM7/DQS16 230DM8/DQS17 161

DQS0#6DQS1#15DQS2#24DQS3#33DQS4#84DQS5#93DQS6#102DQS7#111DQS8#42

NC/DQS9#126NC/DQS10#135NC/DQS11#144NC/DQS12#153NC/DQS13#204NC/DQS14#213NC/DQS15#222NC/DQS16#231NC/DQS17#162

VSS47

VSS89

CS0#193CS1#76

DQS07DQS116DQS225DQS334DQS485DQS594DQS6103DQS7112DQS843

BA071BA1190BA252

SCL118SDA238SA0117SA1237

A0188A1181A2180A4178A7177A9175A10/AP70A1155A12174A13196

CB039CB140CB245CB346CB4158CB5159CB6164CB7165

CK0184CK0#185CK1(NU)63CK1#(NU)64

ODT0195ODT177CKE050CKE1169

CAS#74RAS#192

DM0/DQS9125DM1/DQS10134DM2/DQS11143DM3/DQS12152DM4/DQS13203DM5/DQS14212DM6/DQS15221DM7/DQS16230DM8/DQS17161

DQS0#6DQS1#15DQS2#24DQS3#33DQS4#84DQS5#93DQS6#102DQS7#111DQS8#42

NC/DQS9#126NC/DQS10#135NC/DQS11#144NC/DQS12#153NC/DQS13#204NC/DQS14#213NC/DQS15#222NC/DQS16#231NC/DQS17#162

VSS47

VSS89

C228C0.1u25XC228C0.1u25X

Trang 13

2D writing training switcher

De-coupling Caps For DIMMs

DDR REF POWER & CAPS

R233 10KR0402 R233 10KR0402

Q35 NN-2N7002DW-7-F_SOT363-6-RH Q35

NN-2N7002DW-7-F_SOT363-6-RH

G2 D1 G1

S2 D2

R238 10KR0402 R238 10KR0402

Q38 NN-2N7002DW-7-F_SOT363-6-RH Q38

NN-2N7002DW-7-F_SOT363-6-RH

G2 D1 G1

S2 D2

C246 C10u6.3X5-HF C246 C10u6.3X5-HF

Trang 14

PCI_CLK0

FCH_25M_X1

PCI_CLK_DEBUG PCI_CLK_DEBUG

GPP_TX1NGPP_TX0P

SIO_48M_CLK

LDTSTOP_L_R

AD24AD21

C_BE#3AD29AD26AD23AD20

AD5AD1

AD31AD28

AD13AD10AD8

C_BE#2

AD18AD14

PGNT0#

LOCK#

PARDEVSEL#

UMI_RX0P8UMI_RX0N8UMI_RX1P8UMI_RX1N8UMI_RX2P8UMI_RX2N8UMI_RX3P8UMI_RX3N8

DISP_CLK10DISP_CLK#

10

APU_CLK10APU_CLK#

10PE16_GXF_CLK22PE16_GXF_CLK#

22

SIO_48M_CLK31

PE_LAN_CLK25PE_LAN_CLK#

25

PE1_GPP_CLK023PE1_GPP_CLK0#

23PE1_GPP_CLK123PE1_GPP_CLK1#

23

PCI_CLK0 24

RTC_CLK 18

APU_PWRGD 7,10FCH_DMA_ACTIVE# 10APU_PROCHOT# 10APU_RST# 10

FCH_25M_X118FCH_25M_X218

PCI_CLK_DEBUG31

GPP_RX1P23GPP_RX1N23

GPP_TXC_1N

23GPP_TXC_1P

23GPP_TXC_0N23GPP_TXC_0P23

GPP_RX0P23GPP_RX0N23

LDTSTOP_L10

PGNT0# 24C_BE#[3 0]24AD[31 0]24

DEVSEL# 24FRAME#24IRDY# 24STOP# 24TRDY# 24PERR# 24PAR 24SERR# 24PREQ0# 24

LOCK# 24PCI_INTF#24PCI_INTE#24PCI_INTG# 24

PCIRST# 24

CLKRUN# 31PREQ3# 18

PGNT#3 18

LPC_CLK118,31

Title

Bolton PCIE/PCI/APU/LPC/CLK

CTitle

Bolton PCIE/PCI/APU/LPC/CLK

CTitle

MACH@bios porting to 48M clock output

mach@CRB use 22pF

Layout:

Place close to FCHA_RST# for LPC device;

PCIE_RST# for APU PCIE device;

PCIE_RST#2 FCH PCIE device

For external clock generator mode:

100-MHz reference clock for the FCH Spreadcapable

For internal clock generator mode:

Not used Left unconnected

The function is selected by the pin strap “CLKGEN”

(pin LPCCLK1)

INT

Layout: Place within 1 inch

MACH@???DG:Leave NC if not used;

CRB reserve 49.9R to GND

Layout:Place x'tal within 1.5 inch of FCH

1 - 2

CLEAR CMOS

C304 C0.1u10X0402C304 C0.1u10X0402

C325C22p50N0402C325C22p50N0402

C313 C0.1u10X0402C313 C0.1u10X0402

TP65

C319C0.1u10X0402C319C0.1u10X0402

R219 0R0402R219 0R0402

R214 0R0402R214 0R0402

R231 22R0402R231 22R0402

R227 X_10KR0402R227 X_10KR0402

12

C324C22p50N0402C324C22p50N0402

AD5PCIE_RST#

AE2

VDDBT_RTC_G E6INTRUDER_ALERT#RTCCLK F3F1S5_CORE_ENH732K_X2G432K_X1G2APU_RST#LDT_STP#F26G26APU_PGE26PROCHOT#E28DMA_ACTIVE#G25SERIRQ/GPIO48AE19LDRQ1#/CLK_REQ6#/GPIO49LDRQ0#AE27B27LFRAME#LAD3LAD2LAD1A31A29A26C28LAD0D27LPCCLK1D25LPCCLK0B25INTH#/GPIO35AD18INTG#/GPIO34INTF#/GPIO33INTE#/GPIO32AC16AE18AF18LOCK#AH9CLKRUN#AD19GNT3#/CLK_REQ7#/GPIO46GNT2#/SD_LED/GPO45GNT1#/GPO44GNT0# AK17AD21AD13AD16REQ3#/CLK_REQ5#/GPIO42AM17REQ2#/CLK_REQ8#/GPIO41REQ1#/GPIO40AF15AG13REQ0#AG15SERR#AH8PERR#AM9STOP#PARAH1AE10TRDY#IRDY#AF10AL10DEVSEL#FRAME#CBE3#AK9AG10AD12CBE2#AN10CBE1#AJ8CBE0#AN3AD31/GPIO31AE16AD30/GPIO30AC15AD29/GPIO29AD15AD28/GPIO28AH14AD27/GPIO27AH13AD26/GPIO26AF13AD25/GPIO25AE13AD24/GPIO24AC12AD23/GPIO23AE12AD22/GPIO22AG12AD21/GPIO21AN12AD20/GPIO20AK11AD19/GPIO19AL12AD18/GPIO18AJ10AD17/GPIO17AM11AD16/GPIO16AG9AD15/GPIO15AN8AD14/GPIO14AK7AD13/GPIO13AJ6AD12/GPIO12AM7AD11/GPIO11AL3AD10/GPIO10AD9/GPIO9AD8/GPIO8AD7/GPIO7 AL8AJ1AN6AN5AD6/GPIO6 AL1AD5/GPIO5 AJ5AD4/GPIO4 AH3AD3/GPIO3 AL6AD2/GPIO2 AG4AD1/GPIO1 AL5AD0/GPIO0 AJ3PCIRST# AB5PCICLK4/14M_OSC/GPO39PCICLK3/GPO38AF6

AG2PCICLK2/GPO37AF5PCICLK1/GPO36PCICLK0AF1AF3 R235R235 22R040222R0402

TP58

C308 C0.1u10X0402C308 C0.1u10X0402

R229 X_0R0402R229 X_0R0402

C315 C0.1u10X0402C315 C0.1u10X0402

C309 C0.1u10X0402C309 C0.1u10X0402

C326C0.1u25XC326C0.1u25X

C311 C0.1u10X0402C311 C0.1u10X0402

R223 0R0402R223 0R0402

R226X_0R0402R226X_0R0402

R220 0R0402R220 0R0402

R237 22R0402R237 22R0402

R206 22R0402R206 22R0402

R241 22R0402R241 22R0402

C310 C0.1u10X0402C310 C0.1u10X0402

R222 0R0402R222 0R0402

C306 C18p50N0402

R213 0R0402R213 0R0402

R225 0R0402R225 0R0402

C318C0.1u10X0402C318C0.1u10X0402

C314 C0.1u10X0402C314 C0.1u10X0402

R228 0R0402R228 0R0402

R209 590R1%0402

R2321MRR2321MR

R230 0R0402R230 0R0402

R215 0R0402R215 0R0402

R218 0R0402R218 0R0402

C317C0.1u10X0402C317C0.1u10X0402R210 2KR1%0402

R210 2KR1%0402

R216 0R0402R216 0R0402R217 0R0402R217 0R0402C320C0.1u10X0402C320C0.1u10X0402

Trang 15

AZ_SYNC_R

AZ_RST_RAZ_BITCLK_RAZ_SDATA_OUT_RAZ_SYNC_R

AZ_SDIN

14M_25M_48M_OSCUSB_RCOMP

WD_PWRGD

FCH_PWRGD

FCH_PWRGDFCH_WAKE#

WD_PWRGD

AZ_SDIN

USBSS_CALRP

SCLK3SDATA3

FCH_GPO200

FCH_GPO193

FCH_GPI197

FCH_GPO193FCH_GPI197FCH_GPO200FCH_GPO_CTRL

FCH_GPO194

USB_SS_TX3P_CUSB_SS_TX3N_P

USB_SS_TX2P_CUSB_SS_TX2P_P

USB_SS_TX2N_C

USB_SS_TX1N_P USB_SS_TX1N_CUSB_SS_TX1P_P

USB_SS_TX0P_CUSB_SS_TX0P_P

USB_SS_TX0N_C

ILIM_SEL_1CTL1_1ILIM_SEL_2CTL1_2

CTL2_1ILIM_SEL_2CTL1_1ILIM_SEL_1

CTL2_2

SCLK3SDATA3

VCC3_SB

VCC3_SB VCC3_SBVCC3_SB

VCC3_SB

SPKR34SCLK012SDATA012SCLK122,23,24,25SDATA122,23,24,25

OC#118,28 OC#218,28OC#318,29

23,29,31,32,33

N_RI31

PSOUT#

31

A20GATE31KBRST#

31

FCH_PWRGD31,33

SPI_HOLD#_R16

AZ_SDIN26

USB0+ 27USB0- 27

USB1+ 27USB1- 27

USB2+ 27USB2- 27

USB3+ 27USB3- 27

USB4+ 27USB4- 27

USB5+ 27USB5- 27

FCH_GPIO199 18

USB11+ 28USB11- 28USB10+ 28USB10- 28

FCH_TEST018FCH_TEST118FCH_TEST218

OC#018,29

USB13+ 28USB13- 28USB12+ 28USB12- 28

USB_SS_RX0N_C 28USB_SS_RX1N_C 28USB_SS_RX2N_C 28USB_SS_RX3N_C 28

FCH_IDLEEXIT_L10

CHASSIS_ID231CHASSIS_ID131MB_ID131MB_ID031

USB6+ 27USB6- 27

19

PCIE_RST2# 23

USB9- 27USB9+ 27

USB8- 27USB8+ 27

USB7- 27USB7+ 27

OC#4

29 OC#529

DEPOP_GPIO26

Bolton ACPI/USB/AZ/GPIO

CTitle

C

S5 POWER DOMAINS0 POWER DOMAIN

ROUTE TO DIMMs,SIO

ROUTE TO LAN,PCIE,Mini_PCIE

mach@verify the ports being used

Layout: Place close to FCH

Layout: Place within 1'' of FCH

Wake On Modem Header

HighNormal -12V+12VActive Low

Layout:Place close to FCH ASAP

10-kΩ 5% pull-up resistor to+3.3V_S5

Inte-grated PU

USB Overcurrent Implemented:

Connect to overcurrent signal from USB connector (note that these are

3.3-V swing (i.e not 5-V) and use low-pass filter to prevent glitches during

plug/unplug events

If USB ports are not powered in S4/S5 states and the FCH’s internal pullups

are enabled, provide a diode between the FCH and overcurrent circuit

(cathode towards the FCH) to prevent leakage from the FCH internal pullups

in S4/S5 states

INT 10k PU

USB13 FRONT USB3.0 USB11 REAR USB3.0 USB9 REAR USB2.0 USB7 FRONT USB2.0(RESERVE) USB5 FRONT USB2.0(RESERVE) USB3 CARDREADER USB1 LAN USB2.0 mach@Rerouting the USB pairs follow layout

FOR GPIO[226:209]

KBC Not Implemented:

Use for alternate available function

or leave not connected

HUDSON ACPI/USB/AZ/GPIO

Rise time ≤ 50-ms +3.3V_S5 voltage rails ramp up at least 10-ms before RSMRST# is deasserted

Mode PostionCOOLTURORRESERVED

GP0/GP10/0

1/1Note:Must can trap SMI/SCI

C331X_C1000p50X0402

C333C0.1u10X0402C333C0.1u10X0402

R339 0R0402R339 0R0402

TP34

C340C0.1u10X0402C340C0.1u10X0402

R88010KR0402 R88010KR0402

R2490R0402R2490R0402

R273 10KR0402R273 10KR0402

R267 0R0402R267 0R0402

R341X_10KR0402R341X_10KR0402

TP33C33815p50N0402

C332C0.1u10X0402C332C0.1u10X0402

C339C0.1u10X0402C339C0.1u10X0402

R248 15R0402R248 15R0402

R57910KR0402 R57910KR0402TP56

R27110KR0402 R27110KR0402

AZ_RST#

AE4 AZ_SYNCAD6Y1AZ_SDIN3/GPIO170AZ_SDIN2/GPIO169Y3AZ_SDIN1/GPIO168Y5AZ_SDIN0/GPIO167AA2 AZ_SDOUTAB1 AZ_BITCLKAB3USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#

AF25 GBE_STAT0/GEVENT11#

AA8V10Y6GBE_LED2/GEVENT10#SPI_HOLD#/GBE_LED1/GEVENT9#GBE_LED0/GPIO183W8V8DDR3_RST#/GEVENT7#/VGA_PDSMARTVOLT2/SHUTDOWN#/GPIO51AG26IR_LED#/LLB#/GPIO184J2CLK_REQ1#/FANOUT4/GPIO61AG22CLK_REQ2#/FANIN4/GPIO62AG25SDA1/GPIO228R7SCL1/GPIO227T7SDA0/GPIO47AD25SCL0/GPIO43AD26SPKR/GPIO66AF24 SATA_IS5#/FANIN3/GPIO59AG18SATA_IS4#/FANOUT3/GPIO55AH17CLK_REQ0#/SATA_IS3#/GPIO60AF22 SMARTVOLT1/SATA_IS2#/GPIO50AE26 CLK_REQ3#/SATA_IS1#/GPIO63AE24 CLK_REQ4#/SATA_IS0#/GPIO64AG24

RSMRST#

U2WD_PWRGDAF19R10THRMTRIP#/SMBALERT#/GEVENT2#IR_RX1/GEVENT20#

E22SDA3_LV/GPIO196SCL3_LV/GPIO195SDA2/GPIO194 G21G22G19SCL2/GPIO193H19USB_SS_RX0NK15USB_SS_RX0PJ15USB_SS_TX0N H16USB_SS_TX0P J16USB_SS_RX1NG13USB_SS_RX1PH13USB_SS_TX1N G15USB_SS_TX1P F15USB_SS_RX2NF14USB_SS_RX2PE14USB_SS_TX2N B15USB_SS_TX2P D15USB_SS_RX3NA12USB_SS_RX3PC12USB_SS_TX3N C14USB_SS_TX3P A14USBSS_CALRN A16USBSS_CALRP C16USB_HSD0N E3USB_HSD0P E1USB_HSD1N C3USB_HSD1P C1USB_HSD2N A5USB_HSD2P C5USB_HSD3N A6USB_HSD3P C6USB_HSD4N E8USB_HSD4P F8USB_HSD5N C8USB_HSD5P A8USB_HSD6N G9USB_HSD6P H9USB_HSD7N A10USB_HSD7P C10USB_HSD8N F10USB_HSD8P E10USB_HSD9N D11USB_HSD9P B11USB_HSD10N K13USB_HSD10P K12USB_HSD11N F12USB_HSD11P G12USB_HSD12N J12USB_HSD12P K10USB_HSD13N G10USB_HSD13P H10USB_FSD0NH5USB_FSD0P/GPIO185H6USB_FSD1NH3USB_FSD1P/GPIO186H1USB_RCOMPB9USBCLK/14M_25M_48M_OSCG8

R87710KR0402 R87710KR0402

R26610KR0402 R26610KR0402

R639 10KR0402

R258 1KR1%0402R258 1KR1%0402

R252 2.2KR0402

R31310KR0402 R31310KR0402

R342 X_0R0402R342 X_0R0402

R250 0R0402R250 0R0402

R205 33R0402R205 33R0402

R27410KR0402R27410KR0402

C336C0.1u10X0402C336C0.1u10X0402R261 33R0402

R261 33R0402

R247 15R0402R247 15R0402

R246 11.8KR1%0402R246 11.8KR1%0402

R26810KR0402 R26810KR0402

C337C0.1u10X0402C337C0.1u10X0402

R26910KR0402 R26910KR0402

C341X_C1000p50X0402C341X_C1000p50X0402

R260 33R0402

R73710KR0402R73710KR0402

R636 10KR0402

R27010KR0402 R27010KR0402

R635 10KR0402

R87910KR0402 R87910KR0402

R244 0R0402R244 0R0402

R900X_10KR0402R900X_10KR0402

C335C0.1u10X0402C335C0.1u10X0402

R340 X_0R0402R340 X_0R0402

R638 10KR0402

R57810KR0402 R57810KR0402

R27210KR0402 R27210KR0402

C342X_C1u16X5C342X_C1u16X5

R256 10KR0402

R257 1KR1%0402R257 1KR1%0402

R343 0R0402R343 0R0402

R243 300R0402

R640 10KR0402

Trang 16

SATA_TX1+

SATA_RX0-SATA_TX0-

SPI_DATAIN

SPI_HOLD#

SPI_CLKSPI_DATAIN

SPI_CS#

SPI_HOLD#

FCH_TALERT#

GBE_CRSGBE_COL

GBE_RXERRGBE_MDIO

GBE_PHY_INTR

FCH_SATA_X2FCH_SATA_X1SATA_LED#

SATA_CALRP

SPI_CLKSPI_DATAOUTSPI_CLK_R

SPI_DATAOUT_RSPI_DATAINSPI_CS#_RSPI_WP#_R

ML_VGA_HPDDAC_RSETHUDSON_VGA_R

AUXCAL

HUDSON_VGA_G

HUDSON_VGA_SDATHUDSON_VGA_SCLK

SPI_WP#

SPI_CS#

SPI_DATAIN_R SPI_HOLD#

SPI_DATAOUTSPI_CLK

GPIO171

GPIO175GPIO178GPIO181

SATA_RX3+

SATA_RX3-SATA_TX3+

SATA_TX3-GPIO173GPIO175GPIO176

GPIO180GPIO181

GPIO179GPIO182

BIOS_WP#

HUDSON_VGA_SDATHUDSON_VGA_SCLK

FCH_VDD11_RUN

VCC_DDRVCC3

VCC3_ROM

VCC3VCC3_ROM

VCC5

VCC3_ROM

30SATA_RX0+

SATA_RX0-30

30SATA_RX1+

SATA_RX1-30

30SATA_RX2+

SATA_RX2-30

SATA_TX0+

30SATA_TX0-30

SATA_TX1+

30SATA_TX1-30

SATA_TX2+

30SATA_TX2-30

SPI_HOLD#_R 15

FANOUT018

HUDSON_VGA_VSYNC21HUDSON_VGA_HSYNC21

HUDSON_VGA_R21HUDSON_VGA_G21HUDSON_VGA_B21

HUDSON_VGA_SCLK21HUDSON_VGA_SDAT21

DP0_HPD_VGA_C 10

DP0_AUXP_C 10DP0_AUXN_C 10

FCH_GPIO7331

30SATA_RX3+

SATA_RX3-30SATA_TX3+

30SATA_TX3-30

GPIO_WP#

15

GPIO17115

Title

Bolton SATA/VGA/HWM/SPI

CTitle

C

SATA[3::0]Route to iSATAGEN III 6.0 Gbit/S

LAYOUT:

ROUTE SATA TX DIFF PAIR @ 100 OHM+/-10%

RX DIFF PAIR @ 90 OHM+/-10%

SPI ROM & DEBUG HEADER

MACH@Reserve 0R serial resisters for

SI overshoot/undershoot debug

External Clock Generator Mode:

Connect to 25.000-MHz XTAL or connect SATA_X1/X2 balls to

100MHz differential clock from external clock generator

Integrated Clock Mode:

10-kΩ 5% pull-up resistor to+3.3V_S5

10-kΩ 5% pull-down resistor

VGA HPD 32M

R285 150R1%0402R285 150R1%0402

R284 X_0R0402R284 X_0R0402

C350C5p50N0402

+

EC21+ CD10u16EL5EC211 2CD10u16EL5

R292X_10KR0402R292X_10KR0402

BIOS_WP_X2

JUMP1X2A_RED-RHBIOS_WP_X2

JUMP1X2A_RED-RH

R669X_0R0402 R669X_0R0402

Q40X_N-SST3904_SOT23Q40X_N-SST3904_SOT23

B

R297 X_100KR0402R297 X_100KR0402

R295100KR0402R295100KR0402

R275 10KR0402R275 10KR0402

R296 X_100KR0402R296 X_100KR0402

R279 0R0402R279 0R0402

R291 100R1%0402

U33SPI FLASH-8P_BLACK-RHU33SPI FLASH-8P_BLACK-RH

CS1DO2WP3GND

4 CLKDI56HLODVCC78

R290 715R1%0402R290 715R1%0402

RN25 8P4R-10KR0402RN25 8P4R-10KR0402

1

72

8

R289 931R1%0402R289 931R1%0402

R27710KR0402R27710KR0402

TP59

R294 0R0402R294 0R0402R293 X_10KR0402R293 X_10KR0402

R27810KR0402R27810KR0402

C348C5p50N0402

TP62

R288 1KR1%0402R288 1KR1%0402

R286 150R1%0402R286 150R1%0402

C346C0.1u10X0402C346C0.1u10X0402

BIOS_WP1

H1X3M_RED-RHBIOS_WP1

1

72

8

R642 X_0R0402R642 X_0R0402

TP37

C344 C0.1u16X50402-2C344 C0.1u16X50402-2

R282 0R0402R282 0R0402

U6

W25Q32FVSSIQ-RH

U6

W25Q32FVSSIQ-RHCS1DO(IO1)2WP(IO2)3GND4VCC8HOLD(IO3)7CLK6DI(IO0)5

R287 150R1%0402R287 150R1%0402

SATA_X2AG21

SATA_X1AF21SATA_ACT#/GPIO67AD22SATA_CALRNAF27SATA_CALRPAF28NC13AJ31NC12AJ33NC11AH31NC10AH33NC9AL33NC8AL31NC7AN31AL29NC6SATA_RX5PAM27SATA_RX5NAK27SATA_TX5NAL28SATA_TX5PAN29SATA_RX4PAH26AJ26SATA_RX4NSATA_TX4NAN26AL26SATA_TX4PSATA_RX3PAL24SATA_RX3NAN24SATA_TX3NAJ24SATA_TX3PAH24SATA_RX2PAK23 SATA_RX2NAM23SATA_TX2NAH22SATA_TX2PAJ22SATA_RX1PAJ20SATA_RX1NAH20SATA_TX1NAL22SATA_TX1PAN22SATA_RX0PAN20SATA_RX0NAL20SATA_TX0NAM19SATA_TX0PAK19

NC5L4NC4G27NC3A28NC2AH10NC1AG16VIN7/GBE_LED3/GPIO182 M5VIN6/GBE_STAT3/GPIO181VIN4/SLOAD_1/GPIO179VIN3/SDATO_1/GPIO178VIN5/SCLK_1/GPIO180 M1P3P1N4VIN2/SDATI_1/GPIO177VIN1/GPIO176VIN0/GPIO175 L2M3N2ML_VGA_HPD/GPIO229 C29ML_VGA_L3NML_VGA_L3PP28P29ML_VGA_L2NML_VGA_L2PR30R32ML_VGA_L1NML_VGA_L1PT28T29ML_VGA_L0NML_VGA_L0PT33T31AUXCAL U28AUX_VGA_CH_N V29AUX_VGA_CH_P V28VGA_DAC_RSET K31VGA_DDC_SCL/GPO71 N32VGA_DDC_SDA/GPO70 M33VGA_VSYNC/GPO69N30VGA_HSYNC/GPO68 M28VGA_BLUE M29VGA_GREEN L32VGA_REDL30ROM_RST#/SPI_WP#/GPIO161SPI_CS1#/GPIO165 V1

T6SPI_CLK/GPIO162SPI_DO/GPIO163SPI_DI/GPIO164 V3V5V6GBE_PHY_INTR W9GBE_PHY_RST#GBE_PHY_PD AA7AC2GBE_TXCTL/TXENGBE_TXD0GBE_TXD1GBE_TXD2 AB9AD8AE8AG6GBE_TXD3 AF9GBE_TXCLK AB7GBE_RXERR AD1GBE_RXCTL/RXDVGBE_RXD0GBE_RXD1GBE_RXD2AG8AD7AE7AF7GBE_RXD3AH7GBE_RXCLKGBE_MDIO AB8W10GBE_MDCKGBE_CRSGBE_COL AD9AD3AC4SD_DATA3/GPIO80 AJ14SD_DATA2/GPIO79 AH15SD_DATA1/SDATO_0/GPIO78SD_DATA0/SDATI_0/GPIO77SD_WP/GPIO76 AM13AK13

AH12SD_CD#/GPIO75 AJ12SD_CMD/SLOAD_0/GPIO74SD_CLK/SCLK_0/GPIO73AN14

AL14

R280 0R0402R280 0R0402

R643 0R0402R643 0R0402

R8240R0402 R8240R0402

R281 0R0402R281 0R0402

R404 4.7KR0402R404 4.7KR0402TP36

D4

B140-13-F_SMA-RH

D4

B140-13-F_SMA-RH

Trang 17

VDDPL_1.1V

+1.1VDUAL VDDCR_1.1VVCC3_SB

VDDCR_1.1VVDDXL_3.3V+3.3VALW_RFCH_VDD11_RUN

Bolton POWER/GND

CTitle

C

LAYOUT:

ROUTE THE POWER TRACES 15MILS WIDTH AT LEAST

PLACE THE DECOUPING CAPS CLOSE TO FCH ASAP

PLACE FB<=1" ,CAPS <=0.2"

mach@Internally generated 1.8V supply

for the RGB outputs???

Layout:

VSSPL_SYS;VSSAN_HWM CONNECT TO GND WITH A SEPREATED VIA

mach@???if VGA translater is not used,

power rails tied to GND

It is recommended that each power supply or regulator

on the motherboard be located within 3.0" of its respective

To calculate the minimum power delivery trace width, use the formula: Vdroop = I*R, where R=ρ*L/A (ρ = resistivity of Vdroop must be < 2.5% of the nominal power rail voltage under maximum current conditions

For low current PLL, analog and IO power rails, a minimumabove shows that a thinner trace is acceptable The 15 mil minimum trace width is required to minimize noise coupling;

if necessary, thinner trace can be used but not for more than 300 mils of trace length

26 mA

VDDPL_33_DAC VDDPL_33_ML 12 mA

VDDIO_33_GBE_S

12 mA

VDDPL_33_USB_S VDDAN_33_USB_S_[12:1]

VDDCR_11_S_[2:1]

VDDCR_11_GBE_S[2:1] 63 mA

VDDPL_11_SYS_S VDDAN_11_USB_S_[2:1]

VDDPL_33_SSUSB_S

VDDAN_11_SSUSB_S_[5:1]

VDDPL_11_SYS_S should be tied

to +1.1V_S5 rail if Wake on LAN

or USB 3.0 Wake (Hudson-D3only) is supported; otherwise, it can

L12 220L200mA-300-RH

R300 0R0805R300 0R0805

L6220L2A-50L6220L2A-50

VDDIO_GBE_S_2AA10 VDDIO_GBE_S_1AA9VDDCR_11_GBE_S_2AA11 VDDCR_11_GBE_S_1AB11VDDIO_33_GBE_SAB10VDDAN_11_ML_4V25VDDAN_11_ML_3V24VDDAN_11_ML_2V23VDDAN_11_ML_1Y22VDDPL_11_DACV21LDO_CAPM31VDDPL_33_SATAAG28VDDPL_33_PCIEAH29L18D7VDDPL_33_USB_SVDDPL_33_SSUSB_SVDDAN_33_DACT22VDDPL_33_MLU22VDDPL_33_DACV22VDDPL_33_SYSH24VDDIO_33_PCIGP_10AB16 VDDIO_33_PCIGP_9AB14 VDDIO_33_PCIGP_8AB13 VDDIO_33_PCIGP_7AB12 VDDIO_33_PCIGP_6AC13VDDIO_33_PCIGP_5AG7VDDIO_33_PCIGP_4AD10AE9 VDDIO_33_PCIGP_3VDDIO_33_PCIGP_2AB18 VDDIO_33_PCIGP_1AB17

VDDIO_AZ_S AA4VDDAN_33_HWM_SM8VDDPL_11_SYS_S J24VDDCR_11_S_2 M20VDDCR_11_S_1 N20VDDXL_33_S G24VDDIO_33_S_8W11VDDIO_33_S_7Y13VDDIO_33_S_6Y12VDDIO_33_S_5V13VDDIO_33_S_4V12VDDIO_33_S_3M18VDDIO_33_S_2L19VDDIO_33_S_1N18

VDDAN_11_SATA_10VDDAN_11_SATA_9AC19AB20VDDAN_11_SATA_8AA18VDDAN_11_SATA_7AA20VDDAN_11_SATA_6AC21VDDAN_11_SATA_5AC22VDDAN_11_SATA_3AB22VDDAN_11_SATA_2AB21VDDAN_11_SATA_4Y20VDDAN_11_SATA_1AA21VDDAN_11_PCIE_8AG27VDDAN_11_PCIE_7AF26VDDAN_11_PCIE_6AA22VDDAN_11_PCIE_5AB23VDDAN_11_PCIE_4AD24VDDAN_11_PCIE_3AE25VDDAN_11_PCIE_2Y21VDDAN_11_PCIE_1AB24VDDAN_11_CLK_8 P22VDDAN_11_CLK_7 N22VDDAN_11_CLK_6 N21VDDAN_11_CLK_5 M22VDDAN_11_CLK_4 L22VDDAN_11_CLK_3 K24VDDAN_11_CLK_2 J25VDDAN_11_CLK_1 H26VDDCR_11_9Y17VDDCR_11_8V20VDDCR_11_7V17VDDCR_11_6V14VDDCR_11_5U18VDDCR_11_4U16VDDCR_11_3T20VDDCR_11_2T17VDDCR_11_1T14

R302 0RR302 0R

EFUSER6VSSIO_DACN28VSSANQ_DACVSSAN_DACVSSPL_DACK33L28T21VSS_128 AN33VSS_127 AN28VSS_126 AN18VSS_125 AN1VSS_124 AM25VSS_123 AM21VSS_122 AL18VSS_121 AK25VSS_120 AK21VSS_119 AJ29VSS_118 AJ28VSS_117 AJ18VSS_116 AH27VSS_115 AH25VSS_114 AH23VSS_113 AH21VSS_112 AH19VSS_111 AH18VSS_110 AH11VSS_109 AH5VSS_108 AG32VSS_107 AG30VSS_106 AF33VSS_105 AF16VSS_104 AF12VSS_103 AF8VSS_102 AE28VSS_101 AE21VSS_100VSS_99AE15AE6VSS_98AD27VSS_97AC28VSS_96AC18VSS_95AC6VSS_94AB25VSS_93AA32VSS_92AA30VSS_91AA28VSS_90AA25VSS_89AA17VSS_88AA16VSS_87AA14VSS_86AA13VSS_85AA12VSS_84AA6VSS_83Y18VSS_82Y16VSS_81Y14VSS_80W28VSS_79W25VSS_78W6VSS_77W4VSS_76V18VSS_75V16VSS_74V11VSS_73U32VSS_72U30VSS_71U21VSS_70U20VSS_69U17VSS_68U14VSS_67U6VSS_66T27VSS_65T25

Trang 18

OC#2

VCC3_SB VCC3_SB VCC3

VCC3_SB

VCC3_SB VCC3 VCC3_ALW

PCI_CLK1 14,31 RTC_CLK 14

LPC_CLK0 14,31 FCH_GPIO199 15

FANOUT0 16

FCH_25M_X1 14

FCH_TEST0 15 FCH_TEST2 15

FCH_TEST1 15

OC#0 15,29 OC#1 15,28 OC#2 15,28 OC#3 15,29

PCI_CLK3 14

PREQ3# 14 PGNT#3 14

PCI_CLK4 14,24 LPC_CLK1 14,31

FCH REQUIRED STRAPS

PCI_CLK1

S5 PLUS MODE DISABLED

ALLOW PCIE GEN2

FORCE PCIE GEN1

USE DEBUG STRAPS

IGNORE DEBUG STRAPS Required setting for intergrated CLOCk MODE

PULL LOW

PULL HIGH

DEFAULT

LPC_CLK1

INTERNAL CLOCK GEN DISABLED

DEFAULT

INTERNAL CLOCK GEN ENABLED

FCH XOR CHAIN TEST

SHORTING PLUG

TEST1 TEST0 TEST2

0 1 X Enable test mode

Description FCH XOR CHAIN REF CLOCK

R881 10KR0402 R881 10KR0402

R307 10KR0402 R307 10KR0402

R312 X_10KR0402 R312 X_10KR0402

R311 X_2.2KR0402 R311 X_2.2KR0402

TP47

TP43

R882 10KR0402 R882 10KR0402

TP46

R314 10KR0402 R314 10KR0402

TP44

R624 10KR0402 R624 10KR0402

TP40

R308 X_10KR0402 R308 X_10KR0402

Tiêu đề	MSI MS 7928 Rev 1.1 Schematic
Trường học	Micro-start Int'l Co., Ltd.
Thể loại	technical document
Năm xuất bản	2014

Định dạng
Số trang	36
Dung lượng	805,38 KB