Tài liệu Timing and Delay part 3 doc

10.3.1 $setup and $hold Checks $setup and $hold tasks are used to check the setup and hold constraints for a sequential element in the design.. $setup task Setup checks can be specified

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10.3 Timing Checks

In the earlier sections of this chapter, we discussed how to specify path

delays The purpose of specifying path delays is to simulate the timing of the actual digital circuit with greater accuracy than gate delays In this section,

we describe how to set up timing checks to see if any timing constraints are violated during simulation Timing verification is particularly important for timing critical, high-speed sequential circuits such as microprocessors

System tasks are provided to do timing checks in Verilog There are many timing check system tasks available in Verilog We will discuss the three most common timing checks[1] tasks: $setup, $hold, and $width All timing checks must be inside the specify blocks only Optional notifier arguments used in these timing check system tasks are omitted to simplify the

discussion

[1]

The IEEE Standard Verilog Hardware Description Language document provides additional constraint checks, $removal, $recrem, $timeskew,

$fullskew Please refer to it for details Negative input timing constraints can also be specified

10.3.1 $setup and $hold Checks

$setup and $hold tasks are used to check the setup and hold constraints for a sequential element in the design In a sequential element such as an edge-triggered flip-flop, the setup time is the minimum time the data must arrive before the active clock edge The hold time is the minimum time the data cannot change after the active clock edge Setup and hold times are shown in

Figure 10-6

Figure 10-6 Setup and Hold Times

$setup task

Setup checks can be specified with the system task $setup

Usage: $setup(data_event, reference_event, limit);

reference_event Signal that establishes a reference for monitoring

the data_event signal

Violation is reported if (Treference event - Tdata event) < limit

An example of a setup check is shown below

//Setup check is set

//clock is the reference

//data is being checked for violations

//Violation reported if Tposedge_clk - Tdata < 3

specify

$setup(data, posedge clock, 3);

endspecify

$hold task

Hold checks can be specified with the system task $hold

Usage: $hold (reference_event, data_event, limit);

reference_event Signal that establishes a reference for monitoring

the data_event signal

data_event Signal that is monitored for violation

Violation is reported if ( Tdata event - Treference event ) < limit

An example of a hold check is shown below

//Hold check is set

//clock is the reference

//data is being checked for violations

//Violation reported if Tdata - Tposedge_clk < 5

specify

$hold(posedge clear, data, 5);

endspecify

10.3.2 $width Check

Sometimes it is necessary to check the width of a pulse

The system task $width is used to check that the width of a pulse meets the minimum width requirement

Usage: $width(reference_event, limit);

The data_event is not specified explicitly for $width but is derived as the next opposite edge of the reference_event signal Thus, the $width task checks the time between the transition of a signal value to the next opposite transition in

the signal value

Violation is reported if ( Tdata_event - Treference_event ) < limit

//width check is set

//posedge of clear is the reference_event

//the next negedge of clear is the data_event

//Violation reported if Tdata - Tclk < 6

specify

$width(posedge clock, 6);

endspecify

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10.4 Delay Back-Annotation

Delay back-annotation is an important and vast topic in timing simulation

An entire book could be devoted to that subject However, in this section, we introduce the designer to the concept of back-annotation of delays in a

simulation Detailed coverage of this topic is outside the scope of this book For details, refer to the IEEE Standard Verilog Hardware Description

Language document

The various steps in the flow that use delay back-annotation are as follows:

1 The designer writes the RTL description and then performs functional simulation

2 The RTL description is converted to a gate-level netlist by a logic

synthesis tool

3 The designer obtains pre-layout estimates of delays in the chip by using

a delay calculator and information about the IC fabrication process Then, the designer does timing simulation or static timing verification

of the gate-level netlist, using these preliminary values to check that the gate-level netlist meets timing constraints

4 The gate-level netlist is then converted to layout by a place and route tool The post-layout delay values are computed from the resistance (R) and capacitance (C) information in the layout The R and C information

is extracted from factors such as geometry and IC fabrication process

5 The post-layout delay values are back-annotated to modify the delay estimates for the gate-level netlist Timing simulation or static timing verification is run again on the gate-level netlist to check if timing constraints are still satisfied

6 If design changes are required to meet the timing constraints, the

designer has to go back to the RTL level, optimize the design for

timing, and then repeat Step 2 through Step 5

Figure 10-7 shows the flow of delay back annotation

Figure 10-7 Delay Back-Annotation

A standard format called the Standard Delay Format (SDF) is popularly used for back-annotation Details of delay back-annotation are outside the scope of this book and can be obtained from the IEEE Standard Verilog Hardware Description Language document

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