Tài liệu Behaviotal Modeling part 6 ppt

[ Team LiB ]7.8 Generate Blocks Generate statements allow Verilog code to be generated dynamically at elaboration time before the simulation begins.. Generated instantiations can be one

[ Team LiB ]

7.8 Generate Blocks

Generate statements allow Verilog code to be generated dynamically at elaboration time before the simulation begins This facilitates the creation of parametrized models

Generate statements are particularly convenient when the same operation or module instance is repeated for multiple bits of a vector, or when certain Verilog code is

conditionally included based on parameter definitions

Generate statements allow control over the declaration of variables, functions, and tasks,

as well as control over instantiations All generate instantiations are coded with a module scope and require the keywords generate - endgenerate

Generated instantiations can be one or more of the following types:

• Modules

• User defined primitives

• Verilog gate primitives

• Continuous assignments

• initial and always blocks

Generated declarations and instantiations can be conditionally instantiated into a design Generated variable declarations and instantiations can be multiply instantiated into a design Generated instances have unique identifier names and can be referenced

hierarchically To support interconnection between structural elements and/or procedural blocks, generate statements permit the following Verilog data types to be declared within the generate scope:

• net, reg

• integer, real, time, realtime

• event

Generated data types have unique identifier names and can be referenced hierarchically Parameter redefinition using ordered or named assignment or a defparam statement can

be declared with the generate scope However, a defparam statement within a generate scope is allowed to modify the value of a parameter only in the same generate scope or within the hierarchy instantiated within the generate scope

Task and function declarations are permitted within the generate scope but not within a generate loop Generated tasks and functions have unique identifier names and can be

referenced hierarchically

Some module declarations and module items are not permitted in a generate statement They include:

• parameters, local parameters

• input, output, inout declarations

• specify blocks

Connections to generated module instances are handled in the same way as with normal module instances

There are three methods to create generate statements:

• Generate loop

• Generate conditional

• Generate case

The following sections explain these methods in detail:

7.8.1 Generate Loop

A generate loop permits one or more of the following to be instantiated multiple times using a for loop:

• Variable declarations

• Modules

• User defined primitives, Gate primitives

• Continuous assignments

• initial and always blocks

Example 7-31 shows a simple example of how to generate a bit-wise xor of two N-bit buses Note that this implementation can be done in a simpler fashion by using vector nets instead of bits However, we choose this example to illustrate the use of generate loop

Example 7-31 Bit-wise Xor of Two N-bit Buses

// This module generates a bit-wise xor of two N-bit buses

module bitwise_xor (out, i0, i1);

// Parameter Declaration This can be redefined

parameter N = 32; // 32-bit bus by default

// Port declarations

output [N-1:0] out;

input [N-1:0] i0, i1;

// Declare a temporary loop variable This variable is used only

// in the evaluation of generate blocks This variable does not

// exist during the simulation of a Verilog design

genvar j;

//Generate the bit-wise Xor with a single loop

generate for (j=0; j<N; j=j+1) begin: xor_loop

xor g1 (out[j], i0[j], i1[j]);

end //end of the for loop inside the generate block

endgenerate //end of the generate block

// As an alternate style,

// the xor gates could be replaced by always blocks

// reg [N-1:0] out;

//generate for (j=0; j<N; j=j+1) begin: bit

// always @(i0[j] or i1[j]) out[j] = i0[j] ^ i1[j];

//end

//endgenerate

endmodule

Some interesting observations for Example 7-31 are listed below

• Prior to the beginning of the simulation, the simulator elaborates (unrolls) the code

in the generate blocks to create a flat representation without the generate blocks The unrolled code is then simulated Thus, generate blocks are simply a

convenient way of replacing multiple repetitive Verilog statements with a single statement inside a loop

• genvar is a keyword used to declare variables that are used only in the evaluation

of generate block Genvars do not exist during simulation of the design

• The value of a genvar can be defined only by a generate loop

• Generate loops can be nested However, two generate loops using the same genvar

as an index variable cannot be nested

• The name xor_loop assigned to the generate loop is used for hierarchical name

referencing of the variables inside the generate loop Therefore, the relative

hierarchical names of the xor gates will be xor_loop[0].g1, xor_loop[1].g1, , xor_loop[31].g1

Generate loops are fairly flexible Various Verilog constructs can be used inside the generate loops It is important to imagine, the Verilog description after the generate loop

is unrolled That gives a clearer picture of the behavior of generate loops Example 7-32 shows a generated ripple adder with the net declaration inside the generate loop

Example 7-32 Generated Ripple Adder

// This module generates a gate level ripple adder

module ripple_adder(co, sum, a0, a1, ci);

// Parameter Declaration This can be redefined

parameter N = 4; // 4-bit bus by default

// Port declarations

output [N-1:0] sum;

output co;

input [N-1:0] a0, a1;

input ci;

//Local wire declaration

wire [N-1:0] carry;

//Assign 0th bit of carry equal to carry input

assign carry[0] = ci;

// Declare a temporary loop variable This variable is used only

// in the evaluation of generate blocks This variable does not

// exist during the simulation of a Verilog design because the

// generate loops are unrolled before simulation

genvar i;

//Generate the bit-wise Xor with a single loop

generate for (i=0; i<N; i=i+1) begin: r_loop

wire t1, t2, t3;

xor g1 (t1, a0[i], a1[i]);

xor g2 (sum[i], t1, carry[i]);

and g3 (t2, a0[i], a1[i]);

and g4 (t3, t1, carry[i]);

or g5 (carry[i+1], t2, t3);

end //end of the for loop inside the generate block

endgenerate //end of the generate block

// For the above generate loop, the following relative hierarchical

// instance names are generated

// xor : r_loop[0].g1, r_loop[1].g1, r_loop[2].g1, r_loop[3].g1

r_loop[0].g2, r_loop[1].g2, r_loop[2].g2, r_loop[3].g2

// and : r_loop[0].g3, r_loop[1].g3, r_loop[2].g3, r_loop[3].g3

r_loop[0].g4, r_loop[1].g4, r_loop[2].g4, r_loop[3].g4

// or : r_loop[0].g5, r_loop[1].g5, r_loop[2].g5, r_loop[3].g5

// Generated instances are connected with the following

// generated nets

// Nets: r_loop[0].t1, r_loop[0].t2, r_loop[0].t3

// r_loop[1].t1, r_loop[1].t2, r_loop[1].t3

// r_loop[2].t1, r_loop[2].t2, r_loop[2].t3

// r_loop[3].t1, r_loop[3].t2, r_loop[3].t3

assign co = carry[N];

endmodule

7.8.2 Generate Conditional

A generate conditional is like an if-else-if generate construct that permits the following Verilog constructs to be conditionally instantiated into another module based on an

expression that is deterministic at the time the design is elaborated:

• Modules

• User defined primitives, Gate primitives

• Continuous assignments

• initial and always blocks

Example 7-33 shows the implementation of a parametrized multiplier If either a0_width

or a1_width parameters are less than 8 bits, a carry-look-ahead (CLA) multiplier is

instantiated If both a0_width or a1_width parameters are greater than or equal to 8 bits, a tree multiplier is instantiated

Example 7-33 Parametrized Multiplier using Generate Conditional

// This module implements a parametrized multiplier

module multiplier (product, a0, a1);

// Parameter Declaration This can be redefined

parameter a0_width = 8; // 8-bit bus by default

parameter a1_width = 8; // 8-bit bus by default

// Local Parameter declaration

// This parameter cannot be modified with defparam or

// with module instance # statement

localparam product_width = a0_width + a1_width;

// Port declarations

output [product_width -1:0] product;

input [a0_width-1:0] a0;

input [a1_width-1:0] a1;

// Instantiate the type of multiplier conditionally

// Depending on the value of the a0_width and a1_width

// parameters at the time of instantiation, the appropriate

// multiplier will be instantiated

generate

if (a0_width <8) || (a1_width < 8)

cla_multiplier #(a0_width, a1_width) m0 (product, a0, a1);

else

tree_multiplier #(a0_width, a1_width) m0 (product, a0, a1);

endgenerate //end of the generate block

endmodule

7.8.3 Generate Case

A generate case permits the following Verilog constructs to be conditionally instantiated into another module based on a select-one-of-many case construct that is deterministic at the time the design is elaborated:

• Modules

• User defined primitives, Gate primitives

• Continuous assignments

• initial and always blocks

Example 7-34 shows the implementation of an N-bit adder using a generate case block

Example 7-34 Generate Case Example

// This module generates an N-bit adder

module adder(co, sum, a0, a1, ci);

// Parameter Declaration This can be redefined

parameter N = 4; // 4-bit bus by default

// Port declarations

output [N-1:0] sum;

output co;

input [N-1:0] a0, a1;

input ci;

// Instantiate the appropriate adder based on the width of the bus // This is based on parameter N that can be redefined at

// instantiation time

generate

case (N)

//Special cases for 1 and 2 bit adders

1: adder_1bit adder1(c0, sum, a0, a1, ci); //1-bit implementation 2: adder_2bit adder2(c0, sum, a0, a1, ci); //2-bit implementation // Default is N-bit carry look ahead adder

default: adder_cla #(N) adder3(c0, sum, a0, a1, ci);

endcase

endgenerate //end of the generate block

endmodule

[ Team LiB ]