Tài liệu Soc Encounter P2 pdf

Standard Cell Placement Y Set placement blockage — | Design Edit flipChip Partition Hoorplan tee Cock Route Timing SI Power Verify Tools Specify ——> Placement Blockage — Choose

‘x Encounter - /misc/RAID2/COURSE/iclab/iclabt05/iclab2004 b/lab01/DEMO_1/encounter/CHIP |_ | Oleg

| Design Edit Flip Chip Partition Hoorplan Place Clock Route Timing Sl Power Verify Tools Help

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Standard Cell Placement

Y Set placement blockage

— | Design Edit flipChip Partition Hoorplan tee Cock Route Timing SI Power Verify Tools

Specify ——> Placement Blockage

— Choose M2, M83 Then there will be no cell placed under strip

x Specify Placement Blockage for St |— || Ope

~ Specify Placement Blockage for Strip and Routing Blockage ;

~ M2

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1 M4 _ M5

Cancel | Help | |

— Specify placement blockage for macros

CTU sg.32(61)

Press this button to add placement blockage

x

- /misc/RAID2/COURSEficlab/iclabt05/iclab2004 b/lab01/macro_ex/encounter - To

Edit Flip Chip Partition Hoorplan Place Cock Route Timing sl Power Verify Tools

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Specify placement blockage around macros without power ring or inside macros with power ring

System Integration & Silicon Implementation Group

Y Place standard cells

Design Edit HipGip Partition Hoorplan

Place | Gock Route Timing SI Power Verify Tools

Le Place

— Choose Timing Driven

— Choose Save New Netlist to a specified filename

Placement Effort Level

~, Prototyping

~, Low Effort

| Medium Effort|

~, High Effort

I Timing Driven |

If Save New Netlistto [CHIP.post_tdp.v

_J Ignore Scan Connection _! Ignore Spare Cell Connection

_t Save Placement to |CHIP.place

You may restart from this step by freeing design and reloading the saved netlist into Encounter

Free Design: type the command /freeDesign in the command line

Restore Design: || Design | Edit FlipChip Partition Hooplan Place Glock Route Timing SỈ Power Verify Tools

Restore Design

@®

og 33 (61) System Integration & Silicon Implementation Group.

x Encounter - /misc/RATD2/COURSEjiclab/iclabt05/iclab2004b/lab01/DEMO_ 1/encounter/CHIP T1 E3

Design Edit lipChip Partition © Floorplan Place lock Route Timing S| Power Verify Tools Help

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-> Standard cells

This is a low core

utilization design

Pre-CTS Optimization

vx Pre-CTS timing analysis

— timeDesign command

¢ It will run trial route, RC extraction, timing analysis, and generates detailed timing reports

¢ Type the following command in the command line

timeDesign —preCTS

¢ The generated timing reports are saved in /timingReports/ _, including

“ preCTS.cap”, “_preCTS.fanout”, “_preCTS.tran”, and “ preCTS_all.tarpt”

¢ If the timing is met, pre-CTS optimization can be skipped

— Reports ¢ Timing Summary

Remain —cntH cnt Be careful of negative congestion| TNS: 0.000ns_ Violating Paths: 0

-2: 5 — 0.02% 0 0.00% Pathgroup Slacks Negative slack should be fixe¢

4: 10 003% 0 0.00% reg2reg: 0.000ns

in2reg: 0.000ns

4: 5 ° 4 000% 10% oe 12 18% 09% real DRV (fanout, cap, tran): (0, 1, 0) =

Total DRV = real DRV + clock network DRV

CTU pg 35 (61) ystem integra ementation Group

Pre-CTS Optimization cont,

Vv Pre-CTS optimization

— optDesign command

¢ It will repair

— Setup slack, Setup times

— Design rule violations (DRVs), Remaining DRVs

¢ To optimize timing placed design for the first time with ideal clocks

optDesign —preCTS

¢ To further optimize a design after above command execution

optDesign —preCTS —incr

ri pg 36 (61) System Integration & Silicon Implementation Group

Clock Tree Synthesis

Y Clock Tree Synthesis (CTS)

— The goal of clock tree synthesis includes

¢ Creating clock tree spec file

¢ Building a buffer distribution network

¢ Routing clock nets using CTS-NanoRoute

— In automatic CTS mode, Encounter will do the following things

¢ Build the clock buffer tree according to the clock tree specitication file

¢ Balance the clock phase delay with appropriately sized, inserted clock

delayi buffer2

delay2 buffer3 ,FF3

delay3 buffer4

CTU pa.37 (61) System Integration & Silicon Implementation Group.

Clock Tree Synthesis (oni,

Y Clock Tree Synthesis (CTS) (cont,

— Creating clock tree specification file (.ctstch)

¢ Syntax for automatic CTS

Parameter Example

Buffer transistion time

NoGating NO CTS root pin Sink transition time

CLKBUFX2

Butler CLKINVX1 delay2 buffers F”Z

Phase delay 2

CTIỮ bg.38 (61) System Integration & Silicon Implementation Group.

Clock Tree Synthesis (oni,

Y Clock Tree Synthesis (CTS) (cont)

— Example of clock tree specification file (.ctstch)

AutoCTSRootPin — clk

SinkMaxT ran 400ps BufMaxTran 400ps

Buffer CLKBUFX1 CLKBUFX2 CLKBUFX3 CLKBUFX4

CLKBUFX8 CLKBUF12 CLKBUF16 CLKBUF20 CLKINVX1 CLKINVX2 CLKINVX3 CLKINVX4 CLKINVX8 CLKINVX12 CLKINVX16 CLKINV20

End

CTU pg.39 (61) System Integration & Silicon Implementation Group.

Clock Tree Synthesis (oni,

Y Specify clock tree

— Assign clock tree specification file

— | Design Edit HipChp Partition Hoorplan Place | Clock | Route Timing SI Power Verfy Tools

— Complete the form and click OK L> Specify Clock Tree

Field Fill In ¥ Spearty Clok ine —

Clock Tree File CHIP.ctstch (Clock Tree File [CHiP.ctetch B

¥ Synthesize clock tree An | cancel | - Hep |

— Create clock tree

— | Design Edit HipGhp Partitlion Hoorplan Place | Cock | Route Timing Si Power Verify Tools

— Complete the form and click OK “> synthesize Clock Tree

&% Synthesize Clock Tree

~ Clock Tree Synthesis

—Clock Tree Results

Clock Tree Synthesis @ Handle Clock Crossover No

J” Save Clock Tree Synthesis Report J” Save Clock Tree Routing Guide _j Save Clock Tree Macro Model J” Save Clock Nets

Result Directory: |CHIP_cts Base FileName: 'CHIP_ cts

[ ok || Appy | cancer | Hep | S2

CTIỮ bg.40 (61) System Integration & silicon Implementation Group

Post-CTS Optimization

Y Post-CTS timing analysis

— timeDesign command

¢ Type the following command in the command line to check setup time

timeDesign —postCTS

¢ Type the following command in the command line to check hold time

timeDesign —postC TS —hold

¢ The generated timing reports are saved in /timingReports/ _, including

1 (6

“ postCTS.cap”, “_postC TS.fanout”, “_postCTS.tran”, and

“ postCTS_all.tarpt”

Y Post-CTS optimization

— optDesign command

¢ To correct setup violations and design rule violations

optDesign —postCTS

¢ To correct hold violations

optDesign —postC TS —hold

SRoute

Y Connect standard cell power

— Connect from core power pads to standard cells

Design Edit HipChp Partition Hoorplian Place Glock

Route | Timing

SI Power Verify Tools

Lờ SRoute

— Complete the form and click Apply

Field

Block pins Pad pins

Pad rings Standard cell pins

Fill In

Stripes (unconnected)

CTU pg 42(61)

System Integration & Silicon Implementation Group

X SRouie

case | Advances | Via Generation | mx]

Net(s): |GND VDD

_J Level shifter pins

Net(s): |

-Í Blockpins _í Padpins _í Padrings | Standard cellpinsl _! Stripes (unconnected)

= Layer Change Control Top layer; MS — |

“ Straight connections and allow jogging )~ Prefer straight with layer change

“ Prefer different layer jog

~, Prefer same layer jog

Bottom layer: Ml — |

»x Straight connections only f= DRC clean

= Allow layer change

~» Same layer routing only

_| Area

~Í Extra config file TT

Draw

_J Connect to target inside the _! Delete existing routes _! Generate progress messages i0

[ox | apply _| Defaults | Cancel | Help |

% Encounter - /misc/RAID2/COURSE/iclab/iclabt0S/iclab2004 b/lab01/DEMO_1/encounter/CHIP , TT] E3

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NanoRoute

v Process Antenna Effect (PAE)

— PAE phenomenon

¢ During deep submicron wafer fabrication, gate damage can occur when excessive static charges accumulate and discharge, passing current through a gate

— The cause of PAE

¢ lf the area of the layer connected directly to the gate is large (or the layer connected to the gate through lower layers is large) relative to the area of the gate, the discharge of enough static charges can damage the oxide that insulates the gate and cause the chip to fail

— Prevention of PAE

¢ Method 1: changing the routing so the routing layers connected to a gate or connected to a gate through lower layers are not so large

¢ Method 2: inserting diodes that protect the gate by providing an alternate path to discharge the static charge

CTU bg.44 (61) System Integration & Silicon Implementation Group.

NanoRoute cont)

Crosstalk

VY Signal Integrity (SI) Issue wr

— Charge sharing : ose V7

— Propagated noise _A_ “0” Charge

— Overshoot ¥ Sharing —\- Leakage

¥Y Sl closure

— Occur when a design is free from SI induced functional glitch and timing failure

y¥ J Attacker ` A Y 7 attacker \ A

Se Ne \ a Se

d _— [— d

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NanoRoute cont)

Y SI prevention

— Placement-based SI prevention

¢ Reduce crosstalk glitch and delay variation ¢ Reduce coupling capacitance

elta delay

Downsize!

A delay

ri pg 46 (61) System Integration & Silicon Implementation Group

NanoRoute cont)

Y SI prevention ont,

— Routing-based SI prevention

¢ Wiring Spacing ¢ Layer Switching

¢ Parallel Wires Reducing ¢ Net Re-ordering

lf oS

© CTU bg.47 (61) System Integration & Silicon Implementation Group

NanoRoute cont,

v NanoRoute

— Routing the design without creating DRC or LVS violations

— Routing the design without degrading timing or creating signal integrity

violations

~ | Design Edit HipChp Partition Hoorplian Place lock | Route} Timing SI Power Venfy Tools

NanoRoute (native)

—Mlode

J Global Route Detail Route Start Iteration default End Iteration idefault

—Concurrent Routing Features

| FixAntenna | | InsertDiodes _| | Diode Cell Name [ANTENNA | Fill Cells |

[Timing Driven | Timing Driven Efort M mm SMART

[FSi Driven | Effort medium | mam

Concurrent Routing Features | Diode Cell Name | ANTENNA _ |_“?°#?sss sl viie Ie|

-Routing Control

| | | _! Selected Nets Only _| Regenerate Tracks Bottom Layer default Top Layer default

© Timing Driven _! ECO Route ECO Bottom Layer |default ECO Top Layer ‘default

—Job Control

- Auto Stop _t Batch

J Multi Threading CPUs 1 _! Super Threading Clients ộ Edit Clients |

Apply | Attribute | Save | Load | Cancel | Help |

CTU pg 48 (61) System Integration & Silicon Implementation Group.

% Encounter - /misc/RATD2/COURSE/iclab/iclabt05/iclab 2004 b/lab01/DEMO_1/encounter/CHIP | | Ed

Design Edit Flip Chip Partition Hoorplan Place Cock Route’ Timing sl Power Verify Tools Help

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Y Celtic

— Sl analysis

¢ Type the following command in the command line to do glitch noise analysis

timeDesign —postRoute —si

¢ Check the analysis result in /celtic/celtic.eco If there are any victims, freeDesign and restart NanoRoute with additional information If there is no victim, re-route is unnecessary

Propagated

YW _/ attacker LA noise ` pe

— Sl repair techniques

> Increase

wire < Add shielding

Insert buffer

Upsiz

victim driver

CTU so 50 (61) System Integration & Silicon Implementation Group.