CMOS LOGIC

CMOS LOGIC

SEMICON Solutions

CMOS Logic | eeee

Trinh bày: Đặng Tường Dương e@@

@@

SEMICON

Agenda

e CMOS logic

e Logic levels

e Transmission Gates

e Sequential Logic Cells

e Datapath Logic Cells

ee@

@66Q

ee0e8

e@

B=0 a B=1 Co B=0 H p=7 1L?" _ ite

if

VDD +— VDD A=8 s| [on A=1 | of A=t | [on 4 of F=NOR(A, B)

A -o|

ff

on

ị F=f IF =0 l =0 F =0 0/1/90

]

n-channel off | on

CMOS logic «a two-input NAND qate« a two-input NOR gate * Good ‘1's * Good ‘0's

SEMICON

Logic Levels son

Ves?) tn Yep? tn Ves=V in

1¬0 0 1-Vụ strong '0' weak’

strong ‘0’

Von a

tị D 4" 3 '0 i |

ry a = t Vc| weak '|

T

Naming of complex CMOS TH

——_» A —

—*»B Z ——*>C =

(a) (b)

Drive Strength

We ratio a cell to adjust Its drive strength and make bn=bp to create equal rise and fall times

SEMICON

Naming of complex CMOS

combinational logic cells

a

aL a

— push bubbles to the inputs -4

OR = paralle! Ễ

OR = paralle!

A AND : 7 VDD

pe

Transmission Gates eeee

CMOS transmission gate (TG, TX gate, pass gate, coupler)

G

strong 0

3

A

[Cow | CRIG

A=0: NMOS on, PMOS: off

SEMICON

sequential Logic Cells sss

latch is transparent

1 I] `

dl | 4 8 storage

an 0P - 0K ( f$ ck /——ŸÂ -

(a) (bì

ee@

@66Q

@e&G®6@

ee

CLKP

(a)

CLKN CLKN

QN

CLKP

CLK 14>" Ss — 1D

CLKN CLKP orc” i P—

load master

be

(b)

load slave

mm

SEMICON

Example of Basic Gates toc

¬

Inverter 2-input NAND 2-input NOR

Câu Hỏi & Trả Lời

SEMICON