NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.NIWE2 Schematics Document www.vi
Trang 1THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NIWE2 Schematics Document
www.vinafix.vn
Trang 2THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VOLUME DOWN MUTE
AUDIO ENHANCE BUTTON & LED
ESATA HDD AND USB CONN
RTS5138
HP JACK MIC JACK
NOVO BT POWER MANAGE BT
(UMA/DIS)
BlueTooth CONN CMOS Camera
Conexant CX20671
page37 page27 page33
page33 page 10,11
Trang 3THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
X
+VCCP
power plane
O O O O
+VGA_CORE +1.8VS
DDR3 Voltage Rails
+0.75VS
Cap sensor board
X X
X X
X
X
X SML0CLK
SMBUS Control Table
SMBCLK SMBDATA PCH
WLAN WWAN
SMB_EC_DA2
SMB_EC_CK1 SMB_EC_DA1
X
X X
X X
X
X X
X
X X X
I2C / SMBUS ADDRESSING
1 0 1 0 0 0 0 0
D2 A0
CLOCK GENERATOR (EXT.)
6 4 CMOS RIGHT SIDE
RIGHT SIDE 0
DEVICE PORT
3 2
11 NEW CARD
USB PORT LIST
WIRELESS 8
10
1 WLAN
NEW CARD
CARD READER
3G
9 7
LAN
LEFT SIDE
6 4
DEVICE PORT
5 3 2
PCIE PORT LIST
1
12 13
7 8
+3VALW +3VALW
+3VALW
+3VALW
+3VALW V
(45 BOM)
VGA@ FOR NVIDIA PART
CMOS@ ESATA function Camera function
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Trang 4THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Memory VREF switch SLI raster sync
AC power detect pin MEM_VID orPower supply control
N/A - H H H
L L
Hot plug detect for IFP link C
N/A
- -
-L - -
-Hot plug detect for IFP Link E Programmable Fan Control
Hot plug detect for IFP link F SLI swap ready signal I/O
Products
(3.3V) (1.05V)
(1.8V) (1.05V) (1.5V)
128bit 1024MB DDR3 21.07
20.97
128bit N10P-LP 1024MB DDR3 15.48
3.99 6.14
(3.3V) (1.05V)
(1.8V) (1.05V) (1.5V)
2.20 3.24
64bit N10M-LP 512MB DDR3
Trang 5SM_RCOMP0SM_RCOMP1
H _CATERR#
V CC PWRGOOD_1
XDP_BPM#3XDP_BPM#0XDP_BPM#2
XDP_BPM#5XDP_BPM#1
XDP _DBRESET#
X DP_TCKXDP_TRST#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
CHECK INTEL DOCUMENT #385422 Debug Port Design Guide Rev1.3
5
EC GPIO CONTROL
6
PCH GPIO CONTROL DDR3 CONNECTER
3 3
For Intel S3 Power Reduction.
For Intel S3 Power Reduction.
FROM POWER VTT
POWER GOOD SIGNAL
R1 870_0402_5%
R1 371K_0402_5%
R5 5749.9_0402_1%1 2
R1 900_0402_5%
C 3380.01U_0402_16V7K
R5 4849.9_0402_1%1 2
R1 951.5K_0402_1%
R1 910_0402_5%
GD
SQ422N7002_SOT23
2
R 186750_0402_1%
12
R5 6020_0402_1% 1 2
R57 1 @ 251_0402_1%
R 1923K_0402_1%
U8MC74VHC1G08DFT2G SC70 5PB
R 5552 10_0402_5%
R5 611 210K_0402_5%
R 16349.9_0402_1%2 1
R 3000_0402_5%
@
T17 P ADR5 58
SM_DRAMRST# F6
SM_RCOMP[0] AL1
BCLK# B16BCLK A16
BCLK_ITP# AT30BCLK_ITP AR30
PEG_CLK#PEG_CLK D16E16
DPLL_REF_SSCLK#DPLL_REF_SSCLK A17
PRDY# AT28
PREQ# AP27TCK AN28TMS AP28
TRST# AT27TDI AT29
TDO AR27TDI_M AR29TDO_M AP29DBR# AN25BPM#[0] AJ22
BPM#[1] AK22BPM#[2] AK24BPM#[3] AJ24BPM#[4] AJ25
BPM#[5] AH22BPM#[6] AK23BPM#[7] AH23
R 194750_0402_1%
R5 631 0_0402_5%2 R 1331 251_0402_5%
R1 390_0402_5%
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Trang 6PCIE_CRX_GTX_N0
PCIE_CRX_GTX_N8PCIE_CRX_GTX_N6PCIE_CRX_GTX_N4PCIE_CRX_GTX_N9PCIE_CRX_GTX_N12
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N2PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_P5PCIE_CRX_GTX_P11
PCIE_CRX_GTX_P1
PCIE_CTX_GRX_C_P0
PCIE_CTX_GRX_C_P10PCIE_CTX_GRX_C_P15
PCIE_CTX_GRX_C_P8PCIE_CTX_GRX_C_P6PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P13
PCIE_CTX_GRX_C_P7
PCIE_CTX_GRX_C_P1
PCIE_CTX_GRX_C_P9PCIE_CTX_GRX_C_P12
PCIE_CTX_GRX_C_P3PCIE_CTX_GRX_C_P5
PCIE_CTX_GRX_C_P2PCIE_CTX_GRX_C_P11
PCIE_CTX _GRX_C_N14
PCIE_CTX _GRX_C_N0
PCIE_CTX _GRX_C_N10
PCIE_CTX _GRX_C_N6PCIE_CTX _GRX_C_N8PCIE_CTX _GRX_C_N13
PCIE_CTX _GRX_C_N4PCIE_CTX _GRX_C_N9
PCIE_CTX_GRX_N4PCIE_CTX_GRX_N9
PCIE_CTX_GRX_P3PCIE_CTX_GRX_P5PCIE_CTX_GRX_P8PCIE_CTX_GRX_P6PCIE_CTX_GRX_P4PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P2PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P9PCIE_CTX_GRX_P12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
PCI-Express Configuration Select
0: Lane Numbers Reversed1: Normal OperationCFG3
CFG3-PCI Express Static Lane Reversal
15 -> 0, 14 ->1,
Layout rule : ace tr length < 0.5"
CFG[1:0] 11=1*16 PEG10=2*8 PEG
FOR ES1 SAMPLE ONLY
0: Enabled; An external Display Port1: Disabled; No Physical Display PortCFG4
CFG4-Display Port Presenceattached to Embedded Display Port
device is connected to the EmbeddedDisplay Port
RSVD38 AJ26
RSVD_NCTF_42 AT3
RSVD39 AJ27
RSVD_NCTF_40 AP1RSVD_NCTF_41 AT2
RSVD50 AT31RSVD51 AT32RSVD52 AP33RSVD53 AR33
RSVD_NCTF_54 AT33RSVD_NCTF_55 AT34RSVD_NCTF_56 AP35RSVD_NCTF_57 AR35
RSVD16
A19 RSVD15B19
RSVD22
AB9 RSVD21AC9
RSVD_TP_71 AA2RSVD_TP_72 AA1
RSVD_TP_73 R9RSVD_TP_69 AD3
RSVD_TP_74 AG7RSVD_TP_70 AD2
RSVD_TP_75 AE3RSVD_TP_76 V4RSVD_TP_77 V5RSVD_TP_78 N2
RSVD_TP_81 W3
RSVD_TP_82 W2RSVD_TP_83 N3RSVD_TP_79 AD5
RSVD_TP_84 AE5RSVD_TP_80 AD7
RSVD_TP_85 AD9
RSVD36 AL26RSVD_NCTF_37 AR2
RSVD_TP_59 E15
RSVD_TP_60 F15KEY A2RSVD62 D15RSVD63 C15
RSVD64 AJ15RSVD65 AH15
C5 601 2 0.1U_0402_10V6K
C5 591 2 0.1U_0402_10V6KC5 331 2 0.1U_0402_10V6K
R5 351 DI S@21K_0402_5%
R 1880_0402_5%
2
R5 460_0402_5%
2
C5 341 2 0.1U_0402_10V6KC5 401 2 0.1U_0402_10V6K
C5 581 2 0.1U_0402_10V6KC5 461 2 0.1U_0402_10V6K
C5 561 2 0.1U_0402_10V6K
C5 301 2 0.1U_0402_10V6KC5 481 2 0.1U_0402_10V6KC5 551 2 0.1U_0402_10V6K
PEG_RX#[0] K35PEG_RX#[1] J34
PEG_RX#[2] J33PEG_RX#[3] G35PEG_RX#[4] G32
PEG_RX#[5] F34
PEG_RX#[6] F31PEG_RX#[7] D35PEG_RX#[8] E33
PEG_RX#[9] C33PEG_RX#[10] D32PEG_RX#[11] B32PEG_RX#[12] C31
PEG_RX#[13] B28PEG_RX#[14] B30PEG_RX#[15] A31PEG_RX[0] J35PEG_RX[1] H34PEG_RX[2] H33
PEG_RX[3] F35
PEG_RX[4] G33PEG_RX[5] E34PEG_RX[6] F32
PEG_RX[7] D34PEG_RX[8] F33PEG_RX[9] B33PEG_RX[10] D31
PEG_RX[11] A32PEG_RX[12] C30PEG_RX[13] A28PEG_RX[14] B29
PEG_RX[15] A30PEG_TX#[0] L33PEG_TX#[1] M35
PEG_TX#[2] M33PEG_TX#[3] M30PEG_TX#[4] L31PEG_TX#[5] K32
PEG_TX#[6] M29PEG_TX#[7] J31PEG_TX#[8] K29
PEG_TX#[9] H30PEG_TX#[10] H29PEG_TX#[11] F29PEG_TX#[12] E28
PEG_TX#[13] D29PEG_TX#[14] D27PEG_TX#[15] C26PEG_TX[0] L34PEG_TX[1] M34PEG_TX[2] M32PEG_TX[3] L30
PEG_TX[4] M31PEG_TX[5] K31PEG_TX[6] M28PEG_TX[7] H31
PEG_TX[8] K28PEG_TX[9] G30PEG_TX[10] G29PEG_TX[11] F28
PEG_TX[12] E27PEG_TX[13] D28PEG_TX[14] C27
PEG_TX[15] C25 C5 501 2 0.1U_0402_10V6K
C5 631 2 0.1U_0402_10V6KC5 451 2 0.1U_0402_10V6KC5 641 2 0.1U_0402_10V6K
R 593.01K_0402_1%
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Trang 7DDR_A _D7DDR_A _D5
DDR_ A_D59DDR_ A_D57
DDR_ A_D47DDR_ A_D42
DDR_ A_D61
DDR_A _D2DDR_A _D0
DDR_ A_D55DDR_ A_D51DDR_ A_D48DDR_ A_D50DDR_ A_D52
DDR_ A_D31
DDR_ A_D14
DDR_ A_D25DDR_ A_D27
DDR_ A_D30
DDR_A _D9
DDR_ A_D13DDR_ A_D10
DDR_ A_D29
DDR_ A_D19DDR_ A_D16
DDR_ A_D21DDR_ A_D17
DDR_ A_D22DDR_ A_D18
DDR_A_M A9
DDR_A_MA 14DDR_A_MA 11
DDR_A_M A4
DDR_A_M A7
DDR_A_MA 10DDR_A_M A1
DDR_A_MA 12DDR_A_M A2
DDR_ B_D60
DDR_ B_D33DDR_ B_D11
DDR_ B_D41
DDR_ B_D45DDR_B _D0
DDR_ B_D48DDR_ B_D50DDR_ B_D38
DDR_ B_D21
DDR_ B_D32DDR_ B_D22
DDR_B _D4
DDR_ B_D14
DDR_ B_D27DDR_ B_D25
DDR_ B_D62DDR_ B_D59
DDR_ B_D19
DDR_ B_D52
DDR_B _D7DDR_B _D5
DDR_ B_D17
DDR_ B_D58
DDR_ B_D30DDR_ B_D26
DDR_ B_D36DDR_ B_D13
DDR_ B_D53
DDR_ B_D18DDR_B _D8
DDR_ B_D35
DDR_ B_D46DDR_ B_D12
DDR_ B_D47DDR_ B_D28DDR_B _D2
DDR_ B_D37
DDR_ B_D63
DDR_ B_D40DDR_ B_D29
DDR_ B_D61DDR_ B_D16
DDR_A_MA 15
DDR _A_DQS0DDR _A_DQS2
DDR _A_DQS6DDR _A_DQS4
DDR _A_DQS7
DDR_B_M A0
DDR_B_M A9DDR_B_M A7
DDR_B_MA 13
DDR_B_M A2DDR_B_M A4
DDR_B_MA 11
DDR_B_M A3DDR_B_M A5
DDR_B_MA 10DDR_B_M A8DDR_B_M A1
DDR_B_MA 12DDR_B_MA 14
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SA_CK#[1] Y5SA_CKE[0] P7
SA_CKE[1] P6
SA_CS#[0] AE2
SA_CS#[1] AE8
SA_ODT[0] AD8SA_ODT[1] AF9
SA_DM[0] B9SA_DM[1] D7SA_DM[2] H7
SA_DM[3] M7SA_DM[4] AG6SA_DM[5] AM7SA_DM[6] AN10
SA_DM[7] AN13
SA_DQS[0] C8SA_DQS#[0] C9
SA_DQS[1] F9
SA_DQS#[1] F8
SA_DQS[2] H9SA_DQS#[2] J9
SA_DQS[3] M9SA_DQS#[3] N9
SA_DQS[4] AH8SA_DQS#[4] AH7
SA_DQS[5] AK10
SA_DQS#[5] AK9
SA_DQS[6] AN11SA_DQS#[6] AP11
SA_DQS[7] AR13SA_DQS#[7] AT13
SA_MA[0] Y3
SA_MA[1] W1SA_MA[2] AA8SA_MA[3] AA3SA_MA[4] V1
SA_MA[5] AA9SA_MA[6] V8SA_MA[7] T1SA_MA[8] Y9
SA_MA[9] U6SA_MA[10] AD4SA_MA[11] T2SA_MA[12] U3
SA_MA[13] AG8SA_MA[14] T3SA_MA[15] V9
SB_CKE[1] M2
SB_CS#[0] AB8SB_CS#[1] AD6
SB_ODT[0] AC7
SB_ODT[1] AD1
SB_DM[0] D4SB_DM[1] E1
SB_DM[2] H3SB_DM[3] K1SB_DM[4] AH1SB_DM[5] AL2
SB_DM[6] AR4SB_DM[7] AT8
SB_DQS[4] AG2SB_DQS#[4] AH2
SB_DQS[5] AL5
SB_DQS#[5] AL4
SB_DQS[6] AP5SB_DQS#[6] AR5
SB_DQS[7] AR7
SB_DQS#[7] AR8
SB_DQS[0] C5SB_DQS#[0] D5
SB_DQS[1] E3
SB_DQS#[1] F4
SB_DQS[2] H4SB_DQS#[2] J4
SB_DQS[3] M5SB_DQS#[3] L4
SB_MA[0] U5SB_MA[1] V2
SB_MA[2] T5SB_MA[3] V3SB_MA[4] R1SB_MA[5] T8
SB_MA[6] R2SB_MA[7] R6SB_MA[8] R4SB_MA[9] R5
SB_MA[10] AB5SB_MA[11] P3SB_MA[12] R3SB_MA[13] AF7
SB_MA[14] P5SB_MA[15] N1
Trang 8VCCSENSEVSS SENSE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
1
For Intel S3 Power Reduction.
For Intel S3 Power Reduction.
Modify for cost revew.
GFX_VID[3] AP23GFX_VID[4] AM23GFX_VID[5] AP24GFX_VID[6] AN24
GFX_VR_EN AR25GFX_DPRSLPVR AT25
GFX_IMON AM24
VAXG_SENSE AR22VSSAXG_SENSE AT22
VDDQ6 AB7VDDQ7 AB4VDDQ8 Y1VDDQ9 W7
VDDQ10 W4VDDQ11 U1VDDQ12 T7VDDQ13 T4
VDDQ14 P1VDDQ15 N7VDDQ16 N4VDDQ17 L1
VDDQ18 H1
VTT0_59 P10VTT0_60 N10
VTT0_61 L10VTT0_62 K10
VCCPLL1 L26VCCPLL2 L27VCCPLL3 M26
VTT1_63 J22VTT1_64 J20
VTT1_65 J18VTT1_66 H21VTT1_67 H20VTT1_68 H19
R561 20_0402_5%
C1 6022U_0805_6.3V6M
@1
SQ232N7002_SOT23
SQ19BSS138_NL_SOT23-3
@
R2 6820K_0402_5%
J2JUMP_43X118
1 12
2
R1 321K_0402_5%
DI S@
12
2
C1 5922U_0805_6.3V6M
UMA@
1
2
C 19022U_0805_6.3V6M
@1
1 12
VID[3] AL35VID[4] AL33VID[5] AM33VID[6] AM35
VTT0_37 Y10VTT0_38 W10VTT0_39 U10VTT0_40 T10
VTT0_41 J12VTT0_42 J11
VTT0_1 AH14
VTT0_2 AH12
VTT0_3 AH11VTT0_4 AH10VTT0_5 J14
VTT0_6 J13VTT0_7 H14VTT0_8 H12VTT0_9 G14
VTT0_10 G13VTT0_11 G12VTT0_12 G11VTT0_13 F14
VTT0_14 F13VTT0_15 F12VTT0_16 F11
VTT0_17 E14
VTT0_18 E12VTT0_19 D14VTT0_20 D13
VTT0_21 D12VTT0_22 D11VTT0_23 C14VTT0_24 C13
VTT0_25 C12VTT0_26 C11VTT0_27 B14VTT0_28 B12
VTT0_29 A14VTT0_30 A13VTT0_31 A12VTT0_32 A11
VSS_SENSE AJ35
VTT0_43 J16VTT0_44 J15
C 3250.1U_0603_25V7K
1
2
C5 9210U_0805_6.3V6M
UMA@
1
2
R2 33220_0402_5%
www.vinafix.vn
Trang 9+C PU_CORE
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
VSS_NCTF3 AR34VSS_NCTF4 B34VSS_NCTF5 B2VSS_NCTF6 B1
VSS83 AE32VSS84 AE31VSS85 AE30VSS86 AE29
VSS87 AE28VSS88 AE27VSS89 AE26
VSS90 AE6
VSS91 AD10VSS92 AC8VSS93 AC4
VSS94 AC2VSS95 AB35VSS96 AB34VSS97 AB33
VSS98 AB32VSS99 AB31VSS100 AB30VSS101 AB29
VSS102 AB28VSS103 AB27VSS104 AB26
VSS105 AB6
VSS106 AA10VSS107 Y8VSS108 Y4
VSS109 Y2VSS110 W35VSS111 W34VSS112 W33
VSS113 W32VSS114 W31VSS115 W30VSS116 W29
VSS117 W28VSS118 W27VSS119 W26VSS120 W6
VSS121 V10VSS122 U8VSS123 U4VSS124 U2
VSS125 T35VSS126 T34VSS127 T33
VSS128 T32VSS129 T31VSS130 T30VSS131 T29
VSS132 T28VSS133 T27VSS134 T26VSS135 T6
VSS136 R10VSS137 P8VSS138 P4VSS139 P2
VSS140 N35VSS141 N34VSS142 N33VSS143 N32
VSS144 N31VSS145 N30VSS146 N29VSS147 N28
VSS148 N27VSS149 N26VSS150 N6
VSS151 M10VSS152 L35VSS153 L32VSS154 L29
VSS155 L8VSS156 L5VSS157 L2VSS158 K34
VSS159 K33VSS160 K30
Trang 10D DR_A_BS2
DDR_ A_D45DDR_A _D9
DD R_A_DQS#1
DDR_A_MA 14
DDR_ A_D55
DDR_A_M A4DDR_ A_D21
DDR_ A_D18
M _ODT1
DDR_ A_D43DDR_ A_D34
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
4*0402 1uf
1*0402 0.1uf VREF =
1*0402 2.2uf VDDSPD (3.3V)=
1*0402 0.1uf 1*0402 2.2uf
For Arranale only +VREF_DQ_DIMMA supply from a external 1.5V voltage divide circuit
2
R3 051K_0402_1%
2
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Trang 11DD R_B_DM2
DD R_B_DM1
+VREF_DQ _DIMMBDDR_B _D0
DD R_B_DQS#2DDR_ B_D11
DDR_ B_D54DDR_ B_D45
DDR_ B_D60
M _ODT2
DDR_ B_D37DDR_B_MA 14
DDR_ B_D55DDR_B_M A4
DDR_ B_D62
DDR_ B_D53DDR_ B_D47
M _ODT3
M _CLK_DDR3
M _CLK_DDR#3
DDR_ B_D38DDR_B_MA11
DDR_ B_D61DDR_B_M A2
SMB _CLK_S3
S MB_DATA_S3PM_EXTTS#1_RDDR _B_DQS6
DDR_ B_D35
DDR_B_MA 12
DDR _B_DQS4
DDR_ B_D42DDR_CKE2_DIM MB
DDR_ B_D48
M _CLK_DDR2
M _CLK_DDR#2
DDR_ B_D32DDR_B_MA 13
DDR_ B_D50DDR_ B_D41
+VREF_DQ_DIMMB
+1.5V
+0.75VS+VREF_DQ_DIMMB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
4*0402 1uf
1*0402 0.1uf VDDQ(1.5V) =
1*0402 2.2uf VDDSPD (3.3V)=
For Arranale only +VREF_DQ_DIMMB supply from a external 1.5V voltage divide circuit
R5 7210K_0402_5%1 2
DQ5 6VSS 8DQS0# 10DQS0 12
VSS 14DQ6 16DQ7 18
VSS 20
DQ12 22DQ13 24VSS 26
DM1 28RESET# 30VSS 32DQ14 34
DQ15 36VSS 38DQ20 40DQ17
DQ22 50
DQ23 52VSS 54DQ28 56
DQ29 58VSS 60DQS3# 62DQS3 64
VSS 66DQ30 68DQ31 70VSS 72
CKE1 74VDD 76
A15 78A14 80VDD 82A11 84
A7 86VDD 88A6 90
A4 92VDD 94A2 96A0 98
VDD 100CK1 102CK1# 104VDD 106
BA1 108RAS# 110VDD 112S0# 114
ODT0 116VDD 118ODT1 120
NC 122
VDD 124VREF_CA 126VSS 128DQ36 130
DQ37 132VSS 134DM4 136
VSS 138DQ38 140DQ39 142VSS 144
DQ44 146DQ45 148VSS 150DQS5# 152
DQS5 154VSS 156DQ46 158DQ47 160
VSS 162DQ52 164DQ53 166VSS 168
DM6 170VSS 172DQ54 174
DQ55 176
VSS 178DQ60 180DQ61 182
VSS 184DQS7# 186DQS7 188VSS 190
DQ62 192DQ63 194VSS 196EVENT# 198
SDA 200SA1
Trang 12+3VS_CK505 +1.05VS_CK505+3VS_CK505 +1.05VS_CK505
+1.05VS
+3VS_CK505+3VS_CK505
VDD_3V3_1V5+3VS_CK505
+1.5VS
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
1 PCS CAP(0.1u) BY 1 INPUT PIN
ICS9LVS3199AKLFT MLF 32P CLK GEN (SA00003HR00)
1 PCS CAP(0.1u) BY 1 INPUT PIN
1 PCS CAP(0.1u) BY 1 INPUT PIN
unstuff 09.09.08
R2 780_0603_5%
12
C3 6422P_0402_50V8J
12
C 34922P_0402_50V8J
12
27MHZ_SS
7
XTAL_IN 2827MHZ
6
USB_48
8
CPU_1 20VSS_CPU 21VDD_CPU_IO 18
R 2770_0603_5%1 2
R2 761 20_0402_5%
R2 9810K_0402_5%
SQ252N7002_SOT23-3
2
R2 690_0603_5%1 2
2
R3 191 20_0402_5%
R3 230_0402_5%
@12
Trang 13S ATAICOMPPCH_JTA G_RST#
PCH_JTAG_TMSPCH_JTAG_TDIPCH_JTAG _TDO
BIT CLKHDA _S Y NC
HDA _ SDIN0
H DA_SDOUT
PCH_INTVRMEN
SATA_ITX_DRX_P0SAT A_DTX_C_IRX_N0SAT A_ITX_C_DRX_N0
SAT A_ITX_C_DRX_N4
SATA_ITX_DRX_P1SAT A_DTX_C_IRX_N1SAT A_ITX_C_DRX_N1
PCH_JTA G_TCK
SPI_W P#
SPI_HOLD#
S PI_CLK_PCH_RSPI_SB _CS0#
SPI_SISPI_SO _R
GPIO 19
GPIO 21GPIO 19GPIO 21
SPI_CLK_PCHSPI_CLK_PCH
SATA_ITX _DRX_N4_CONNSAT A_DTX_C_IRX_N4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
H:Integrated VRM enable
L:Integrated VRM disable
*
GPIO33 = GPO , internal pull-up,should not be pulled low
GPIO19 = GPI,3.3V,CORE GPIO21 = GPI,3.3V,CORE
GPIO23 = NATIVE,3.3V,CORE
GPIO13 = GPI,3.3V,SUS flash ME core of strap pin pull down
PCH JTAGPre-Production
PCH JTAGProductionRefDes
PCH Pin
No InstallPCH_JTAG_TDO
R591R590
No InstallR587
R586
R595R594
HDD ODD
E-SATA
(2009,05,04)
FOR INTEL DPDG REV1.6 (MAY 2009)
R1 1810K_0402_5%
LDRQ1# / GPIO23 F34FWH4 / LFRAME# C34LDRQ0# A34
SATA1RXN AH6SATA1RXP AH5
SATA1TXN AH9SATA1TXP AH8SATA2RXN AF11
SATA2RXP AF9SATA2TXN AF7SATA2TXP AF6SATA3RXN AH3SATA3RXP AH1SATA3TXN AF3
SATA3TXP AF1SATA4RXN AD9SATA4RXP AD8
SATA4TXN AD6SATA4TXP AD5SATA5RXN AD3
SATA5RXP AD1SATA5TXN AB3SATA5TXP AB1
R4 8210K_0402_5%
R1 0033_0402_5%
CL RP3SHORT PADS
R 44710K_0402_5%
CL RP2SHORT PADS
R 50037.4_0402_1%
C 1400.01U_0402_16V7K2 1
C 64812P_0402_50V8J
C 64712P_0402_50V8J
C1 8315P_0402_50V8J
1
2
R 47910K_0402_5%2 1
X132.768KHZ_12.5PF_9H03200413
R1 023.3K_0402_5%
R990_0402_5%
C2 021U_0603_10V4Z
R7520K_0402_5%
@
R1 16100_0402_1%
C1 420.01U_0402_16V7K2 1ESATA@
R 1681 233_0402_5%
R1 541 10M_0402_5%2
R73200_0402_5%
C 1410.01U_0402_16V7K2 1
R 424 10K_0402_5%
@
R 10315_0402_5%
@
R1 0115_0402_5%
12
C1 3822P_0402_50V8J
@
R4 211M_0402_5%
R 419 20K_0402_1%1 2
C1 841U_0603_10V4Z
1
2
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Trang 14SM BCLKSMBDATA
GPIO 60SML0CLK
S ML0DATA
GPIO 74
SMB_EC_CK2_REC_SM B_CK2
SMB_EC_DA2_REC_SM B_DA2
EC_SM B_CK2EC_SM B_DA2SML1CLK
S ML1DATA
LID_OUT#
PEG_CLK REQ#
SM BCLKSMBDATA
GPIO 60
SM BCLKSMBDATA S MB_DATA_S3
SMB _CLK_S3
SMB_EC_CK2_RSMB_EC_DA2_R
EC_SM B_CK2EC_SM B_DA2PEG_CLK REQ#
C LK_PCI_FB
CLK_PCIE_LAN_RCLK_PCIE_LAN#_R
CLK_PCIE_VG A_RCLK _EXP#_RCLK _EXP_R
PCIE_PTX_DRX_P4
PCIE _PRX_DTX_N4PCIE_PRX_DTX_P4PCIE _PTX_DRX_N4
CLK _ PCIE_CARD_PCH#_RCLK _P CIE_CARD_PCH_R
CL K_PCI_DB_R
X TAL25_INXTAL25_OUT
XTAL25_OUTCLK_PCIE_EXP _PCH_R
CLK_PCIE_EXP _PCH#_R
CLK REQ_EXP#
PCIE_PTX_DRX_P5PCIE _PTX_DRX_N5PCIE_PRX_DTX_P5PCIE _PRX_DTX_N5
+3VALW
+3VS+3VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
WLAN
NEW CARD LAN
6
4
DEVICE PORT
@
R 1220_0402_5%
@
R1 481 2.2K_0402_5%2R4 041 2.2K_0402_5%2
R1 471 2.2K_0402_5%2
R1 9822_0402_5%
R1 451 10K_0402_5%2
R 1190_0402_5%
@
R1 231 2.2K_0402_5%2
R3 991 10K_0402_5%2R1 211 10K_0402_5%2
SML0CLK C6SML0DATA G8
CLKIN_BCLK_N AP3CLKIN_BCLK_P AP1
CLKIN_DMI_N AW24CLKIN_DMI_P BA24
CLKIN_DOT_96N F18CLKIN_DOT_96P E18
CLKIN_SATA_N / CKSSCD_N AH13CLKIN_SATA_P / CKSSCD_P AH12
XTAL25_IN AH51XTAL25_OUT AH53
REFCLK14IN P41CLKIN_PCILOOPBACK J42
CLKOUT_PEG_A_N AD43CLKOUT_PEG_A_P AD45
CLKOUT_DMI_N AN4CLKOUT_DMI_P AN2
PEG_B_CLKRQ# / GPIO56
P13
CLKOUT_PEG_B_P
AK51 CLKOUT_PEG_B_NAK53
SML1ALERT# / GPIO74 M14
SML1CLK / GPIO58 E10SML1DATA / GPIO75 G12
R 1201 210K_0402_5%
Q7B2N7002DW-T/R7_SOT363-6
3
4
Q8A2N7002DW-T/R7_SOT363-6
R 4541 210K_0402_5%
Q7A2N7002DW-T/R7_SOT363-6
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Trang 15DMI_CRX_PTX_N0DMI_CRX_PTX_N2
DMI_CRX_PTX_P0DMI_CRX_PTX_P2DMI_CTX_PRX_N1
P M_RSMRST#
DMI_CTX_PRX_N3
DMI_CTX_PRX_P1DMI_CTX_PRX_P3
FDI_CTX_PRX_P1FDI_CT X_PRX_N7FDI_CTX_PRX_P0
FDI_CTX_PRX_P3
FDI_CTX_PRX_P6FDI_CTX_PRX_P4
DA C _BLU
DA C_R ED
DA C_G RNPCH_ENBKL
E DI D_CLKEDID_DATA
S US _PWR_DN_ACK_R
S YS_PWROKVGATE
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
Checklist0.8:MEPWROK
can be connect to
PWROK if iAMT disable
If not using integratedLAN,signal may be left as NC
Can be left NC when IAMT is
GPIO29 = GPO,3.3V,SUS GPIO31 = GPI,3.3V,SUS
DDPB_2N BB40
DDPB_3N AW38
DDPC_0N BE40DDPC_1N BF41DDPC_2N BD38DDPC_3N BB36
DDPD_0N BJ40DDPD_1N BJ38
DDPB_0P BC42DDPB_1P BG42
DDPD_2P BH37DDPD_3P BD36
DDPB_2P BA40DDPB_3P BA38
DDPC_2P BC38
DDPC_3P BA36
DDPD_0P BG40DDPD_1P BG38
DDPD_CTRLCLK U50DDPD_CTRLDATA U52
SDVO_STALLP BG48
SDVO_STALLN BJ48
SDVO_INTP BH45SDVO_INTN BF45
FDI_RXN5 BE14FDI_RXN6 BA14FDI_RXN7 BC12FDI_RXP0 BB18FDI_RXP1 BF17FDI_RXP2 BC16
FDI_RXP3 BG16
FDI_RXP4 AW16FDI_RXP5 BD14FDI_RXP6 BB14
FDI_RXP7 BD12
FDI_FSYNC0 BF13FDI_FSYNC1 BH13
FDI_LSYNC0 BJ12FDI_LSYNC1 BG14
FDI_INT BJ14
PMSYNCH BJ10
TP23 N2SLP_M# K8SLP_S3# P12SLP_S4# H7SLP_S5# / GPIO63 E4
12
R 5042.2K_0402_5%
C 6391UMA_HDMI@2 0.1U_0402_10V6K
R 1752.2K_0402_5%
R 4511 0_0402_5%2
R5 022.37K_0402_1%
R5 991 @ 0_0402_5%2
R4 9710K_0402_5%
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Trang 16USB_OC#7USB_OC#4
USB_OC#0
USB_OC#3
USB_OC#5USB_OC#1
USB_OC#6
GPIO1GPIO6
GPIO 36
GPIO 36GPIO 17
+3VALW
+3VS
+3VS+1.8VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
GPIO27 if pull down to turn off 1.8V VR
A16 swap overide Strap/Top-Block
Swap Override jumper
Swap Override enabled
High=Default
Intel Anti-Theft Techonlogy
*
Weak internalPU,Do not pull lowSet to Vcc when HIGH DMI Termination Voltage
NV_ALE High=Enabled Low=Disable(floating)
NV_CLE Set to Vss when LOW
NV_ALE
NV_CLE
Enable Intel Anti-TheftTechnology:8.2K PU to +3VSDisable Intel Anti-TheftTechnology:floating(internal PD)DMI termination voltage
weak internal PU, don't PD
1 1
PCI_GNT1#
PCI_GNT0#
0
Boot BIOS Location 1
LPC Boot BIOS Strap
PCI
0 Reserved(NAND)
SPI 1
0 0
RIGHT SIDE 0
DEVICE PORT
3 2
11 NEW CARD
USB PORT LIST
WIRELESS 8
10
1
CARD READER
9 7
12 13
LEFT SIDE
LEFT SIDE
56 5% >checklist 1.654.9 1% >CRB 1.0
H:Intel ME Crypto TransportLayer Security(TLS) chiper suitewith confidentiality
L:Intel ME Crypto TransportLayer Security(TLS) chiper suitewith no confidentiality
High:Enables the internal VccVRM
to have a clean supply for analograils no need to use on boardfilter circuit
Default:Do not connect(floating)
it have weak internal PU 20K
GPIO12 = GPI,3.3V,SUS GPIO8 = GPO,3.3V,SUS GPIO7 = GPI,3.3V,CORE GPIO1 = GPI,3.3V,CORE
Check list Rev0.8 section1.23.2
If not implemented, the Braidwood
interface signals can be left as No Connect (NC).
TP11 AJ24TP12 AK41
THRMTRIP# BD10
GPIO8
F10
CLKOUT_PCIE6N AH45CLKOUT_PCIE6P AH46
PCIECLKRQ6# / GPIO45
H3
CLKOUT_PCIE7N AF48CLKOUT_PCIE7P AF47
PCIECLKRQ7# / GPIO46
F1
TP5 AY46TP4 AY45
NC_1 AB45NC_2 AB38NC_3 AB42NC_4 AB41
TP14 M32TP15 N32
SATA2GP / GPIO36
AB7
NC_5 T39INIT3_3V# P6
CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3
CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1
TP19 AA23TP18 H12
R1 1010K_0402_5%
R 11110K_0402_5%
NV_CLE AY6
NV_DQS0 AV9NV_DQS1 BG8NV_DQ0 / NV_IO0 AP7NV_DQ1 / NV_IO1 AP6
NV_DQ10 / NV_IO10 BD6
NV_DQ11 / NV_IO11 BB7NV_DQ12 / NV_IO12 BC8NV_DQ13 / NV_IO13 BJ8NV_DQ14 / NV_IO14 BJ6
NV_DQ15 / NV_IO15 BG6
NV_DQ2 / NV_IO2 AT6NV_DQ3 / NV_IO3 AT9
NV_DQ4 / NV_IO4 BB1NV_DQ5 / NV_IO5 AV6NV_DQ6 / NV_IO6 BB3
NV_DQ7 / NV_IO7 BA4
NV_DQ8 / NV_IO8 BE4NV_DQ9 / NV_IO9 BB6
NV_RB# AV7NV_RCOMP AU2
NV_WR#0_RE# AY8
NV_WR#1_RE# AY5NV_WE#_CK0 AV11NV_WE#_CK1 BF5
USBP0N H18USBP0P J18
USBP10N A22
USBP10P C22USBP11N G24USBP11P H24USBP12N L24
USBP12P M24USBP13N A24USBP13P C24
USBP1N A18USBP1P C18USBP2N N20USBP2P P20
USBP3N J20USBP3P L20USBP4N F20USBP4P G20
USBP5N A20USBP5P C20USBP6N M22
USBP7N B21USBP7P D21USBP8N H22
USBP8P J22USBP9N E22USBP9P F22
USBRBIAS# B25USBRBIAS D25
OC5# / GPIO9 G16OC6# / GPIO10 F12OC7# / GPIO14 T15
R1 07 10K_0402_5%1
2
R7610K_0402_5% 1 2
R 48010K_0402_5% 1 2
2
R1 0432.4_0402_1%
R 155100K_0402_5%
R 415 10K_0402_5%
R5 1856_0402_5%
R 48110K_0402_5% 1 2
R 44610K_0402_5%
2
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Trang 17P CH_V5REF_SUS
+PCH_VCC1_1_22+PCH_VCC1_1_20
+V1.1A_INT_V CCSUS+VCCSST
+5VALW
+3VS
+3VS
+PCH_VRM+1.05VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
0.344A 0.052A
0.035A 0.072A 0.073A
0.069A
0.030A
0.156A
6mA 0.035A 0.061A 0.059A
0.085A
0.042A 1.524A
support and not
Intel LAN, VCCLAN
Source=>GND
0.1uH inductor, 200mA
10uH inductor, 120mA10uH inductor, 120mA
C 1390.1U_0402_16V4Z
D6CH751H-40PT_SOD323-2
C4 9210U_0805_6.3V6M
UMA@
1
2
R 5090_0402_5%
@1
2
R 42310_0402_1%
R2 080_0603_5%
C 4860.01U_0402_16V7K
UMA@
1
2
R5 210_0402_5%
UMA@
12
UMA@
1
2
C4 941U_0402_6.3V4Z
@1
2
+C5 07220U_B2_2.5VM_R35
UMA@
1
2
C 4520.1U_0402_16V4Z
C4 760.1U_0402_16V4Z
VCCTX_LVDS[1] AP43
VCCTX_LVDS[2] AP45VCCALVDS AH38
VCCIO[1]
AM23
VCC3_3[2] AB34
VCC3_3[3] AB35VCC3_3[4] AD35
VCC3_3[1]
AN35
VCCME3_3[1] AM8VCCME3_3[2] AM9
VCCME3_3[3] AP11VCCME3_3[4] AP9
VCCPNAND[2] AK16
VCCPNAND[9] AM15VCCPNAND[1] AM16
VCCDMI[1] AT16VCCDMI[2] AU16
+C5 06220U_B2_2.5VM_R35
VCCIO[13] AD19
VCCIO[14] AF20VCCIO[15] AF19
VCC3_3[11] N36VCC3_3[12] P36
VCC3_3[13] U35
VCCRTC
A12
VCCSUS3_3[27] A26VCCSUS3_3[26] A28
VCCSUS3_3[25] B27VCCSUS3_3[24] C26VCCSUS3_3[23] C28VCCSUS3_3[22] E26
VCCSUS3_3[21] E28VCCSUS3_3[20] F26VCCSUS3_3[19] F28
VCCSUS3_3[18] G26
VCCSUS3_3[17] G28VCCSUS3_3[16] H26VCCSUS3_3[15] H28
VCCSUS3_3[14] J26VCCSUS3_3[13] J28VCCSUS3_3[12] L26VCCSUS3_3[11] L28
VCCSUS3_3[10] M26VCCSUS3_3[9] M28VCCSUS3_3[8] N26VCCSUS3_3[7] N28
VCCSUS3_3[6] P26VCCSUS3_3[5] P28VCCSUS3_3[4] U24
VCCSUS3_3[3] U26
VCCSUS3_3[2] U28VCCSUS3_3[1] V28
VCCME[15] Y35VCCME[16] AA35
UMA@
1
2
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Trang 18THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VSS[82] AK32
VSS[83] AK34VSS[84] AK35VSS[85] AK38
VSS[86] AK43VSS[87] AK46VSS[88] AK49VSS[89] AK5
VSS[90] AK8VSS[91] AL2VSS[92] AL52VSS[93] AM11
VSS[96] AM20
VSS[97] AM22
VSS[98] AM24VSS[99] AM26VSS[100] AM28
VSS[102] AM30VSS[103] AM31VSS[104] AM32
VSS[105] AM34VSS[106] AM35VSS[107] AM38VSS[108] AM39
VSS[109] AM42VSS[110] AU20VSS[111] AM46VSS[112] AV22
VSS[113] AM49VSS[114] AM7VSS[116] BB10
VSS[117] AN32VSS[118] AN50VSS[119] AN52
VSS[120] AP12VSS[121] AP42VSS[122] AP46VSS[123] AP49
VSS[124] AP5VSS[125] AP8VSS[126] AR2VSS[127] AR52
VSS[128] AT11VSS[131] AT32
VSS[132] AT36VSS[133] AT41VSS[134] AT47VSS[135] AT7
VSS[136] AV12VSS[137] AV16VSS[138] AV20VSS[139] AV24
VSS[140] AV30VSS[141] AV34VSS[142] AV38
VSS[143] AV42VSS[144] AV46VSS[145] AV49VSS[146] AV5
VSS[147] AV8VSS[148] AW14VSS[149] AW18VSS[150] AW2
VSS[151] BF9VSS[152] AW32VSS[153] AW36VSS[154] AW40
VSS[155] AW52VSS[156] AY11VSS[157] AY43VSS[158] AY47
VSS[101] BA42
VSS[95] AD24VSS[94] BB44U7I
VSS[268] L2VSS[269] L22VSS[270] L32VSS[271] L36
VSS[272] L40VSS[273] L52VSS[274] M12VSS[275] M16
VSS[276] M20VSS[277] N38VSS[278] M34
VSS[279] M38
VSS[280] M42VSS[281] M46VSS[282] M49
VSS[283] M5VSS[284] M8VSS[285] N24VSS[286] P11
VSS[288] P22VSS[289] P30VSS[290] P32
VSS[291] P34VSS[292] P42VSS[293] P45VSS[294] P47
VSS[295] R2VSS[296] R52VSS[297] T12VSS[298] T41
VSS[299] T46VSS[300] T49VSS[301] T5
VSS[302] T8VSS[303] U30VSS[304] U31VSS[305] U32
VSS[306] U34VSS[307] P38VSS[308] V11VSS[309] P16
VSS[310] V19VSS[311] V20VSS[312] V22VSS[313] V30
VSS[314] V31VSS[315] V32VSS[316] V34
VSS[322] V47VSS[323] V49VSS[324] V5
VSS[325] V7VSS[326] V8VSS[327] W2VSS[328] W52
VSS[329] Y11VSS[330] Y12VSS[331] Y15VSS[332] Y19
VSS[333] Y23VSS[334] Y28VSS[335] Y30VSS[336] Y31
VSS[337] Y32VSS[338] Y38VSS[339] Y43VSS[340] Y46
VSS[342] Y5VSS[343] Y6
VSS[344] Y8
VSS[341] P49
VSS[345] P24VSS[287] AD15
VSS[348] AT8VSS[349] AD47VSS[350] Y47VSS[351] AT12
VSS[352] AM6VSS[353] AT13VSS[354] AM5VSS[355] AK45
VSS[356] AK39VSS[366] AV14
VSS[262] K11VSS[263] K43
VSS[259] H49VSS[260] H5
VSS[261] J24
www.vinafix.vn
Trang 19VGA_LVDS_SCL_CVGA_LVDS_SDA_CXTALIN
PCIE_CTX_GRX_N1PCIE_CTX_GRX_P1PCIE_CTX_GRX_P0PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N4PCIE_CTX_GRX_P4PCIE_CTX_GRX_P5PCIE_CTX_GRX_N5PCIE_CTX_GRX_N6PCIE_CTX_GRX_P6PCIE_CTX_GRX_P7PCIE_CTX_GRX_N7PCIE_CTX_GRX_N8PCIE_CTX_GRX_P8PCIE_CTX_GRX_P9PCIE_CTX_GRX_N9PCIE_CTX_GRX_N10PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N11PCIE_CTX_GRX_P11PCIE_CTX_GRX_N12PCIE_CTX_GRX_P13PCIE_CTX_GRX_N13PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P14PCIE_CTX_GRX_N14PCIE_CTX_GRX_P15PCIE_CTX_GRX_N15
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_P12
PCIE_CRX_C_GTX_N12PCIE_CRX_GTX_P13
PCIE_CRX_C_GTX_P0PCIE_CRX_C_GTX_N0PCIE_CRX_C_GTX_N1PCIE_CRX_C_GTX_P1PCIE_CRX_C_GTX_P2PCIE_CRX_C_GTX_P3PCIE_CRX_C_GTX_N3PCIE_CRX_GTX_P4
PCIE_CRX_C_GTX_N2
PCIE_CRX_C_GTX_P5PCIE_CRX_C_GTX_P4PCIE_CRX_C_GTX_N5
PCIE_CRX_GTX_P2
PCIE_CRX_C_GTX_N6PCIE_CRX_GTX_P3
PCIE_CRX_C_GTX_P6PCIE_CRX_GTX_N3
PCIE_CRX_C_GTX_N7PCIE_CRX_C_GTX_P7PCIE_CRX_C_GTX_P8PCIE_CRX_C_GTX_N8
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_P10
PCIE_CRX_C_GTX_P9PCIE_CRX_C_GTX_N9PCIE_CRX_C_GTX_N10PCIE_CRX_C_GTX_P10PCIE_CRX_C_GTX_P11PCIE_CRX_C_GTX_N11PCIE_CRX_C_GTX_P12
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PCIE_CRX_C_GTX_P13PCIE_CRX_C_GTX_N13
VGA_LVDS_SCL_CVGA_LVDS_SDA_C
DACA_RSET
JTAG_TCK
VGA_ENBKL_RVGA_ENVDD_R
VGA_GPIO11
JTAG_TRST_NJTAG_TDOJTAG_TDI
I2CB_SDAI2CB_SCL
VGA_DDCDATA_CVGA_DDCCLK_C
NV_INVTPWMPCIE_CTX_GRX_N[0 15]
PCIE_CTX_GRX_P[0 15]
PEG_CLKREQ#
TESTMODE
VGA_LVDS_SCL <27>VGA_LVDS_SDA <27>
VGA_DDCDATA <26>VGA_DDCCLK <26>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
1.0V
VGA_CORE GPU_VID0
0
GPU_VID1
0.8V
P0 1
P8 0
0
GPIO6 GPIO5
1
Deep P12
1
0.85V P-State
0.9V
VGA_CORE GPU_VID0
0
GPU_VID1
0.8V
P0 1
P8 0
0 0x0A7D
N11M-GE1/LP1 (40nm)
R50510K_0402_5%
R5171DIS@ 2 2.2K_0402_5%
C101DIS@ 1 2 0.1U_0402_16V7KC100DIS@ 1 2 0.1U_0402_16V7K
R5121DIS@ 2 0_0402_5%
C45012P_0402_50V8J
C106DIS@ 1 2 0.1U_0402_16V7K
C97 DIS@ 1 2 0.1U_0402_16V7K
T11PAD
R530 1DIS@ 2 150_0402_1%
R4992.2K_0402_5%
R4782.2K_0402_5%
DIS@
R2510K_0402_5%1@ 2
C45112P_0402_50V8J
R64 2DIS@ 1 2.2K_0402_5%
C99 DIS@ 1 2 0.1U_0402_16V7KC110DIS@ 1 2 0.1U_0402_16V7KC118DIS@ 1 2 0.1U_0402_16V7K
R4210K_0402_5%
GPIO0 N1GPIO1 G1GPIO2 C1GPIO3 M2GPIO4 M3GPIO5 K3GPIO6 K2GPIO7 J2GPIO8 C2GPIO9 M1GPIO10 D2GPIO11 D1GPIO13 J1
DACA_HSYNC AD2DACA_VSYNC AD1DACA_RED AE2DACA_BLUE AD3DACA_GREEN AE3
DACA_RSET AE1DACA_VREF AF1
PEX_TSTCLK_OUTAF10
PEX_TSTCLK_OUT_NAE10
GPIO14 K1GPIO15 F3GPIO16 G3GPIO17 G2GPIO18 F1GPIO19 F2GPIO12 J3
PEX_REFCLKAB10PEX_REFCLK_NAC10
PEX_RST_NAD9
PEX_RX7AG18PEX_RX7_NAG19PEX_RX8AF19PEX_RX8_NAE19PEX_RX9AE21PEX_RX9_NAF21PEX_RX10AG21PEX_RX10_NAG22PEX_RX11AF22PEX_RX11_NAE22PEX_RX12AE24PEX_RX12_NAF24PEX_RX13AG24PEX_RX13_NAF25PEX_RX14AG25PEX_RX14_NAG26PEX_RX15AF27PEX_RX15_NAE27
PEX_TERMPAG10
PEX_TX0AD10PEX_TX0_NAD11PEX_TX1AD12PEX_TX1_NAC12PEX_TX2AB11PEX_TX2_NAB12PEX_TX3AD13PEX_TX3_NAD14PEX_TX4AD15PEX_TX4_NAC15PEX_TX5AB14PEX_TX5_NAB15PEX_TX6AC16PEX_TX6_NAD16PEX_TX7AD17PEX_TX7_NAD18PEX_TX8AC18PEX_TX8_NAB18PEX_TX9AB19PEX_TX9_NAB20PEX_TX10AD19PEX_TX10_NAD20PEX_TX11AD21PEX_TX11_NAC21PEX_TX12AB21PEX_TX12_NAB22PEX_TX13AC22PEX_TX13_NAD22PEX_TX14AD23PEX_TX14_NAD24PEX_TX15AE25PEX_TX15_NAE26
PEX_CLKREQ_NAE9
DACB_HSYNC U6DACB_VSYNC U4DACB_RED T5DACB_BLUE R4DACB_GREEN T4DACB_VREF R6DACB_RSET V6
JTAG_TCK AF3JTAG_TDI AG4JTAG_TDO AE4JTAG_TMS AF4JTAG_TRST_N AG3TESTMODE AD25
XTAL_SSIN D11XTAL_OUTBUFF E9XTAL_OUT E10XTAL_IN D10
I2CS_SCL T1I2CS_SDA T2
I2CH_SCL A3I2CH_SDA A4
I2CC_SCL A2I2CC_SDA B1
I2CB_SCL R2I2CB_SDA R3
I2CA_SCL R1I2CA_SDA T3
C8512P_0402_50V8J
R541 2.49K_0402_1%1 2 DIS@
C5620P_0402_50V8
DIS@
1
2
C95 DIS@ 1 2 0.1U_0402_16V7KC117DIS@ 1 2 0.1U_0402_16V7K
C8612P_0402_50V8J
Trang 20VGA_LVDS_A2#
VGA_LVDS_A2VGA_LVDS_A0#
VGA_LVDS_ACLK#
VGA_LVDS_ACLK
ROM_SIROM_SOROM_SCLK
STRAP2STRAP1STRAP0
IFPC_AUXIFPC_AUX_N
FBAA5
FBBACS0#
FBAA7FBAA_CKEFBACAS#
FBA_BA1
FBA_BA0FBA_RSTFBAA12
FBBA4FBARAS#
FBBA_CKE
FBAA[0 13]
FBBA[2 5]
FBADQS#2FBADQS#4FBADQS#6FBADQS#0
FBADQS2FBADQS4FBADQS6FBADQS0
FBADQM5
FBADQM0FBADQM2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
C430.01U_0402_16V7K
@1
2
R391 DIS@ 2 1K_0402_1%
Q38A2N7002DW-T/R7_SOT363-6
DIS@
61
R44510K_0402_5%
DIS@
R2310K_0402_5%
DIS@
Q38B2N7002DW-T/R7_SOT363-6
DIS@
T2PADT3PAD
R5314.7K_0402_5%
DIS@
R1510K_0402_5%
DIS@
R291.3K_0402_1%
@
T1PAD
R4771 @ 2 1K_0402_1%
R441 @ 2 1K_0402_1%
C64912P_0402_50V8J
2
R46810K_0402_5%
DIS@
C65012P_0402_50V8J
@12
FBA_CMD0 F26FBA_CMD1 J24FBA_CMD2 F25FBA_CMD3 M23FBA_CMD4 N27FBA_CMD5 M27FBA_CMD6 K26FBA_CMD7 J25FBA_CMD8 J27FBA_CMD9 G23FBA_CMD10 G26FBA_CMD11 J23FBA_CMD12 M25FBA_CMD13 K27FBA_CMD14 G25FBA_CMD15 L24FBA_CMD16 K23FBA_CMD17 K24FBA_CMD18 G22FBA_CMD19 K25FBA_CMD20 H22FBA_CMD21 M26FBA_CMD22 H24FBA_CMD23 F27FBA_CMD24 J26FBA_CMD25 G24FBA_CMD26 G27FBA_CMD27 M24FBA_CMD28 K22
FBA_DEBUG M22
FBA_CLK1 N24FBA_CLK1_N N23
FBA_CLK0 F24FBA_CLK0_N F23FB_VREF A16
FBA_DQS_WP2 E19FBA_DQS_WP4 T22
FBA_DQS_RN2 E18FBA_DQS_RN4 R22
FBA_DQM2 D19FBA_DQM4 T24
FBA_CMD29 J22FBA_CMD30 L22FBA_DQM1 B19FBA_DQM3 D23FBA_DQM0 C26
FBA_DQM5 AA23FBA_DQM6 AB27FBA_DQM7 T26FBA_DQS_RN1 A18FBA_DQS_RN3 B24FBA_DQS_RN0 D25
FBA_DQS_RN5 Y24FBA_DQS_RN6 AA27FBA_DQS_RN7 R27
FBA_DQS_WP1 A19FBA_DQS_WP3 A24FBA_DQS_WP0 C25
FBA_DQS_WP5 AA24FBA_DQS_WP6 AA26FBA_DQS_WP7 T27
FBA_D63N26 FBA_D62N25FBA_D60R26FBA_D61T25FBA_D59V27FBA_D56V25FBA_D57R25FBA_D58V26FBA_D55AD27
FBA_D44AA22
FBA_D51W25FBA_D52AB25FBA_D53AB26FBA_D54AD26
FBA_D49W27FBA_D50W26FBA_D48AA25 FBA_D47V22 FBA_D46W22 FBA_D45W23
FBA_D40AC24FBA_D41AB23FBA_D42AB24FBA_D43W24
FBA_D39P22 FBA_D38P24 FBA_D37R23
FBA_D32U24FBA_D33V24FBA_D34V23FBA_D35R24FBA_D31A26 FBA_D30B25 FBA_D29A25 FBA_D28C22
FBA_D0D22FBA_D1E24FBA_D2E22FBA_D3D24FBA_D4D26FBA_D5D27FBA_D6C27FBA_D7B27FBA_D8A21FBA_D9B21FBA_D10C21FBA_D11C19FBA_D12C18FBA_D13D18FBA_D14B18FBA_D15C16FBA_D16E21FBA_D17F21FBA_D18D20FBA_D19F20FBA_D20D17FBA_D21F18FBA_D22D16FBA_D23E16FBA_D24A22FBA_D25C24FBA_D26D21FBA_D27B22
R1610K_0402_5%
DIS@
R2610K_0402_5%1DIS@ 2
BUFRST_N N5
THERMDN D8
ROM_SCLK C9ROM_SI A10ROM_SO C10ROM_CS_N B10
STRAP0 C7IFPB_TXC
AB3IFPB_TXC_NAB2IFPB_TXD4W1IFPB_TXD4_NV1IFPB_TXD5W3IFPB_TXD5_NW2IFPB_TXD6AA2IFPB_TXD6_NAA3IFPB_TXD7AB1IFPB_TXD7_NAA1
IFPD_AUX_I2CX_SCLD3
IFPD_AUX_I2CX_SDA_ND4
IFPD_L0F5IFPD_L0_NF4IFPD_L1E4IFPD_L1_ND5IFPD_L2C3IFPD_L2_NC4IFPD_L3B3IFPD_L3_NB4
IFPC_AUX_I2CW_SCLG4
IFPC_AUX_I2CW_SDA_NG5
IFPC_L0P4IFPC_L0_NN4IFPC_L1M5IFPC_L1_NM4IFPC_L2L4IFPC_L2_NK4IFPC_L3H4IFPC_L3_NJ4
IFPE_AUX_I2CY_SCLF7
IFPE_AUX_I2CY_SDA_NG6
IFPE_L0D6IFPE_L0_NC6IFPE_L1A6IFPE_L1_NA7IFPE_L2B6IFPE_L2_NB7IFPE_L3E6IFPE_L3_N
IFPD_RSET M6IFPC_RSET R5IFPAB_RSET AB6
STRAP2 A9STRAP1 B9
SPDIF F9CEC N2
NC C15
NC D15
NC J5
RFU_1 T6RFU_2 W6RFU_3 Y6RFU_4 AA6RFU_5 N3
THERMDP D9
R5264.7K_0402_5%
DIS@
www.vinafix.vn
Trang 21+1.05VS
+1.05VS+1.05VS
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
FB_PLLVDD=100mA FB_DLLVDD=100mA
220mA NEAR BGA
The power is base on VRAM type.
N10M-GS: 2.63A N11M-GE1:2.55A
C4960.1U_0402_10V7K
DIS@
1
2
C4991U_0402_6.3V6K
DIS@
1
2
R4710K_0402_5%2 1 @
C244.7U 6.3V K X5R 0603
DIS@
1
2
C320.047U_0402_25V7K
DIS@
1
2
C470.1U_0402_10V7K
DIS@
1
2
C5124.7U 6.3V K X5R 0603
DIS@
1
2
C5110.1U_0402_10V7K
DIS@
1
2
C491U_0402_6.3V6K
DIS@
1
2
C610.1U_0402_10V7K
DIS@
12
R4310K_0402_5%
DIS@
12
C264.7U 6.3V K X5R 0603
DIS@
1
2
C460.1U_0402_10V7K
DIS@
1
2
C651U_0402_6.3V6K
DIS@
1
2
C630.1U_0402_10V7K
DIS@
1
2
C523470P_0402_50V7K
DIS@
1
2
C53810U_0805_6.3V6M
DIS@
1
2
C600.1U_0402_10V7K
DIS@
1
2
C4824.7U 6.3V K X5R 0603
DIS@
1
2
C4810.1U_0402_10V7K
DIS@
1
2
C5191U_0402_6.3V6K
DIS@
1
2
C420.047U_0402_25V7K
DIS@
1
2
C360.047U_0402_25V7K
DIS@
1
2
C4884.7U 6.3V K X5R 0603
DIS@
1
2
C711U_0402_6.3V6K
DIS@
1
2
C540.1U_0402_10V7K
DIS@
1
2
C5200.1U_0402_10V7K
DIS@
1
2
C620.1U_0402_10V7K
DIS@
1
2
C580.1U_0402_10V7K
DIS@
1
2
C5244.7U 6.3V K X5R 0603
DIS@
1
2
C280.01U_0402_16V7K
DIS@
1
2
C410.047U_0402_25V7K
DIS@
1
2
C370.01U_0402_16V7K
DIS@
1
2
C824.7U 6.3V K X5R 0603
DIS@
1
2
C5130.1U_0402_10V7K
DIS@
1
2
C310.047U_0402_25V7K
DIS@
1
2
C351U_0402_6.3V6K
DIS@
1
2
C301U_0402_6.3V6K
DIS@
1
2
C5210.1U_0402_10V7K
DIS@
1
2
L24MBK1608121YZF_0603
DIS@
C500.1U_0402_10V7K
VDDP11 VDDN19 VDDN17 VDDN16 VDDN15 VDDN14
VDDR12
VDDM11
VDDN12
VDDM9 VDDL9 VDDJ13 VDDJ12 VDDJ10 VDDJ9
VDDN13
VDDP12VDDP13VDDP14VDDP15VDDP16VDDP17VDDR9VDDR11
VDDN11VDDM17VDDN9
VDDU19VDD
W 9
VDD
W 13VDD
W 18VDD
W 19
FBVDDQ A13FBVDDQ B13FBVDDQ C13FBVDDQ D13FBVDDQ D14FBVDDQ E13FBVDDQ F13FBVDDQ F14FBVDDQ F15FBVDDQ F16
VDD
W 12 VDD
W 10
FBVDDQ F17FBVDDQ F19FBVDDQ F22FBVDDQ H23FBVDDQ H26FBVDDQ J15FBVDDQ J16FBVDDQ J18FBVDDQ J19FBVDDQ L19FBVDDQ L23FBVDDQ L26FBVDDQ M19FBVDDQ N22FBVDDQ U22FBVDDQ Y22
PEX_IOVDDQ AB7PEX_IOVDDQ AB8PEX_IOVDDQ AB9PEX_IOVDDQ AB13PEX_IOVDDQ AB16PEX_IOVDDQ AB17PEX_IOVDDQ AC7PEX_IOVDDQ AC13PEX_IOVDDQ AD6PEX_IOVDDQ AE6PEX_IOVDDQ AF6PEX_IOVDDQ AG6
PEX_IOVDD AG7PEX_IOVDD AF7PEX_IOVDD AE7PEX_IOVDD AD8PEX_IOVDD AD7PEX_IOVDD AC9PEX_PLLVDD AF9VID_PLLVDD K6SP_PLLVDD L6PLLVDD K5FB_PLLAVDD R19
VDD_SENSE W 15FB_CAL_PD_VDDQ B15DACB_VDD W 5DACA_VDD AG2
FB_PLLAVDD AC19FB_DLLAVDD T19
VDD_SENSE E15
VDD33A12VDD33B12VDD33C12VDD33D12VDD33E12VDD33F12
IFPE_PLLVDDD7IFPD_PLLVDDN6IFPC_PLLVDDP6IFPAB_PLLVDDAD5
IFPDE_IOVDDH6IFPC_IOVDDJ6IFPB_IOVDDV2IFPA_IOVDDV3PEX_SVDD_3V3AG9
C234.7U 6.3V K X5R 0603
DIS@
1
2
C290.01U_0402_16V7K
DIS@
1
2
L1MBK1608121YZF_0603
DIS@
C440.1U_0402_10V7K
DIS@
1
2
C4970.1U_0402_10V7K
DIS@
1
2
C641U_0402_6.3V6K
DIS@
1
2
L21MBK1608121YZF_0603
DIS@
12
C574.7U 6.3V K X5R 0603
DIS@
1
2
C481U_0402_6.3V6K
DIS@
1
2
C380.047U_0402_25V7K
DIS@
1
2
C740.1U_0402_10V7K
DIS@
1
2
C390.01U_0402_16V7K
DIS@
1
2
C55222U_0805_6.3V6M
DIS@
1
2
C4800.1U_0402_10V7K
DIS@
1
2
C520.01U_0402_16V7K
DIS@
1
2
C530.01U_0402_16V7K
DIS@
1
2
C734.7U 6.3V K X5R 0603
DIS@
1
2
C831U_0402_6.3V6K
DIS@
1
2
L5MBK1608121YZF_0603
DIS@
C510.01U_0402_16V7K
DIS@
1
2
L29MBK1608121YZF_0603
2
C550.1U_0402_10V7K
DIS@
1
2
C660.1U_0402_10V7K
DIS@
1
2
C5224700P_0402_25V7K
DIS@
1
2
C5100.1U_0402_10V7K
DIS@
1
2
L3MBK1608121YZF_0603
DIS@
C55310U_0805_6.3V6M
DIS@
1
2
C590.1U_0402_10V7K
DIS@
1
2
C5514.7U 6.3V K X5R 0603
DIS@
1
2
C451U_0402_6.3V6K
DIS@
1
2
C671U_0402_6.3V6K
DIS@
1
2
C684.7U 6.3V K X5R 0603
DIS@
1
2
C4981U_0402_6.3V6K
DIS@
1
2
C721U_0402_6.3V6K
DIS@
1
2
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Trang 22THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A total of 24 logical strapping bits are available
6 physical strapping pins
4 logical strapping bits
Place Components Close to BGA
DG-04642-001-V01(May 22, 2009)
Memory/PKG
40.2 ohm FB_CAL_PU_GND FBCAL_PD_VDDQ DDR3
FBCAL_TERM_GND FBVDDQ
+1.5VS
Must be used 1% resister for driver calibration
40.2/60.4 ohm 40.2 ohm
PD 15K
PD 15K ROM_SO
PU 35K
ROM_SI
GPU Samsung 800MHz (defaul)
GND T14GND T15GND T16
GND U2GND U5GND U11GND U12GND U13GND U14GND U15GND U16GND U17
GND AF14GND AF17GND AF20GND AF23GND AF26
GND U23GND U26GND V9GND V19GND W11GND W14GND W17GND Y2GND Y5GND Y23GND Y26GND AC2GND AC5GND AC6GND AC8GND AC11GND AC14GND AC17GND AC20GND AC23GND AC26GND AF2GND AF5GND AF8GND AF11
GNDE17GNDE20GNDE23GNDE26GNDH2GNDH5GNDJ11GNDJ14GNDJ17GNDK9GNDK19GNDL2GNDL5GNDL11GNDL12GNDL13GNDL14GNDL15GNDL16GNDL17GNDM12GNDM13GNDM14GNDM15GNDM16GNDP2GNDP5GNDP9GNDP19GNDP23GNDP26GNDT12GNDT13
GND_SENSEE14GND_SENSEW16
FB_CAL_PU_GND A15FB_CAL_TERM_GND B16
MULTI_STRAP_REF0_GND F10MULTI_STRAP_REF1_GND F11
Trang 23FBACLK1FBACLK 1#
FBACLK 0#
FBACLK0
FBADQS#2FBADQ M2FBADQS2
FBA_B A1FBAA 11FBAA5
FBACAS#
F BAWE#
FBA_B A0FBAA 12
FBAA8FBAA3FBAA1
FBACAS#
FBAA4
FBAA_CKEFBA_B A0FBAA1
FBA_B A2FBAA6
FBA_B A1
FBAA 11FBAA8
FBARAS#
FBA_B A1
FBBA2FBBA4
FBAA9FBAA6FBAA8FBAA1
FBBACS 0#
FBAA8FBBA2
FBAA 13FBAA 10
FBARAS#
FBBA5
FBA_ RST
FBAA 11FBBA4
F BAWE#
FBA_B A2FBAA0
FBA_B A1FBAA 12
FBACLK 1#
FBACLK1FBACLK 0#
FBA_D18FBA_D19
FBA_D25FBA_D31FBA_D30
FBA_D0
FBA_D6FBA_D1
FBA_D3FBA_D2
FBA_D58
FBA_D60FBA_D56
FBA_D59FBA_D62FBA_D63FBA_D57
FBA_D39FBA_D35
FBA_D38FBA_D37
FBA_D55FBA_D54
FBA_D52FBA_D53
FBA_D51FBA_D49
FBA_D8FBA_D9
FBA_D13FBA_D15FBA_D12FBA_D14
FBA_D41FBA_D40FBA_D42
FBA_D44FBA_D45FBA_D46
FBA_D47FBA_D34
FBA_D33
FBA_D36FBA_D32
+1.5VS+1.5VS
+VRAM_VREFA+VRAM_VREFB
+VRAM_VREFC+VRAM_VREFD
+VRAM_VREFC+VRAM_VREFD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
C51810U_0603_6.3V6M
D IS@
1
2
R523240_0402_1%
DQL3 F9
DQL4 H4DQL5 H9DQL6 G3DQL7 H8
VSSQ D2
VSS A10VSS E2
VSSQ B2
VSSQ B10VSSQ D9VSSQ E3
DQU6 B9
DQU7 A4DQU0 D8
VDD R2
VDD R10
VSS J9VSS M2VSS M10VSS P2
VSS P10VSS T2VSS T10VDDQ D3
DQL3 F9
DQL4 H4DQL5 H9DQL6 G3DQL7 H8
VSSQ D2
VSS A10VSS E2
VSSQ B2
VSSQ B10VSSQ D9VSSQ E3
DQU6 B9
DQU7 A4DQU0 D8
VDD R2
VDD R10
VSS J9VSS M2VSS M10VSS P2
VSS P10VSS T2VSS T10VDDQ D3
DQL3 F9
DQL4 H4DQL5 H9DQL6 G3DQL7 H8
VSSQ D2
VSS A10VSS E2
VSSQ B2
VSSQ B10VSSQ D9VSSQ E3
DQU6 B9
DQU7 A4DQU0 D8
VDD R2
VDD R10
VSS J9VSS M2VSS M10VSS P2
VSS P10VSS T2VSS T10VDDQ D3
DQL3 F9
DQL4 H4DQL5 H9DQL6 G3DQL7 H8
VSSQ D2
VSS A10VSS E2
VSSQ B2
VSSQ B10VSSQ D9VSSQ E3
DQU6 B9
DQU7 A4DQU0 D8
VDD R2
VDD R10
VSS J9VSS M2VSS M10VSS P2
VSS P10VSS T2VSS T10VDDQ D3
D IS@
R 191.33K_0402_1%
D IS@
R81.33K_0402_1%
D IS@
C44410U_0603_6.3V6M
D IS@
1
2
R 101.33K_0402_1%
D IS@
1
2
C310U_0603_6.3V6M
D IS@
R 442243_0402_1%
D IS@
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Trang 24HD MI_CLK-_CK
HDMI_TX2+_CK
HDMI_TX0+_CKHDMI_TX0-_CKHDMI_CLK+_CK
HDMI_DETECT_VGA
HDMI_TX1+_CK
HDMI_TX2-_CKHDMI_TX1-_CK
HD MI_CLK-_CK
HDMI_TX2+_CK
HDMI_TX0+_CKHDMI_TX0-_CKHDMI_CLK+_CK
HDMI_TX0+_CONN
HDMI_TX0-_CONNHDM I_CLK+_CONN
HDMI_TX2-_CONN
HDMI_ CLK-_CONN
HDMI_TX2+_CONNHDMI_TX1+_CK
HDMI_TX0+_CONNHDMI_TX0-_CONNHDM I_CLK+_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
HDMI@
R2572.2K_0402_5%
HDMI@
R5810_0805_5%
DIS@
D23BAT54S-7-F_SOT23-3
@2
31
R5821HDMI@2 0_0402_5%
C6011 2 DIS@0.1U_0402_16V7K
R5941HDMI@2 0_0402_5%
R2492.2K_0402_5%
@2
31
L15 DIS@ MBK1608121YZF_0603
R5921HDMI@2 0_0402_5%
D22RB751V_SOD323
GND 20GND 21GND 22GND 23
C29512P_0402_50V8J
SQ412N7002W -T/R7_SOT323-3
DIS@
L30MBK1608121YZF_0603
DIS@
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Trang 25HDMI_DET_UMA
HD MI_CLK-_CKHDMI_TX0+_CK
HD MIDAT_RHDMICLK_R
HDMI_TX1+_CKHDMI_TX0-_CK
+3VS
+3VS+3VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
internal pull down
internal pull down
PIN7 PULL DOWN 7.5Kohm PIN7 PULL UP 20Kohm
input output
R428 STUFF RESERVE THE R668 PULL UP TO 3VS FOR asmedia
RESERVE THE R670 PULL DOWN TO GND CHANGE R483 FROM 499 TO 3.4K OHM P/N:SA00003GT00 (ASM1442)
R25320K_0402_1%
GND 12
GND 18GND 24GND 27GND 31GND 36GND 37GND 43
VCC 11VCC 15VCC 21VCC 26VCC 33VCC 40VCC 46
PC1 4PC0 3
OUT_D4+ 13OUT_D4- 14OUT_D3+ 16OUT_D3- 17OUT_D2+ 19
IN_D4+
48IN_D4-47IN_D3+
45IN_D3-44IN_D2+
42IN_D2-41
38
IN_D1-OE#
25
SCL_SINK28SDA_SINK29
HPD_SINK30DDC_EN32
OUT_D2- 20OUT_D1+ 22OUT_D1- 23IN_D1+
39
CFG034CFG135
PAD 49
R2554.7K_0402_5%
@
R245 1 2 UMA_HDMI@3.4K_0402_1%
R2544.7K_0402_5%
UMA_HDMI@
C6020.1U_0402_16V4Z
@
C28510U_0805_10V4Z
UMA_HDMI@
1
2
R2527.5K_0402_1%
@
R2444.7K_0402_5%
UMA_HDMI@
1
2
C2800.1U_0402_16V4Z
@
R2564.7K_0402_5%
@
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