Logic kỹ thuật số thử nghiệm và mô phỏng P10

A func- tional test targets defects within a memory cell, as well as failures that occur whencell contents are altered by a read or write to another cell.. A memory test pattern that tes

Digital Logic Testing and Simulation, Second Edition, by Alexander Miczo

ISBN 0-471-43995-9 Copyright © 2003 John Wiley & Sons, Inc.

com-A typical PC is depicted in the block diagram of Figure 10.1 It is basically amemory hierarchy connected by several buses and adapters and controlled by aCPU The purpose for much of the hierarchy is to combine two or more storage sys-tems with divergent capacities, speeds, and costs such that the combined system hasalmost the speed of the smaller, faster, more expensive memory at almost the cost,speed, and storage capacity of the larger, slower, less expensive memory Clearly,not all storage devices are part of this hierarchy The CDROM may be used todeliver programs and/or data to an end user, and video memory is dedicated to thedisplay console The central processing unit (CPU) accesses many of these auxiliarymemory devices through a peripheral component interconnect (PCI) bus, which reg-ulates the flow of data through the system

Unlike the random logic that has been considered up to this point, memory storagedevices are characterized by a high degree of regularity For example, a semiconductormemory is organized as an array of cells, while storage on a hard drive is organizedinto cylinders This regularity of semiconductor memories permits much greater pack-ing of transistors on die For example, in the PowerPC MPC750, memory accounts for85% of the transistors but only 44% of the die area.1 In the Alpha 21164, 80% of the9.6 million transistors are used for three on-chip caches, but the remaining 20% of thetransistors occupy a majority of the physical die area.2 The various storage devices inFigure 10.1 employ different kinds of circuits for storing and retrieving data, and dif-ferent kinds of media for retaining data, hence they have unique failure mechanisms,requiring different test strategies These memories may also employ varying levels ofredundancy to detect and/or correct errors during operation

514 MEMORY TEST

Figure 10.1 Memory distribution in a typical PC architecture.

Because semiconductor memories are characterized by a high degree of regularity, it

is easy to devise algorithms to test them However, because of the growing capacity

of memories, many of the tests will run for unacceptably long periods of time A nificant problem then, when testing memories, is to identify the kinds of faults thatare most likely to occur and determine the most efficient tests for those faults.Semiconductor memories can be characterized according to the followingproperties:

sig-Serial or random access

Volatile or nonvolatile

Static or dynamic

Destructive or nondestructive readout

Serial access memories are those in which data are accessed in a fixed, mined sequence Magnetic tape units are an example of serial access To read arecord it is necessary to read the entire tape up to the point where the desired dataexists By way of contrast, a random access memory (RAM) permits reading of data

predeter-at any specific locpredeter-ation without first reading other dpredeter-ata When performing a read of aFIFO (first-in, first-out) memory, the first location stored is the first to be read out.These memories act as buffers when transferring data between functional units withdifferent data rates A stack in a computer, often used to save data and returnaddresses, is an example of a LIFO (last-in, first-out) memory The last data pushedonto the stack is the first data to become available when the stack contents arepopped from the stack

CPU LocalBus MemoryBus

Cache controller PCI bridge

Main memory Motionvideo

peripheral

Video memory

SCSI

Host bus

adapter

LAN adapter ISA/EISAbridge

PCI Bus

LAN

CD ROM

Disk Tape

Expansion bus

Graphics adapter

Video frame buffer

Bus master

I/O slave

Memory slave

SEMICONDUCTOR MEMORY ORGANIZATION 515

Figure 10.2 Dynamic memory cell.

Memories can be categorized according to whether or not they can retain mation when power is removed A nonvolatile memory can retain information whenpower is removed Examples of nonvolatile memories include magnetic cores, mag-netic tapes, disks, MROMs, EPROMS, EEPROMS, and flash memories Volatile

infor-memory devices lose information when power is removed

Volatile memories can be further broken down into static and dynamic memories A

static memory retains information as long as power is applied, while a dynamic ory can lose information even when power is continuously applied Static RAMs(SRAMs) are flip-flops that, with their two stable states, can remain in a given stateindefinitely, without need for refresh, as long as power is applied; that is, they are staticbut volatile The dynamic RAM (DRAM), illustrated in Figure 10.2, is an example of adynamic memory The cell is chosen if decoding the memory address causes its word-line to be selected It is basically a capacitor that can either be discharged onto the bit-line or that can be recharged from the bit-line Since it is a capacitor, the charge canleak away over time The memory system must employ refresh circuitry that periodi-cally reads the cells and writes back a suitably amplified version of the signal

mem-If the contents of a memory device are destroyed by a read operation, it is fied as a destructive readout (DRO); otherwise it is a nondestructive readout

classi-(NDRO) device DRAMs must be refreshed when their contents are read out, since aread causes the capacitor to discharge

Programmable read-only memories (PROMs) are slightly more complicated tocharacterize They are static and nonvolatile Mask programmable ROMs and fuseprogrammable ROMs are programmed once and thereafter can only be read.EPROMs (erasable PROMs) can be erased by means of ultraviolet light, whichinvolves physically removing them from the system in which they are installed Forall practical purposes, they are programmed only once because it is quite inconve-nient to erase and reprogram them, unless they are being used to emulate a newdesign for the purposes of debugging that design

EEPROMs (electrically erasable PROMs) can be reprogrammed after beinginstalled in a system, but their response time is slower than DRAMs or SRAMs;hence they are confined to applications where nonvolatility is required Flash memo-ries are structurally almost identical to EPROMs, but they can be reprogrammed in asystem and are more dense than EEPROMs However, EEPROMs can be pro-grammed a bit at a time, whereas flash memories are erased a block at a time beforebeing reprogrammed The Venn diagram in Figure 10.3 illustrates this distribution ofproperties among the various kinds of semiconductor memories.3

read/write select

Data bit

Word-line

516 MEMORY TEST

Figure 10.3 Semiconductor memory properties.

Semiconductor memories usually employ an organization called 2-D In this nization a 2m× 1 memory with m address lines is organized into a matrix with 2N

orga-rows and 2Mcolumns (N + M = m) The address lines are split into two groups suchthat N lines go to a row decoder and M lines go to a column decoder This is illus-trated in Figure 10.4 The row decoder selects 2N memory cells, and the columndecoder selects one of those to be read out of or written into memory This idealizedorganization is the subject of numerous modifications whose purpose is to permitfaster operation and/or faster test One of the more significant changes is the division

of the memory array into several smaller arrays This reduces loading on the bit lines

As we shall see, it also permits multiple cells to be tested simultaneously

Figure 10.4 A semiconductor memory organization.

Dense

volatile

Non- writable

Re-DRAM ROM

EPROM

EEPROM FLASH

MEMORY TEST PATTERNS 517

10.3 MEMORY TEST PATTERNS

In this section some classical, or legacy, memory test algorithms will be examined.Memory test algorithms fall into two categories: functional and dynamic A func- tional test targets defects within a memory cell, as well as failures that occur whencell contents are altered by a read or write to another cell A dynamic test attempts tofind access time failures The All 1s or All 0s tests are examples of functional tests.These tests write 1s or 0s into all memory cells in order to detect individual celldefects including shorts and opens However, these tests are not effective at findingother failure types

A memory test pattern that tests for address nonuniqueness and other functionalfaults in memories, as well as some dynamic faults, is the GALPAT (GALlopingPATtern), sometimes referred to as a ping-pong pattern This pattern accesses eachaddress repeatedly using, at some point, every other cell as a previous address Itstarts by writing a background of zeroes into all memory cells Then the first cellbecomes the test cell It is complemented and read alternately with every other cell

in memory Each succeeding cell then becomes the test cell in turn and the entireread process is repeated All data are complemented and the entire test is repeated Ifeach read and compare is counted as one operation, then GALPAT has an executiontime proportional to 4N2, where N is the number of cells It is effective for findingcell opens, shorts, address uniqueness faults, sense amplifier interaction, and accesstime problems

The following Verilog code illustrates the operation of the GALPAT test First, aRAM module of size “memdepth” × 1 bit is described The RAM model containscode used to insert a stuck-at fault at memory location 27 The RAM model is fol-lowed by a testbench that executes the GALPAT test The line of code that instanti-ates the RAM passes parameters into the RAM from the testbench in order tooverride the RAM size

module ram(addr, datai, datao, wen, oen);

parameter log2_memdepth = 8, memdepth = 256;

input [log2_memdepth−1:0] addr;

input datai, wen, oen;

if (!oen && wen) datao = ramcore[addr];

end

always @(negedge wen)

begin

reg [log2_memdepth−1:0] addr;

reg datain, wen, oen, memval;

for(i = 0; i < memdepth; i = i+1)

for(i = 0; i < memdepth; i = i+1)

$display("Mem Error at loc %d\n", j);

write(e,i); // restore value at loc i

MEMORY TEST PATTERNS 519

input data, adval;

Walking Pattern is similar to the GALPAT except that the test cell is read once

and then all other cells are read To create a Walking Pattern from the GALPAT gram, omit the second read operation in the testbench The Walking Pattern has an

pro-execution time proportional to 2N2 It checks memory for cell opens and shorts andaddress uniqueness

March, like most of the algorithms, begins by writing a background of zeroes.

Then it reads the data at the first location and writes a 1 to that address It continuesthis read/write procedure sequentially with each address in memory When the end

of memory is reached, each cell is read and changed back to zero in reverse order

The test is then repeated using complemented data Execution time is of order N It

can find cell opens, shorts, address uniqueness, and some cell interactions

Galloping Diagonal is similar to GALPAT in that a 1 is moved through memory.

However, it is moved diagonally, checking both row and column decoders

simulta-neously It is of order 4N3 /2 Row and column GALPATs of order 4N3 /2 also exist

Sliding Diagonal (see Figure 10.5) writes a complete diagonal of 1s against a

background of 0s and then, after reading all memory cells, it shifts the diagonal izontally This continues until the diagonal of 1s has passed through all memory

hor-locations The Diagonal test, of order N, will verify address uniqueness at a

signifi-cant speed enhancement over the Walk or GALPAT

Checkerboard Test writes 1s and 0s into alternate memory locations in a

check-erboard pattern After a time delay, which may be several seconds, the pattern is readfrom memory This pattern is used to evaluate data retention in static RAMs

Figure 10.5 The sliding diagonal test.

Surround Read Disturb starts by creating a background of all 0s Then, each

cell in turn becomes the test cell The test cell is complemented and the eight cally adjacent cells are repeatedly read After a number of iterations the test cell isread to determine if it has been affected by the read of its neighbors The operation isthen repeated for a background of 1s The intent is to find disturbances caused byadjacent cell operations Execution time depends on the number of read cycles but is

physi-of the order N.

Surround Write Disturb is identical to the Surround Read Disturb except that a

write rather than a read is performed

Write Recovery writes a background of 0s Then the first cell is established as

the test cell A 1 is written into the second cell and the first (test) cell is read Thesecond cell is restored to 0 and the test cell is read again This is repeated for the testcell and every other cell Every cell then becomes the test cell in turn The entire

process is repeated using complemented data This is an N2 test that is directed atwrite recovery type faults It also detects faults that are detected by GALPAT

Address Test writes a unique value into each memory location Typically, this

could be the address of that memory cell; that is, the value n is written into memory location n After writing all memory locations, the data are read back The purpose

of this test is to check for address uniqueness This algorithm requires that the ber of bits in each memory word equal or exceed the number of address bits

num-Moving Inversions test4 inverts a memory filled with 0s to 1s and conversely.After initially filling the memory with 0s, a word is read Then a single bit ischanged to a 1, and the word is read again This is repeated until all bits in the wordare set to 1 and then repeated for every word in memory The operation is thenreversed, setting bits to 0 and working from high memory to low memory

For a memory with n address bits the process is repeated n times However, on

each repetition, a different bit of the address is taken as the least significant bit forincrementing through all possible addresses An overflow generates an end aroundcarry so all addresses are generated but the method increments through addresses by1s, 2s, 4s, and so on For example, on the second time through, bit 1 (when regardingbit 0 as least significant bit, LSB) is treated as the LSB so all even addresses are gen-erated out to the end of memory After incrementing to address 111 110, the nextaddress generated is address 000 001, and then all consecutive odd addresses are

The Moving Inversions test pattern has 12BN l og2N patterns, where B is the number

of bits in a memory word It detects addressing failures and cell opens and shorts It

is also effective for checking access times

As memories grow larger, with more memory cells packed into an ever-shrinkingdie area, the cost to manufacture a die remains fairly constant, while the time it takes

to apply test programs increases exponentially It is variously estimated that the cost

to test a memory chip runs from 50% to 70% of the total cost of the finished uct.5 The first step in reducing the cost of memory test is to understand what faultmechanisms are most likely to occur and then develop test programs that targetthose faults With this approach, the manufacturer and the end-user can determinetheir priorities, balancing cost versus DPM (defects per million) that they can toler-ate in their applications

prod-A number of different failure types can occur in semiconductor memories, ing memory cell contents, cell addressing, and the time required to read out data.Some of the more common failures include the following:6

affect-Cell opens or shorts

Address nonuniqueness

Cell/column/row disturb sensitivity

Sense amplifier interaction

Slow access time

Slow write recovery

Data sensitivity

Refresh sensitivity

Static data losses

Opens and shorts within semiconductor memory cells may occur because offaulty processing, including misaligned masks or imperfect metallization These

failures are characterized by a general randomness in their nature Opens and shorts

may occur at the chip connections to a printed circuit board In a km × n memory system containing km words of n bits each, and made up of memory chips of size

m × 1, a fault that occurs in bit position i of m consecutive bits is indicative of either

a totally failed chip or one in which an open or short exists between the chip and thePCB on which it is mounted

Address nonuniqueness results from address decoder failures that may eithercause the same memory cell to be accessed by several different addresses or severalcells may be addressed during a single access These failures often cause some cells

to be physically inaccessible An effective test must insure that each read or writeoperation accesses one, and only one, memory cell

Disturb sensitivity between adjacent cells or between cells in the same row orcolumn can result from capacitive coupling Slow access time can be caused by slowdecoders, overloaded sense amplifiers, or an excessive capacitive charge on outputcircuits Slow write recovery may indicate a saturated sense amplifier that cannotrecover from a write operation in time to perform a subsequent read operation

A memory cell can be affected by the contents of neighboring cells Worse still,the cell may be affected only by particular combinations on neighboring cells Thisproblem grows more serious as the distance between neighboring cells shrinks.Refresh sensitivity in dynamic RAMs may be induced by a combination of datasensitivity and temperature or voltage fluctuations Static RAM cells are normallyable to retain their state indefinitely However, data may become lost due to leakagecurrent or opens in resistors or feedback paths

Recall from Section 3.4, when discussing faults in random logic, that fault els other than the stuck-at model were examined The one trait these models had incommon was a susceptibility to combinatorial explosion For very small circuits, thenumber of faults grew so quickly that it was simply not feasible to consider them.Memory circuits, because of their density and the close proximity of cells to oneanother, exhibit this problem of combinatorial explosion to a far greater degree.Hence, it becomes necessary to restrict consideration to faults that are most likely tooccur

mod-The first step is to group the faults into three broad categories: address decoderfaults, memory array faults, and read/write logic faults From there we use the fact,demonstrated by Nair, Thatte, and Abraham,7 that faults in memory addressing andread/write logic, which includes sense amplifiers, write drivers, and other supportinglogic, can be mapped onto functionally equivalent faults in the memory array Thismakes it possible to concentrate on faults in the memory array and to develop testsaddressed at the functionality of the memory array

First consider faults in the address decode logic A fault may cause multiple cells

to be accessed, or no cell may be accessed, or the wrong cell may be addressed Inthe case of multiple cells being addressed, the fault may be viewed as a couplingfault between cells If no cell is addressed, then, depending on the logic, theresponse from the read logic may appear as a stuck-at-1 or a stuck-at-0 If the wrongcell is addressed, then, given the presence of the opposite value in that cell, itappears as a stuck-at fault

MEMORY FAULTS 523

A fault in the read/write logic may cause an output line to be at-0 or at-1 In either case, the corresponding cell may be considered to be stuck-at-0 orstuck-at-1 If there are shorts or capacitive coupling between data input or data out-put lines, these faults can be regarded as coupling between memory cells

stuck-Three conditions, listed below, are defined by Nair et al in order to detect the

faults in their fault model In the conditions, a forced transition is one that occurs as

a result of the test algorithm writing into a cell

Condition 1. Every cell must undergo each of the following two transitions, and must

be read after each transition, before undergoing any subsequent forced transitions.(a) a 0–1 transition and

(b) a 1–0 transition

Condition 2 For every pair of cells (i, j), cell i must be read after cell j makes a forced transition and before cells i and j make any further forced transitions for the following states of cell i and transitions in cell j:

(a) cell i in state 0, cell j making a 0–1 transition,

(b) cell i in state 1, cell j making a 0–1 transition,

(c) repeat a and b with cell j making a 1–0 transition.

Condition 3 For every cell triple (i, j, k), and x, y, z ∈ {0, 1}, if the test makes a

transition in cell j from y to y after cell i makes a transition from x to x and before cell

k in state z is read, then the test must possess another sequence where either:

(a) cell k in state z is read after an x to x transition in cell i and before a y to

Theorem 10.2 The above algorithm is a complete test for the stated memory faultmodel.

The algorithm described above is of order n, denoted O(n), where n is the size of

memory In fact, there are 30 read and write passes through memory, so the

algo-rithm is frequently described as being of complexity 30n In their paper, Nair et al point out that the GALPAT, which is O(n2), does not satisfy all of condition 2 Theythen define a more comprehensive fault model that includes coupling faults, andthey extend the above algorithm to address those faults

10.5 MEMORY SELF-TEST

Memory ICs keep growing larger The cost of manufacturing these ICs remains tively constant as they grow larger, but the cost of testing them increases, becauseevery cell has to be tested for several different kinds of fault mechanisms It waspointed out in the previous section that the cost of testing these large memory ICsoften takes up more than half of the total manufacturing cost

rela-One of the major contributors to test cost for memory ICs is the commercialtesters that are used to test them In addition to the growing size of memories, thespeed at which they operate also continues to increase In order to keep up withmemory IC technology, vendors must constantly upgrade their testers, with a result-ant increase in cost Another problem that must be faced is the inability to accessmany of the memories because they are embedded in ICs, surrounded by randomlogic Gaining access to the address, data and control pins and controlling them withdedicated memory test algorithms is often impossible

As a result of these growing difficulties, memory built-in self-test (MBIST) hasbecome an accepted way to test many memories BIST not only has the ability toaccess embedded memories, but it also has the advantage that it can be designed inconjunction with the memory Thus, architectural features can be incorporated into thedesign to take advantage of the presence of BIST This includes partitioning an internalmemory array into several smaller arrays that can be tested in parallel, thus signifi-cantly reducing total test time Note, however, that fragmentation of memories may be a

MEMORY SELF-TEST 525

disadvantage If a design contains many small memories, the overhead of BIST may

be prohibitive

Another advantage of BIST is its ability to test memory within a system while it

is in operation; hence whenever the system is powered up, the memory can be testedfor defects that may have occurred since the system was last in operation This iscritical in systems that must be failsafe, particularly as there is some concern thatwith technology approaching 0.1 micron; soft errors and noise may become majorproblems.9

10.5.1 A GALPAT Implementation

A generic BIST circuit is depicted in Figure 10.6.10 For memory test the CUT would

be the memory module The BIST must not only generate the data, but must alsocontain circuits to generate memory addresses in some predetermined order Withminor modifications to the diagram, the same test generator could be used to gener-ate the expected response, by way of the control logic, in addition to the test patternsequence In fact, the test generator could generate data to first fill all of memorywith some desired pattern, then the same test generator could generate the expectedresponse simultaneously with reading memory Depending on the algorithm imple-mented by the test generator, this BIST will test for addressing faults as well asmemory faults

The following synthesizable Verilog code implements a BIST circuit, togetherwith testbench, to perform a GALPAT test Note that the GALPAT example inSection 10.3 was executed by the testbench; it would be analogous to application ofGALPAT from a memory tester The reader can experiment with the parameters tosee how the circuit behaves with different memory sizes The circuit is easily modi-fied to perform one of several other memory test algorithms that we will discuss sub-sequently (see the exercises at the end of the chapter) The RAM module, not listedhere, is the same one used previously (Section 10.3) It is easily altered to modelvarious fault mechanisms

Figure 10.6 Generic BIST scheme.

Circuit under test (CUT)

Control logic

Test

Generator

Response monitor

M U X

parameter log2_memdepth = 4, memdepth = 16;

wire [log2_memdepth-1:0] addr;

wire datain, wen, oen, dataout, TC, err_flg;

if(TC) begin // Test Complete

$display(“Algorithm required %d clocks\n”, counter);

parameter log2_memdepth = 8, memdepth = 256;

output [log2_memdepth-1:0] adval;

output testval, wen, oen, err_flg, TC;

input memval, TCLK, T_reset;

reg [log2_memdepth-1:0] j, testcell;

wire [log2_memdepth-1:0] adval;

reg [2:0] GSTATE, GSTATE_next;

reg TC, e, read, write;

wire oen, wen, err_flg, testval;

read = 1; // disable readwrite = 0; // enable writetestcell = testcell+1;

end

`S1: testcell = testcell+1;

`S2: begin // read neighbor

write = 1; // inhibit writeread = (j == testcell) ? 1 : 0;

assign wen = !TCLK | write;

assign oen = !TCLK | read;

assign err_flg = !oen & !read & (memval ^ e);

assign testval = (GSTATE == `S1 || GSTATE == `S3)

? !e : e;

assign adval = (GSTATE == `S2) ? j : testcell;

endmodule

MEMORY SELF-TEST 529

Figure 10.7 State graph for GALPAT.

In this model, corresponding to the state diagram in Figure 10.7, the background is

written during state S0 In state S1 the testcell is chosen and set to the value e Then,

during states S2 and S3 the circuit “ping-pongs” back and forth, alternately readingthe test cell and one of the neighbor cells In S4 the testcell is restored S5 transitions

to S1 if additional memory locations remain to act as testcells If all of the memory

locations have served as test cells, then e ∈ {0,1} is checked to determine if bothvalues have been processed If not, then the state machine transitions from S5 to S6;otherwise it transitions to S7, where it is done

It is instructive to examine the gate count of this circuit as it is synthesized forvarious memory sizes The gate counts will of course vary as a function of theoptions chosen during synthesis, and those will in turn depend on whether the userchooses to optimize for speed or die area But, nonetheless, the gate counts vary inproportion to the number of address bits, rather than to memory size

The GALPAT is impractical, even in BIST form, for all but the smallest ries The problem is not the gate count but, rather, the execution time The circuit

memo-“ping-pongs” between states S2 and S3 for each testcell Hence, ignoring the

back-ground write in state S0, it is of approximate duration (2n)2, where n is the number

of memory cells This is often expressed as O(n2), read as “order of n-squared,”

meaning that computation time is dominated by the square of the number of ory cells This BIST circuit is easily modified to implement a walking pattern, butthe inherent problem of execution time remains

mem-10.5.2 The 9N and 13N Algorithms

A number of BIST circuits have been proposed in the literature, and in each case thekey to successfully defining a memory BIST lies in identifying the fault classes that

S YNTHESIS S IZE FOR GALPAT

Done

are of interest and tailoring an algorithm to address those faults Then, a hardwareimplementation, or BIST, circuit can be designed to implement that algorithm The9N and 13N algorithms will be described here, where N is the number of memorylocations.11 The 13N has been used in the AMD K6 microprocessor.12 Implementa-tion of BIST circuits13 for 9N and 13N is left as an exercise.

Development of the 9N and 13N algorithms began with a study of a number ofspot defects in an 8k × 8 SRAM memory The defects were first translated to defects

in the circuit transistor diagram Then, defects at transistor level were classifiedbased on equivalent faulty memory behavior The result was six fault classes:

1 A cell is stuck-at 0 or stuck-at 1

2 A cell is stuck-open

3 A cell has a transition fault

4 A cell is state coupled to another cell

5 A multiple access fault exists from one memory cell to another

6 A cell has a data retention fault

In their study, the authors found that about 50% of the faults were stuck-at faults.Data retention was the second most common fault, while multiple access faults wereleast common The 13N algorithm is used when the SRAM sense amplifiers include

a data latch The purpose of the latch is to extend the read window of the RAM.However, during testing, this latch can mask the effects of stuck-open faults The 9Nalgorithm is shown to be sufficient to detect all the faults of interest when there is nodata latch

The first five rows in this algorithm constitute the 9N algorithm The inclusion ofthe final four rows extend it to a 13N algorithm The duration of the wait depends

on the node capacitance and leakage current in the memory cells It is proven in theoriginal paper that all of the fault classes of interest are detected by the 9N and/orthe 13N algorithms We will consider here the proof for detection of couplingfaults

Theorem 10.3 The 9N/13N algorithm detects all state coupling faults

MEMORY SELF-TEST 531

Figure 10.8 Cell checking sequence for 9N algorithm.

Proof The test for state coupling is proven by demonstrating that, for any two trary cells, all four binary combinations exist on these two cells, and are checked, atsome point during the test We start by designating two arbitrary cells to be cell1 andcell2 Then, in the state diagram in Figure 10.8, the binary values inside the state cir-cles represent the values on cell1 and cell2 The arc labeled 1/R1 represents step 1,which is a read of cell1 Then, the arc 2/W1 represents a transition to the state (1, 0),and represents a write to cell 1 In that state, the arc 3/R2 represents a read of cell2.The remaining transitions are interpreted similarly The reader can confirm that allcombinations are checked at some point during the algorithm

arbi-10.5.3 Self-Test for BIST

One of the questions that occasionally comes up concerns failures in the BIST cuits What happens if the BIST fails? First, it should be considered that, for largememory arrays, the BIST circuitry is a small percentage of the total die area Con-sequently, the DPM (defects per million) attributable to the BIST should be verysmall One way to further reduce the DPM caused by BIST is to use less aggressivescaling in the BIST circuits so as to realize greater reliability Another approach thatcan further reduce the DPM caused by BIST is to incorporate BIST circuits in theBIST In Section 9.8.2 a self-test feature was described that took advantage ofthe parity of one-hot encoded state machines A large percentage of the defects inthe state machine are immediately detectable by virtue of the fact that they willcause an even number of flip-flops to be turned on A parity check on these flip-flops reveals stuck-at faults not only in the flip-flops, but in the logic that controlsthe state transitions

cir-10.5.4 Parallel Test for Memories

Conceptually, it is inviting to think of a memory as being composed of a single,monolithic array This is in part due to the fact that we usually have no visibility into