1. Trang chủ
  2. » Giáo Dục - Đào Tạo

Modulation and coding course- lecture 10

20 301 0
Tài liệu đã được kiểm tra trùng lặp

Đang tải... (xem toàn văn)

Tài liệu hạn chế xem trước, để xem đầy đủ mời bạn chọn Tải xuống

THÔNG TIN TÀI LIỆU

Thông tin cơ bản

Tiêu đề Convolutional codes
Tác giả Catharina Logothetis
Chuyên ngành Digital communications
Thể loại Lecture
Năm xuất bản 2007
Định dạng
Số trang 20
Dung lượng 119,91 KB

Các công cụ chuyển đổi và chỉnh sửa cho tài liệu này

Nội dung

Today, we are going to talk about:„ Another class of linear codes, known as Convolutional codes.. Convolutional codescoding substantially different from that of block codes.. „ does not

Trang 1

Digital Communications I:

Modulation and Coding Course

Period 3 - 2007 Catharina Logothetis

Lecture 10

Trang 2

Last time, we talked about:

„ Channel coding

„ Linear block codes

Trang 3

Today, we are going to talk about:

„ Another class of linear codes, known as Convolutional codes.

„ We study the structure of the encoder.

„ We study different ways for representing the encoder.

Trang 4

Convolutional codes

coding substantially different from that of block codes

„ A convolutional encoder:

„ encodes the entire data stream, into a single codeword

„ does not need to segment the data stream into blocks of fixed size ( Convolutional codes are often forced to block structure by periodic

truncation ).

„ is a machine with memory.

different nature to the design and evaluation of the code

„ Block codes are based on algebraic/combinatorial

techniques.

„ Convolutional codes are based on construction techniques.

Trang 5

Convolutional codes-cont’d

„ A Convolutional code is specified by

three parameters or

where

number of data bits per coded bit.

assume that from now on

where the encoder has K-1 memory

elements.

„ There is different definitions in literatures for constraint length

) ,

, ( n k K ( k / n , K )

n k

Trang 6

Block diagram of the DCS

Information

source

Rate 1/n

Information

sink

Rate 1/n

4

4 3 4

4 2

1

sequence Input

2

1 , , , , )

=

m

4

4 3 4

4 2 1

4 4

4 4

1

bits) coded ( rd Branch wo 1

sequence

Codeword

3 2 1

, ) , ,

, , (

n

ni ji

i i

i

, ,u , ,u

u U

U U

U U

=

=

= G(m)

U

, ) ˆ

, , ˆ

, ˆ (

m

4 4

4 4

1

d Branch wor per

outputs

1

d Branch wor for

outputs

r Demodulato

sequence received

3 2 1

, ) , ,

, , (

n

ni ji

i i

i

i

, ,z , ,z

z Z

Z Z

Z Z

=

=

Z

Trang 7

A Rate ½ Convolutional encoder

„ 3 shift-registers where the first one takes the

incoming data bit and the rest, form the memory

of the encoder

m

1

u

2

u

First coded bit

Second coded bit

2

1, u

u

(Branch word)

Trang 8

A Rate ½ Convolutional encoder

1

t

1

u

2

u

1 1

2

u

2

t

1

u

2

u

0 1

2

u

3

t

1

u

2

u

0 0

2

u

4

t

1

u

2

u

0 1

2

u

) 101 (

=

m

Message sequence:

Trang 9

A Rate ½ Convolutional encoder

Encoder

) 101 (

=

5

t

1

u

2

u

1 1

2

u

6

t

1

u

2

u

0 0

2

u

Trang 10

Effective code rate

„ Initialize the memory before encoding the first bit (all-zero)

(all-zero)

„ Hence, a tail of zero-bits is appended to data bits.

„ L is the number of data bits and k=1 is assumed:

data tail Encoder codeword

c

K L

n

L

− +

=

) 1 (

Trang 11

Encoder representation

„ Vector representation:

vector for each modulo-2 adder) The i:th element

in each vector, is “1” if the i:th stage in the shift register is connected to the corresponding

modulo-2 adder, and “0” otherwise

„ Example:

m

1

u

2

u

2

1 u u

) 101 (

) 111 (

2

1

=

=

g g

Trang 12

Encoder representation – cont’d

„ Impulse response representaiton:

goes through it

„ Example:

1 1 001

0 1 010

1 1 100

11 10

11 : sequence Output

0 0

1 :

sequence Input

2

u

Branch word Register

contents

11 10

00 10

11

11 10

11 1

00 00

00 0

11 10

11 1

Output

Input m

Modulo-2 sum:

Trang 13

Encoder representation – cont’d

„ Polynomial representation:

modulo-2 adder Each polynomial is of degree K-1 or

less and describes the connection of the shift

registers to the corresponding modulo-2 adder

„ Example:

The output sequence is found as follows:

2 2

) 2 ( 2

) 2 ( 1

) 2 ( 0 2

2 2

) 1 ( 2

) 1 ( 1

) 1 ( 0 1

1

)

(

1

)

(

X X

g X

g g

X

X X

X g

X g

g X

+

= +

+

=

+ +

= +

+

=

g g

) ( ) ( with interlaced

) ( ) ( )

U =

Trang 14

Encoder representation –cont’d

In more details:

11 10

00 10

11

) 1 , 1 ( )

0 , 1 ( )

0 , 0 ( )

0 , 1 ( ) 1 , 1 ( ) (

0

0

0 1 ) ( )

(

0 1

) ( )

(

1 ) 1

)(

1 ( ) ( )

(

1 ) 1

)(

1 ( ) ( )

(

4 3

2

4 3

2 2

4 3

2 1

4 2

2 2

4 3

2 2

1

=

+ +

+ +

=

+ +

+ +

=

+ +

+ +

=

+

= +

+

=

+ +

+

= +

+ +

=

U U

g

m

g

m

g

m

g

m

X X

X X

X

X X

X X

X X

X X

X X

X X

X X

X X

X

X X

X X

X X

X X

Trang 15

State diagram

„ A finite-state machine only encounters a finite number of states

„ State of a machine: the smallest amount

of information that, together with a

current input to the machine, can predict the output of the machine.

„ In a Convolutional encoder, the state is represented by the content of the

memory.

„ Hence, there are states.1

2K

Trang 16

State diagram – cont’d

„ A state diagram is a way to represent

the encoder

„ A state diagram contains all the states and all possible transitions between

them.

„ Only two transitions initiating from a

state

„ Only two transitions ending up in a state

Trang 17

State diagram – cont’d

00

11

output

Next state

input

Current state

01 0

01 1

10

0 10

00 1

11

0 01

11 1

00

0

000

S

1

S

2

S

S

0

S

2

S

0

S

2

S

1

S

3

S

1

S

0

S

1

S

2

S

3

S

1/11

1/00

1/01

0/11 0/00

0/01 0/10

Input

Output (Branch word)

Trang 18

Trellis – cont’d

diagram that shows the passage of time.

Time

i

State

00

0 =

S

01

1 =

S

10

2 =

S

11

3 =

S

0/00

1/10

0/11

0/10 0/01

1/11

1/01

1/00

Trang 19

Trellis –cont’d

0/11

0/10 0/01

1/11

1/01

1/00

0/00

0/11

0/10 0/01

1/11

1/01 1/00

0/00

0/11

0/10 0/01

1/11

1/01 1/00

0/00

0/11

0/10 0/01

1/11

1/01 1/00

0/00

0/11

0/10 0/01

1/11

1/01 1/00

0/00

Input bits Output bits

Tail bits

Trang 20

Trellis – cont’d

1/11

0/00

0/10 1/11

1/01

0/00

0/11

0/10 0/01

1/11

1/01 1/00

0/00

0/11

0/10 0/01

0/00

0/11 0/00

6

t

1

Input bits Output bits

Tail bits

Ngày đăng: 25/10/2013, 06:15

TỪ KHÓA LIÊN QUAN

w