Expanding Memory and I-O

The mode set pins MD0, MD1 and MD2 are used to select one of seven operating modes, which determine the uses of the address bus, data bus and read/write signals.. Table 13.2: Pins Relati

Chapter 13 Expanding Memory and I/O

Since the H8/3048 has a 128kbyte internal ROM and an 8kbyte internal RAM, it can accommodate a relatively large program without externally expanding the memory If the internal memory is insufficient, however, you can externally expand it, which is essential for hardware design engineers to know Although software engineers can still develop programs without this knowledge, they are also expected to understand some of the basic techniques

Although the H8/3048 can accommodate a dynamic RAM, this chapter focuses on the basic functions and describes the ROM and static RAM

In this chapter, you learn about which signals are required for expanding the memory, how they change at reading/writing and how to calculate if the CPU and memory speed match This chapter also helps you understand memory signals and timings

Note: The following are negative logic signals:

Although the H8/3048 has an internal ROM and RAM, external memory expansion may be required due to insufficient capacity The following describes how to connect the memory and CPU and match their speeds using EPROM and SRAM as examples

13.1 H8/3048 Operating Mode

When expanding the H8/3048 memory, you can determine how much memory capacity to be added and how to use the data bus The mode set pins (MD0, MD1 and MD2) are used to select one of seven operating modes, which determine the uses of the address bus, data bus and read/write signals

Table 13.1 shows each mode:

* Status at resetting It is available as either an 8- or 16-bit bus according

to the setting

Since mode 7 represents single-chip mode, no external memory can be added

Table 13.1: H8/3048 Operating Mode

The internal ROM and RAM are always connected to the CPU through the 16-bit data bus irrespective of the mode setting "Disabled" in the "Internal ROM" column means that the internal ROM, though it exists, is disabled by being disconnected from the CPU In this case, an external ROM must be connected When the internal ROM and RAM are enabled, no external memory can be added to the same address If the same address is used, the internal memory has priority, disabling reading/writing from/to the externally connected memory

13.2 Pins for Memory Connection

Table 13.2 shows the pins relating to memory connection provided for the H8/3048 and their functions

Connected memory size

Since there are 24 address buses (A0 to A23), up to 16Mbytes of memory can be connected If the memory to be connected is 1Mbyte or smaller, only 20 address buses (A0 to A19) are required and the remaining 4 pins can be used for other purposes

Data bus width

Since the H8/300H is a 16-bit CPU, it has 16 pins (D0 to D15) for reading and writing 16-bit data If word data is allowed to be divided into two

by the MOV.W instruction, only 8 data bus pins (D8 to D15) are required and the remaining 8 pins (D0 to D7) can be used for other purposes

As described above, the use of pins determines whether the memory address is 16M or 1M and the data bus is either 16 or 8 bits So you have to figure out the most effective use with the limited number of pins

Table 13.2: Pins Relating to Memory Connection

Address strobe

Indicates that an address is valid and that it is external when it is at low level It is not set at low level if an address is internal (internal ROM or RAM) When the CPU is reading or writing data from/to the internal ROM or RAM, reading/writing is not available externally The RD, HWR and LWR signals are not changed to low level, either

Read/write signals

When the data bus width is 8 bits (RD and HWR are used):

Data buses D8 to D15 are used, and D0 to D7 are not

When the data bus width is 16 bits (RD, HWR and LWR are used):

The RD signal is used as the read signal for both 8- and 16-bit widths, the HWR signal is used for writing to an even-numbered address, and the LWR signal is used for writing to an odd-numbered address During 16-bit data writing, both the HWR and LWR signals are output For details, refer to the section describing connection between the CPU and memory

[Explanation with motion pictures and sound]

13.3 Read Timing from External Memory

Figure 13.1 shows the read timing from an external memory This is an example for 24-bit address and 16-bit data buses Reading is completed in a 3-system clock time (3-state access)

To read data or instructions from the memory, the setup time and hold time of the read data must be satisfied

Figure 13.1: Read Timing from External Memory

13.4 Write Timing to External Memory

Figure 13.2 shows the write timing to an external memory This is an example for 24-bit address and 16-bit data buses

Writing is completed in a 3-system clock time (3-state access)

Figure 13.2: Write Timing to External Memory

Figure 13.3 shows the read/write timings including waits If the WAIT input is at low level at the trailing edge of T2, the CPU inserts a wait state to slow reading/writing When the WAIT input is returned to high level, reading/writing is completed

Depending on the address output by the CPU, users have to design circuits to input WAIT signals if the memory connected to the address is slow,

or to prevent WAIT signals from being input if it is fast

The H8/3048 is provided with a wait state controller so that the wait state can

be input without creating such circuits

Figure 13.3: Read/Write Timings Including Waits

Since the H8/3048 has an internal wait controller, waits can be inserted

in various ways

Wait state controller enable register (WCER)

Determines for which area the wait state controller is enabled from area

0 to area 7

WCER H'FFFFEF address

Figure 13.4: Wait State Controller Enable Register (WCER)

The wait state controller is enabled for the area with "1" written and disabled for that with "0" By default, it is enabled for all areas

Wait control register

Determines how to insert waits for the wait-enabled area

WCR H'FFFFEE address

Figure 13.5: Wait Control Register (WCR)

Wait mode select 1 and01 (WMS1 and WMS0)

Programmable wait mode

Without using the WAIT pin, forcibly inserts the wait set by the wait count

Pin wait mode 1

Waits for the wait cycle specified by the program and inserts an additional wait depending on the WAIT pin status (Figure 13.3)

Pin auto wait mode

The WAIT signal input to the WAIT pin only determines whether to insert a wait state or not, and how many states to be inserted is determined by the wait count Wait is inserted as necessary

Wait count 1 and01 (WC1 and WC0)

This determines how many wait states to be inserted in a programmable wait or pin auto wait mode

By default, the wait controller is enabled for all areas and three states are set to be inserted in programmable wait mode In other words, three wait states are forcibly inserted in all areas Change the setting as soon as possible after resetting if necessary

13.5 Sample Memory (EPROM)

The HN27C4001G is used here as an EPROM example

The HN27C4001G has a 4Mbit capacity and 524288 word × 8 bit configuration Figure 13.6 shows the pin assignment

Figure 13.6: NH27C4001G Pin Assignment Diagram

There are 19 address input pins, A0 to A18.Since addresses are input in 19-bit units, this memory has 512-kbyte (to be more precise, 524,288)

addresses The address count of the memory IC is determined by the address pin count

There are 8 data pins, I/O0 to I/O7, meaning that the memory uses 8 bits per address Since this is a ROM, it is a read only memory when connected

to a CPU and the data pins are set to output They are changed to input pins for writing by an EPROM writer Here, we consider the case in which it is

connected to a CPU and serves as a ROM only

The Vpp pin is designed to apply the write voltage (12V) for writing by

an EPROM writer It is fixed to high or low level for operation as a ROM with connection to a CPU

CE (Chip Enable) is a memory select signal and the memory is selected when it is set at low level This is used to assign a specific address by adding

an address-decoded signal

OE (Output Enable) is an output enable signal and read data is output from a data pin when it is set at low level

The table below summarizes this

In read mode, the CPU reads data from the EPROM and sets both CE and OE at low level

In output disable mode, the memory is selected but read data is not output to an I/O pin The I/O pin is set in high impedance mode (disconnected state)

In standby mode, the memory is not selected When CE is set at high level, the system is set in standby mode irrespective of the OE setting Since the memory IC is not operating in this mode, power consumption is low

Table 13.3 shows the HN27C4001G read timing There are 100ns and 120ns types

Table 13.3: HN27C4001G Read Timing

Read timing waveform

Figure 13.7 shows the HN27C4001G read timing

Read data is output from an I/O pin when the access time (tACC), CE output delay time (tCE) and OE output delay time (tOE) are satisfied

Figure 13.7: Read Timing Waveform

13.6 Sample Memory (SRAM)

The HM628512BI is used here as a static RAM example It has a 4Mbit memory capacity and 524288 word × 8 bit configuration Figure 13.8 shows the pin assignment

Figure 13.8: HN628512BI Pin Assignment

There are 19 address pins, using 512 kbytes, and 8 data pins, using 8 bits per address

CS (Chip Select) is a memory select signal and is the same as CE of the EPROM The memory is selected when it is set at low level This is used to assign a specific address by adding an address-decoded signal

OE (Output Enable) is an output enable signal and read data is output from a data pin when it is set at low level The function and name are the same

as for OE of the EPROM

Writing is enabled when WE (Write Enable) is set at low level Table 13.4 summarizes this

Table 13.4: HM628512BI Modes

In read mode, the CPU reads data from the SRAM and sets both CS and

OE at low level

In output disable mode, the memory is selected but read data is not output to an I/O pin The I/O pin is set in high impedance mode (disconnected state)

Write operation takes two forms When CS is set at low to set WE at low, OE is capable of writing at either high or low Writing with OE set at high

is called the "OE clock" mode since it is set at low for reading and high for writing Writing with OE set at low, on the other hand, is called the "OE low fixed" mode since it is set at low for both reading and writing Writing is generally conducted in OE clock mode

In non-selection mode, the memory is not selected When CS is set at high, the system is set in non-selection mode irrespective of the OE or WE setting Since the memory IC is not operating in this mode, power consumption

is low

Table 13.5 shows the HM628512BI read cycle There are 70ns and 80ns types

Table 13.5: HM628512BI Read Cycle

Read cycle timing

Figure 13.7 shows the read timing waveform Read data is output to an I/O pin when the address access time (tAA), chip select access time (tCO) and output enable access time (tOE) are satisfied

Figure 13.9: Read Timing Waveform

Table 13.6 shows the HM628512BI write cycle

Table 13.6: HM628512BI Write Cycle

Figure 13.10 shows the write cycle waveform of the OE clock

The important parameters for the write timing are input data set time (tDW) and input data hold time (tDH)

Writing is conducted at either the CS or WE leading edge, whichever is earlier The input data set time (tDW) and input data hold time (tDH) must be satisfied for this write timing

Figure 13.10: Write Cycle Waveform (OE Clock)

13.7 Connecting CPU to Memory(Connecting EPROM Using 8-bit Data Bus)

The following conditions are assumed here for connecting a CPU to a memory:

CPU: H8/3048F (clock frequency: 10MHz) 16Mbyte memory space (24 address pins) Internal ROM disabled (internal ROM is not used but an EPROM is connected externally)

8-bit data bus (D8 to D15 used)

RD, HWR and CS0 to CS7 are used as control signals

Memory: HN27C4001G-10 for EPROM (access time: 100ns) HM628512BI-8 for SRAM (access time: 85ns) First, let's consider how to connect a CPU to a memory using an 8-bit data bus

must be connected between H'000000 and H'01FFFF The internal ROM is assumed to be disabled here

Generally, a memory is assigned to one of the spaces obtained by equally dividing the CPU memory space by the memory capacity Since the CPU memory space is 16Mbytes and the EPROM capacity is 512kbytes, the CPU memory space is divided into 32 equal parts The smallest addresses are from H'000000 to H'07FFFF This is shown in Figure 13.11

Figure 13.11: Address Assignment

Next, let's develop an address decode circuit The EPROM should be designed to operate only when the address output by the CPU is the EPROM address (from H'000000 to H'07FFFF) and operation is enabled only when the

CE pin of the EPROM is set at low level The address decode circuit is designed to set CE at low level when the address output by the CPU is the EPROM address

Then, how can you determine that the address output by the CPU is the EPROM address? The EPROM address is represented as follows in binary notation:

H'000000: 0000 0000 0000 0000 0000 0000 H'07FFFF: 0000 0111 1111 1111 1111 1111

Accordingly, you can determine that it is the EPROM address when the upper 5 bits (A23 to A19) of the address are all 0 On the other hand, you can determine that the address of the address bus is valid when AS is set at low level As a result, CE of the EPROM is set at low level under the following conditions:

AS is at low level and A23 to A19 are also at low level Figure 13.12 shows a sample circuit to satisfy them

Figure 13.12: Address Decode Circuit

The more memories that are connected, the harder it is to develop decoders as shown above for each memory By using the HD74AC138, a standard logic IC, you can develop select signals for 8 memories Figure 13.11 shows the HD74AC138 pin assignment and truth values are shown in Table 13.7

Figure 13.13: HD74AC138 Pin Assignment

Table 13.7: HD74AC138 Truth Value Table

Table 13.8 shows the AC characteristics

Table 13.8: AC Characteristics of HD74AC138

A decode circuit using the HD74AC138 is shown in Figure 13.14

Figure 13.14: Decode Circuit Using HD74AC138

Figure 13.15 shows connection between H8/3048 and HN27C4001G

Figure 13.15: Connection Between CPU and EPROM

The memory address pins are connected to the corresponding address pins of the CPU (A0 to A0, A1 to A1, etc.) from A0 to A18

The memory data pins are connected to the corresponding data pins of the CPU (I/O0 to D8, I/O1 to D9, etc.) from I/O0 to I/O7, to D8 to D15

Address-decoded signals are input to the memory CE pin

RD signals of the CPU are input to the memory OE pin When the CPU

is in read mode, the RD signal and OE are set at low and reading starts

This completes logical connection between the CPU and the memory Next, it must be calculated whether the speeds of the CPU and the memory match Since an EPROM is connected, the CPU read timings are calculated here

Figure 13.16 shows CPU timings required for calculation