VHDL1 ebook,VHDL tutorial

Conversely, an existing technology-dependent gate-level description such as a netlist can be read by Design Compil-er, then written out as a technology-independent VHDL description by VH

About This Manual i

Audience i

Manual Contents ii

Conventions v

Synopsys Products vi

1 Design Process 1–1

Hardware Description Languages 1–3 Typical Uses for HDLs 1–3 Advantages of HDLs 1–4 About VHDL 1–5 About VHDL Compiler 1–8 Using VHDL Compiler with Design Compiler 1–9

A Model of the Design Process 1–10 VHDL Example 1–13 Design Problem 1–13 VHDL Design Description 1–14 Synthesizing the VHDL Design 1–16

2 Description Styles 2–1

Design Hierarchy 2–2 Data Types 2–3 Design Constraints 2–4 Register Selection 2–4 Asynchronous Designs 2–5 Language Constructs 2–6

VHDL Compiler, a member of the Synopsys HDL Compiler family,translates and optimizes a VHDL description to an internal

gate-level equivalent This representation is then compiled withthe Synopsys Design Compiler Family to produce an optimizedgate-level design in a given ASIC technology

Conversely, an existing technology-dependent gate-level

description (such as a netlist) can be read by Design

Compil-er, then written out as a technology-independent VHDL

description by VHDL Compiler This translation capability is

called reverse synthesis; it provides a powerful means of

leveraging existing designs

To work with VHDL, familiarize yourself with the following

concepts:

Hardware Description Languages About VHDL

About VHDL Compiler Using VHDL Compiler with Design Compiler

A Model of the Design Process VHDL Examples

Design Problem VHDL Design Description Synthesizing the Example VHDL Design

The United States Department of Defense, as part of its High-Speed Integrated Circuit (VHSIC) program, developed

Very-VHSIC HDL (VHDL) in 1982 VHDL describes the behavior,

function, and inputs and outputs of a digital circuit design.VHDL is similar in style and syntax to modern programming

languages, but includes many hardware-specific constructs.Appendix A contains sample VHDL designs, with schematics

of their synthesized circuits

VHDL Compiler reads and parses the supported VHDL syntax.Appendix C lists all VHDL constructs with the level of Synopsyssupport for each

Hardware Description Languages

Hardware description languages (HDLs) are used to describethe architecture and behavior of discrete electronic systems.HDLs were developed to deal with increasingly complex

designs An analogy is often made to the history of what can

be called software description languages, from machine

code (transistors and solder), to assembly language (netlists),

to high-level languages (HDLs)

Top-down, HDL-based system design is most useful in large

projects, where several designers or teams of designers areworking concurrently HDLs provide structured development.After major architectural decisions have been made, and

major components and their connections have been fied, work can proceed independently on subprojects

identi-Typical Uses for HDLs

HDLs typically support a mixed-level description where tural or netlist constructs can be mixed with behavioral or

struc-algorithmic descriptions With this mixed-level capability, youcan describe system architectures at a high level of abstrac-tion; then incrementally refine a design into a particular

component-level or gate-level implementation Alternatively,you can read an HDL design description into the Synopsys

Design Compiler, then direct the compiler to synthesize a

gate-level implementation automatically

Advantages of HDLs

A design methodology that uses HDLs has several tal advantages over a traditional gate-level design method-ology Among the advantages are the following:

fundamen-
You can verify design functionality early in the designprocess, and immediately simulate a design written as

an HDL description Design simulation at this higher level,before implementation at the gate-level, allows you totest architectural and design decisions

By using VHDL Compiler with Synopsys’ logic synthesis,

you can automatically convert a VHDL description to agate-level implementation in a given technology Thismethodology eliminates the former gate-level designbottleneck and reduces circuit design time and errorsintroduced when hand-translating a VHDL specification

to gates With Synopsys’ logic optimization, you can

automatically transform a synthesized design to a

small-er or fastsmall-er circuit You can apply information gainedfrom the synthesized and optimized circuits back to theVHDL description, perhaps to fine-tune architecturaldecisions Synopsys Design Compiler, which is described

in the , provides logic synthesis and optimization.

HDL descriptions provide technology-independentdocumentation of a design and its functionality An HDLdescription is more easily read and understood than anetlist or schematic description Since the initial HDLdesign description is technology-independent, you canlater reuse it to generate the design in a different

technology, without having to translate from the original

VHDL, like most high-level software languages, provides

strong type checking A component that expects a

four-bit-wide signal type cannot be connected to athree- or five-bit-wide signal; this mismatch causes anerror when the HDL description is compiled If a vari-able’s range is defined as 1 to 15, an error results fromassigning it a value of 0 Incorrect use of types has beenshown to be a major source of errors in descriptions Typechecking catches this kind of error in the HDL descriptioneven before a design is generated

About VHDL

VHDL is one of just a few HDLs in widespread use today VHDL

is recognized as a standard HDL by the IEEE (IEEE Standard

1076, ratified in 1987) and by the United States Department ofDefense (MIL–STD–454L)

VHDL divides entities (components, circuits, or systems)

be-tween an external or visible part (entity name and tions) and an internal or hidden part (entity algorithm and

connec-implementation) After you define the external interface to

an entity, other entities can use that entity when they all arebeing developed This concept of internal and external views

is central to a VHDL view of system design An entity is

de-fined, with respect to other entities, by its connections and

behavior You can explore alternate implementations tectures) of an entity without changing the rest of the design.

(archi-After you define an entity for one design, you can reuse it inother designs as needed You can develop libraries of entitiesfor use by many designs, or for a family of designs

The VHDL model of hardware is shown in Figure 1–1

Figure 1–1 VHDL Hardware Model

A VHDL entity (design) has one or more input, output, or

input-output ports that are connected (wired) to neighboring

systems An entity is itself composed of interconnected

enti-ties, processes, and components, all which operate rently Each entity is defined by a particular architecture,

concur-which is composed of VHDL constructs such as arithmetic,

signal assignment, or component instantiation statements

In VHDL, independent processes model sequential (clocked)

circuits, such as flip-flops, and combinational (unclocked)

circuits, such as AND or XOR gates Processes can define and

call (instantiate) subprograms (subdesigns) Processes municate with each other by signals (wires).

com-A signal has a source (driver), one or more destinations ers), and a user-defined type, such as “color” or “number

ab-VHDL language constructs are divided into three categories

by their level of abstraction: behavioral, dataflow, and tural These categories are described as follows:

struc-behavioral

The functional or algorithmic aspects of a design, pressed in a sequential VHDL process

ex-dataflow

The view of data as flowing through a design, from input

to output An operation is defined in terms of a tion of data transformations, expressed as concurrentstatements

collec-structural

The view closest to hardware; a model where the ponents of a design are interconnected This view isexpressed by component instantiations

com-About VHDL Compiler

VHDL Compiler converts VHDL source code to an internal

format used by the Synopsys Design Compiler VHDL Compiler

is accessed in dc_shell or Design Analyzer by executing

elaborate and analyze VHDL Compiler performs two

func-tions: translating VHDL to an internal format, and optimizingthe block level representation through various optimizationmethods

Design Compiler reads the design in internal format from

VHDL Compiler, then optimizes and maps the design’s logicalstructure for a specific ASIC technology library, as shown inFigure 1–2.

Figure 1–2 VHDL Compiler Used with VHDL System Simulator (VSS)

and Design Compiler

VHDL System Simulator

(functionality verification)

A VHDL description is first simulated to verify design ality, by using a VHDL simulator such as the Synopsys VSS

function-Family (VSS Expert or VSS Professional)

When analyzing VHDL design files for simulation you can use

vhdlan –spc to verify Synopsys synthesis policy For more

information, refer to the chapter on the VHDL Analyzer in the

or the

VHDL Compiler is called by Design Compiler when you read

in or write out a VHDL design VHDL Compiler synthesizes

VHDL descriptions according to the VHDL synthesis policy

defined in Chapter 2, “Description Styles.”

The Synopsys VHDL synthesis policy has three parts: design

methodology, design style, and language constructs You usethe VHDL synthesis policy to produce high quality VHDL-

based designs

Using VHDL Compiler with Design Compiler

When VHDL Compiler reads a VHDL design, the design is

converted to Design Compiler’s internal database format

When Design Compiler performs logic optimization on a

design, Design Compiler can restructure part or all of the

design You control the degree of restructuring You can keep

a design hierarchy intact, move modules up or down the

design hierarchy, combine modules, or compress the entiredesign into one module

After you are in Design Compiler, you can write out any

design in a variety of formats, including VHDL Existing level netlists, sets of logic equations, or technology-specificcircuits can be automatically converted to a VHDL descrip-tion The new VHDL description can serve as documentation

gate-of the original design, and you can use it as a starting pointfor reimplementation into a new technology In addition, youcan give the VHDL description to a VHDL simulator to providecircuit timing information

A Model of the Design Process

An example of a VHDL design session is described below

Starting with a VHDL description (source file), the example

shows how to execute Design Compiler, read in and optimize

a design, view its schematic, and write out the optimized

circuit description

Figure 1–3 illustrates a typical design flow that uses VHDL

Compiler, Design Compiler, and your VHDL simulator

Figure 1–3 Design Flow that Uses VHDL Compiler

VHDL Description

VHDL Simulator

Synopsys VHDL Compiler

Synopsys Design Compiler

VHDL Driver

VHDL Level Description

VHDL Simulator

Simulation Output

Simulation Output

Compare Output

1

2

4

7 3

5

6

8

The steps in Figure 1–3 are explained below

1 Write a design description in the VHDL language Thisdescription can be a combination of structural andfunctional elements (as shown in Chapter 2, “DescriptionStyles”) This description is used with both the SynopsysVHDL Compiler and your VHDL simulator

2 Provide VHDL-language test drivers for your VHDL tor These drivers supply test vectors for the simulationand gather output data.

simula-3 Simulate the design by using your VHDL simulator toverify the accuracy of the description

4 Synthesize the VHDL description with VHDL Compiler

VHDL Compiler performs architectural optimizations,then creates an internal representation of the design

5 Use the Synopsys Design Compiler to produce an mized gate-level description in the target ASIC library.You can optimize the generated circuits to meet thetiming and area constraints you want This optimizationstep must follow the translation step (step 4) to produce

opti-an efficient design

6 Use the Synopsys Design Compiler to output a gate-levelVHDL description This netlist-style description uses ASICcomponents as the leaf-level cells of the design Thegate-level description has the same port and moduledefinitions as the original high-level VHDL description

7 Pass the gate-level VHDL description from step 6 throughyour VHDL simulator You can use the VHDL simulationdrivers from Step 2 because module and port definitionsare preserved through the translation and optimizationprocesses

8 Compare the output of the gate-level simulation (step 7)against the output of the original VHDL description

simulation (step 3) to verify that the implementation iscorrect

VHDL Example

The example that follows is called “Count Zeros—SequentialVersion,” and is taken from Appendix A The next three sec-tions contain

A description of the design problem (count the number

of zeros in a sequentially input eight-bit value)

A listing of a VHDL design description

A step-by-step description of how to read in the VHDLdesign description, how to compile (synthesize) the circuit,how to view the resulting schematic, and how to write outthe synthesized circuit description as a VHDL file

Design Problem

The Count Zeros example illustrates a design problem where

an eight-bit value is given and the circuit determines

Exactly one sequence of 0s is in the value

The number of 0s in that sequence (if any)

A valid value can have no more than one series of tive zeros A value consisting entirely of 1s is defined as a validvalue If a value is invalid, the zero counter is reset to zero Forexample, value 00000000 is valid and has eight zeros; value

consecu-11000111 is valid and has three zeros; value 00111100 is not

valid

The circuit accepts the eight-bit data value serially, one bitper clock cycle, by using the DATA and CLK inputs The othertwo inputs are

RESET, which resets the circuit (synchronous reset)

READ, which causes the circuit to begin accepting databits and continue to accept data bits

The circuit’s three outputs are

IS_LEGAL, which is TRUE if the data was a valid value

COUNT_READY, which is TRUE at the first invalid bit or whenall eight bits have been processed

COUNT, the number of zeros (if IS_LEGAL is TRUE) The outputport COUNT is declared with mode BUFFER, so that it can

be read inside the process OUT ports can only be written

to, not read

Note:

The pathname of the VHDL source file for this example is

/synopsys/doc/syn/examples/vhdl/cnt–seq/cnt–seq.vhd,where /synopsys is the name of your Synopsys rootdirectory

architecture BEHAVIOR of COUNT_SEQ_VHDL is

begin

process

variable SEEN_ZERO, SEEN_TRAILING: BOOLEAN;

variable BITS_SEEN: INTEGER range 0 to 7;

begin

wait until CLK’event and CLK = ’1’;

if (RESET) then

COUNT_READY <= FALSE;

IS_LEGAL <= TRUE; –– Signal assignment

SEEN_ZERO := FALSE; –– Variable assignment

end if; –– if (READ)

end if; –– if (RESET)

end process;

end BEHAVIOR;

Synthesizing the VHDL Design

To synthesize a circuit from the VHDL design example, use

Design Analyzer and follow these steps:

1 Start Design Analyzer by entering the following mand at your UNIX prompt (%):

2 Set your target library and the associated link and bol libraries For this example, use the generic Synopsys

sym-class library Move the cursor to Setup, then click the leftmouse button to bring up the Setup menu Click on

Defaults to bring up the Setup/Defaults dialog

Add the Synopsys-supplied library directory name / synopsys/libraries/syn to the end of the Search Path

field Set the Link Library, Target Library, and Symbol Library fields as shown in Figure 1–5 Click on OK to setthese default values

Figure 1–5 Setup/Defaults Window

Click on Cancel to remove the Variables dialog

3 Analyze the VHDL source file; use the File/Analyze

dialog

Enter the directory name /synopsys/doc/syn/examples/ vhdl/cnt–seq/ in the File Name field and click on OK AnAnalyze window appears with a design_analyzer

prompt

Click on CANCEL

4 Elaborate the VHDL source file by using the rate dialog The Elaborate Design window appears

File/Elabo-Enter the library name WORK in the Library field

Enter the design name COUNT_SEQ_VHDL (BEHAVIOR) in theDesign field Click OK

An Elaborate window opens to show the status sages and inferred devices (see “Register and Three-State Inference” in Chapter 8) produced by VHDL Com-piler.

mes-After you have reviewed the VHDL report, click on Cancel

to remove the report window

5 The design has now been read into memory and lated to an internal (equation-based) format, indicated

trans-by the symbol Y=A+B The Design Analyzer window nowshows the design’s icon and name (COUNT_SEQ_VHDL)

6 Click on the design icon to select it, then click on thedown-arrow button (left side of window) to generateand display the symbol view of the design.

7 Set a constraint for the design Ask for the minimum area

by using the Attributes/Optimization sign Constraints selection

Constraints/De-The Design Constraints dialog box appears

Click Apply then Cancel

8 Look at the initial (HDL-level) schematic Click on theschematic view icon.

9 You can see the ports and gates produced by VHDLCompiler from the VHDL description by using HDL Advi-

sor For more information, see the HDL Advisor User Guide.

10.Compile the design by using the Tools/Design tion dialog Use the default settings and click on OK tostart the compilation.

Optimiza-Delay

A Compile Log report window shows the compilationstatus After you review the report, click on Cancel toremove the window.

11.Display the schematic for the design by clicking on the

Schematic View button (small AND gate)

At this point, you can explore the design by using DesignAnalyzer You can see the critical path, get timing in-formation, highlight all cells or references of a giventype, change circuit constraints, group and ungroupsubsets of the circuit, and get a variety of reports Seethe for complete information

12.Write out the design by using the File/Save As dialog.Enter the new filename in the File Name field, for exam-ple, example.vhdl Choose the output format you wantfrom the File Format list; in this case, VHDL netlist outputformat.

13.Quit Design Analyzer by using the File/Quit dialog.

Click on OK to exit Design Analyzer, or Cancel to removethis dialog The screen is locked when this dialog isdisplayed

Architectures 3–7 Configurations 3–9 Processes 3–9 Subprograms 3–11 Packages 3–11 Using a Package 3–12 Package Structure 3–13 Package Declarations 3–13 Package Bodies 3–15 Defining Designs 3–16 Entity Specifications 3–16 Entity Generic Specifications 3–17 Entity Port Specifications 3–18 Entity Architectures 3–19 Entity Configurations 3–23 Subprograms 3–24 Subprogram Declarations 3–25 Subprogram Bodies 3–27 Subprogram Overloading 3–28 Operator Overloading 3–29 Type Declarations 3–30 Subtype Declarations 3–30 Constant Declarations 3–31 Signal Declarations 3–31 Resolution Functions 3–32 Variable Declarations 3–36 Structural Design 3–36 Using Hardware Components 3–37 Component Declaration 3–38 Sources of Components 3–39 Consistency of Component Ports 3–40

4 Data Types 4–1

Enumeration Types 4–3 Enumeration Overloading 4–4 Enumeration Encoding 4–4 Enumeration Encoding Values 4–7 Integer Types 4–8 Array Types 4–9 Constrained Array 4–9 Unconstrained Array 4–10 Array Attributes 4–11 State Vector Attributes 4–13 Record Types 4–17 Predefined VHDL Data Types 4–18 Data Type BOOLEAN 4–20 Data Type BIT 4–20 Data Type CHARACTER 4–20 Data Type INTEGER 4–21 Data Type NATURAL 4–21 Data Type POSITIVE 4–21 Data Type STRING 4–21 Data Type BIT_VECTOR 4–21 Unsupported Data Types 4–22 Physical Types 4–22 Floating Point Types 4–22 Access Types 4–22 File Types 4–22 SYNOPSYS Data Types 4–22 Subtypes 4–23

5 Expressions 5–1

Operators 5–3 Logical Operators 5–5 Relational Operators 5–7

Adding Operators 5–10 Unary (Sign) Operators 5–12 Multiplying Operators 5–13 Miscellaneous Arithmetic Operators 5–16 Operands 5–17 Operand Bit Width 5–18 Computable Operands 5–18 Literals 5–21 Numeric Literals 5–21 Character Literals 5–22 Enumeration Literals 5–22 String Literals 5–23 Identifiers 5–25 Indexed Names 5–26 Slice Names 5–28 Limitations on Null Slices 5–30 Limitations on Noncomputable Slices 5–30 Records and Fields 5–31 Aggregates 5–32 Attributes 5–34 Function Calls 5–35 Qualified Expressions 5–36 Type Conversions 5–38

6 Sequential Statements 6–1

Assignment Statements 6–3 Assignment Targets 6–4 Simple Name Targets 6–4 Indexed Name Targets 6–5 Slice Targets 6–7 Field Targets 6–8

Variable Assignment 6–11 Signal Assignment 6–12

if Statement 6–14 Evaluating condition 6–14 Using the if Statement to Imply Registers and Latches 6–15 case Statement 6–16 Using Different Expression Types 6–17 Invalid case Statements 6–19 loop Statements 6–20 loop Statement 6–22 while loop Statement 6–22 for loop Statement 6–23 next Statement 6–27 exit Statement 6–29 Subprograms 6–31 Subprogram Calls 6–33 Procedure Calls 6–34 Function Calls 6–37 return Statement 6–38 Mapping Subprograms to Components (Entities) 6–39 wait Statement 6–44 Inferring Synchronous Logic 6–45 Combinational vs Sequential Processes 6–50 null Statement 6–53

7 Concurrent Statements 7–1

process Statements 7–3 Combinational Process Example 7–5 Sequential Process Example 7–7 Driving Signals 7–9 block Statement 7–10 Concurrent Procedure Calls 7–12

Concurrent Signal Assignments 7–15 Conditional Signal Assignment 7–15 Selected Signal Assignment 7–17 Component Instantiations 7–20 generate Statements 7–23 for generate Statement 7–23 if generate Statement 7–27

8 Register, Multiplexer and Three-State Inference 8–1

Register Inference 8–2 Using Register Inference 8–3 wait vs if Statements 8–5 Recommended Use of Register Inference Capabilities 8–5 Restrictions on Register Capabilities 8–7 Delays in Registers 8–8 Describing Latches 8–9 Automatic Latch Inferencing 8–10 Restrictions on Latch Inference Capabilities 8–11 Example—Design with Two-Phase Clocks 8–12 Describing Flip-flops 8–14 Flip-flop with Asynchronous Reset 8–15 Example—Synchronous Design with Asynchronous

Reset 8–17 Additional Types of Register Inference 8–19 Attributes 8–19 async_set_reset 8–19 sync_set_reset 8–21 async_set_reset_local 8–23 sync_set_reset_local 8–25 async_set_reset_local_all 8–27 sync_set_reset_local_all 8–29

Example—Using Synchronous and Asynchronous

Processes 8–51 Multiplexers 8–53 New HDL Attribute 8–53 New Variables for Multiplexer Inference 8–54 New compile Variables 8–55 Uses of Variables and Attributes 8–56 New inference Report 8–56 Example of a Multiplexer Inference 8–57 Summary of HDL Compiler Limitations of Multiplexer

Inference 8–60 Three-State Inference 8–61 Assigning the Value ’Z’ 8–62 Latched Three-State Variables 8–63

9 Resource Sharing 9–1

Scope and Restrictions 9–3 Control Flow Conflicts 9–4 Data Flow Conflicts 9–7 Errors 9–8 Resource Sharing Methods 9–9 Automatic Resource Sharing 9–9 Source Code Preparation 9–10 Functional Description 9–10 Automatic Resource Sharing with Manual Controls 9–14 Source Code Preparation 9–16 Functional Description 9–18 Referring to Operations and Resources 9–27 Manual Resource Sharing 9–35 Source Code Preparation 9–36 Functional Description 9–36 Input Ordering 9–37 Resource Sharing Conflicts and Error Messages 9–39 User Directive Conflicts 9–39

Module Conflicts 9–40 Control Flow Conflicts 9–42 Data Flow Conflicts 9–43 Reports 9–44 Generating Resource Reports 9–44 Interpreting Resource Reports 9–44

10 Writing Circuit Descriptions 10–1

How Statements are Mapped to Logic 10–3 Design Structure 10–4 Adding Structure 10–4 Using Variables and Signals 10–4 Using Parentheses 10–6 Using Design Knowledge 10–7 Optimizing Arithmetic Expressions 10–7 Merging Cascaded Adders with a Carry 10–8 Arranging Expression Trees for Minimum Delay 10–9 Sharing Common Subexpressions 10–15 Operator Bit Width 10–18 Using State Information 10–21 Propagating Constants 10–25 Sharing Complex Operators 10–25 Design Compiler Optimization 10–26 Flattening Designs 10–27 Grouping Logic 10–27 Asynchronous Designs 10–28 Don’t-Care Inference 10–35 Using Don’t-Cares 10–40 Differences Between Simulation and Synthesis 10–40 Synthesis Issues 10–42

11 VHDL Compiler Directives 11–1

Notation for VHDL Compiler Directives 11–2 VHDL Compiler Directives 11–3 Translation Stop and Start Directives 11–3 Resolution Function Directives 11–6 Component Implication Directives 11–6 Synthesis Attributes and Constraints 11–7 About VHDL Attributes 11–8 Synthesis Attributes Defined for VHDL Compiler 11–9 Using VHDL Attributes to Specify Synthesis Constraints 11–10 Input Port Attributes 11–11 Output Port Attributes 11–13 Cell (VHDL Component Instantiation) Attribute 11–13 Design Constraints 11–14 Output Port Constraints 11–14 Embedded Constraint and Attribute Commands 11–16

12 Design Compiler Interface 12–1

Starting Design Compiler 12–3 Starting the Command Interface (dc_shell ) 12–3 Starting Design Analyzer 12–4 Processing the VHDL Source Files 12–4 Using Analyze and Elaborate with VHDL Source Files 12–5 Analyzing and Elaborating a Single VHDL Source File 12–5 Analyzing and Elaborating Multiple VHDL Source Files 12–5 Analyzing HDL Packages 12–6 Reading VHDL Source Files 12–7 VHDL Input Variables 12–7 Template Naming Variables 12–10 Array Naming Variables 12–11 Using VHDL Templates (Generics) 12–13 Grouping VHDL Designs 12–15 Writing Out VHDL Files 12–16