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Central processing unit CPUControl unit Arithmetic logical unit ALU... public class Interp {static int PC; // program counter holds address of next instr static int AC; // the accumulato

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COMPUTER SYSTEMS

ORGANIZATION

CuuDuongThanCong.com https://fb.com/tailieudientucntt

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Central processing unit (CPU)

Control unit

Arithmetic logical unit (ALU)

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ALU input register

ALU output register ALU

ALU input bus

Fig 2-2 The data path of a typical von Neumann machine

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public class Interp {

static int PC; // program counter holds address of next instr

static int AC; // the accumulator, a register for doing arithmetic static int instr; // a holding register for the current instruction

static int instr 3 type; // the instruction type (opcode)

static int data 3 loc; // the address of the data, or − 1 if none

static int data; // holds the current operand

static boolean run 3 bit = true; // a bit that can be turned off to halt the ma

public static void interpret(int memory[ ], int starting 3 address) {

// This procedure interprets programs for a simple machine with instructions // one memory operand The machine has a register AC (accumulator), used // arithmetic The ADD instruction adds an integer in memory to the AC, for e // The interpreter keeps running until the run bit is turned off by the HALT ins // The state of a process running on this machine consists of the memory, the // program counter, the run bit, and the AC The input parameters consist of // of the memory image and the starting address.

if (data 3 loc >= 0) // if data 3 loc is − 1, there is no operand data = memory[data 3 loc]; // fetch the data

execute(instr 3 type, data); //execute instruction }

}

private static int get 3 instr 3 type(int addr) { }

private static int find 3 data(int instr, int type) { }

private static void execute(int type, int data){ }

}

Fig 2-3 An interpreter for a simple computer (written in Java)

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Operand fetch unit

Instruction execution unit

Write back unit

Fig 2-4 (a) A five-stage pipeline (b) The state of each stage as afunction of time Nine clock cycles are illustrated

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Operand fetch unit

Write back unit

Instruction decode unit

Operand fetch unit

Write back unit

Fig 2-5 (a) Dual five-stage pipelines with a common instructionfetch unit

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S2 S3 S5 Instruction

decode unit

Operand fetch unit

LOAD Writeback

unit

S1 Instruction

fetch

unit

S4

Floating point STORE

ALU ALU

Fig 2-6 A superscalar processor with five functional units

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(a) (b)

CPU

Shared memory

Bus CPU CPU CPU

Local memories

CPU

Shared memory

Bus CPU CPU CPU

Fig 2-8 (a) A single-bus multiprocessor (b) A multicomputerwith local memories

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1 2 3 4 5 6 7

0 1 2 3 4 5

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Address Big endian Address

Byte

0 0

(a)

4 4 8 8 12 12

0 4 8 12

1 5 9 13

2 6 10 14

3 7 11 15

32-bit word

Little endian

Byte 3

(b)

7 11 15

2 6 10 14

1 5 9 13

0 4 8 12

32-bit word

Fig 2-11 (a) Big endian memory (b) Little endian memory

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A

C 1

1

0 0

(a)

B

(b)

Parity bits

A

C 1

1 0 0 0

0

1

(c)

Error A

B

C

1 1 0 0

0

Fig 2-14 (a) Encoding of 1100 (b) Even parity added (c) Error

in AC.

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Memory word 1111000010101110 0

1

0 2

1 3

0 4

1 5

1 6

1 7

0 8

0 9

0 10

0 11

0 12

1 13

0 14

1 15

1 16

0 17

1 18

1 19

1 20

0 21

Parity bits

Fig 2-15 Construction of the Hamming code for the memory

word 1111000010101110 by adding 5 check bits to the 16 databits

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Bus

Main memory CPU

Fig 2-16 The cache is logically between the CPU and main

memory Physically, there are several possible places it could belocated

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Fig 2-17 A single inline memory module (SIMM) holding 32

MB Two of the chips control the SIMM

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Main memory Cache

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of arm motion

Disk arm

Read/write head

Preamble

E C

1 sect

or

Fig 2-19 A portion of a disk track Two sectors are illustrated

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Surface 2

Surface 1

Surface 0

Read/write head (1 per surface)

Direction of arm motion Surface 3

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P16-19 Strip 16 Strip 17 Strip 18 Strip 12 P12-15 Strip 13 Strip 14

Strip 4 Strip 0

Strip 9 Strip 5 Strip 1

RAID level 2

RAID level 1

Bit 7

Bit 1 Bit 2 Bit 3 Bit 4

P8-11 Strip 6 Strip 2

Strip 10 P4-7 Strip 3

Strip 19 Strip 15

Strip 11 Strip 7 P0-3

Fig 2-23 RAID levels 0 through 5 Backup and parity drives areshown shaded

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Spiral groove

PitLand

2K block ofuser data

Fig 2-24 Recording structure of a Compact Disc or CD-ROM

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Frames of 588 bits, each containing

24 data bytes

Symbols of

14 bits each

42 Symbols make 1 frame

98 Frames make 1 sector

…

Fig 2-25 Logical data layout on a CD-ROM

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Printed label

Protective lacquer Reflective gold layer

layer

Substrate Direction

Infrared laser diode

Dark spot in the dye layer burned

by laser when writing 1.2 mm

Dye

Polycarbonate

Fig 2-26 Cross section of a CD-R disk and laser (not to scale) Asilver CD-ROM has a similar structure, except without the dyelayer and with a pitted aluminum layer instead of a gold layer

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Polycarbonate substrate 1

Polycarbonate substrate 2

Semireflective layer

Aluminum reflector

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Keyboard Floppy

disk drive

Hard disk drive

Hard disk controller

Floppy disk controller

Keyboard controller

Video controller Memory

CPU

Bus

Fig 2-29 Logical structure of a simple personal computer

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SCSI disk

Network controller

Video controller

Printer controller

Sound

ISA bridge

SCSI

scanner

Main memory SCSI

bus

PCI bus

ISA bus cache

Fig 2-30 A typical modern PC with a PCI bus and an ISA bus.The modem and sound card are ISA devices; the SCSI controller

is a PCI device

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(a) (b)

Electron gun

Grid Screen Spot on screen Vacuum Vertical

deflection plate

Horizontal scan

Vertical retrace Horizontal retrace

Fig 2-31 (a) Cross section of a CRT (b) CRT scanning pattern

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Front glass plate Front electrode Front polaroid

Bright Dark

Light source

;

Fig 2-32 (a) The construction of an LCD screen (b) The grooves

on the rear and front plates are perpendicular to one another

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Video RAM

Main memory

Video board A2B2C2

Fig 2-33 Terminal output on a personal computer

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Keyboard Some signals:

Protective ground (1) Transmit (2)

Receive (3) Request to send (4) Clear to send (5) Data set ready (6) Common return (7) Carrier detect (8) Data terminal ready (20)

Terminal ABC

Fig 2-34 Connection of an RS-232-C terminal to a computer.The numbers in parentheses in the list of signals are the pinnumbers

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Pointer controlled by mouse

Mouse buttons Mouse

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(a) (b)

Fig 2-36 (a) The letter ‘‘A’’ on a 5 × 7 matrix (b) The letter

‘‘A’’ printed with 24 overlapping needles

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Laser Rotating octagonal

mirrorDrum sprayed and charged

Light beamstrikes drum

Toner

ScraperDischarger

Drum

Blank

paper

Heatedrollers

Stackedoutput

Fig 2-37 Operation of a laser printer

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(a) (b) (c) (d) (e) (f)

Fig 2-38 Halftone dots for various gray scale ranges (a) 0–6 (b)14–20 (c) 28–34 (d) 56–62 (e) 105–111 (f) 161–167

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Low amplitude

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ISDN alarm

Digital bit pipe

carrier's internal network

exchange

Fig 2-40 ISDN for home use

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Hex Name Meaning Hex Name Meaning

2222222222222222222222222222222222222222222222222222222222222222222222222

4 EOT End Of Transmission 14 DC4 Device Control 4

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