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Data inWritegate I0 I1 I2 QDCK Word 1selectline Word 2selectline QDCK QDCK QDCK QDCK QDCK QDCK QDCK QDCK QDCK QDCK Figure 3-29.. RD delay from falling edge of Φ in T1Data setup time prio

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THE DIGITAL LOGIC LEVEL

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NAND A

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A A

6

7

B 2

C 3

Figure 3-3 (a) The truth table for the majority function of

three variables (b) A circuit for (a).

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A B

A

B

Figure 3-4 Construction of (a) NOT , (b) AND , and (c) OR

gates using only NAND gates or only NOR gates.

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C B

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AA = A

AB = BA (AB)C = A(BC)

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B A

(d) (c)

A B

B A

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Figure 3-9 (a) Electrical characteristics of a device.

(b) Positive logic (c) Negative logic.

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3 2

1

Figure 3-10 An SSI chip containing four gates.

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Figure 3-12 (a) An MSI multiplexer (b) The same

multi-plexer wired to compute the majority function.

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C A

Figure 3-13 A 3-to-8 decoder circuit.

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A If this fuse is

blown, B is not

an input to ANDgate 1

12 3 2 = 24input signals

24 input lines

6 outputs

50 inputlines

If this fuse isblown, AND gate

Figure 3-15 A 12-input, 6-output programmable logic array.

The little squares represent fuses that can be burned out to determine the function to be computed The fuses are arranged

in two matrices: the upper one for the AND gates and the lower one for the OR gates.

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A B

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A B

Carry

Carry out

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A + B

ENB

Figure 3-19 A 1-bit ALU.

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Carryout

1-bitALU

A6 B6

O6

1-bitALU

A5 B5

O5

1-bitALU

A4 B4

O4

1-bitALU

A3 B3

O3

1-bitALU

A2 B2

O2

1-bitALU

A1 B1

O1

1-bitALU INC

A0 B0

O0

Figure 3-20 Eight 1-bit ALU slices connected to make an

8-bit ALU The enables and invert signals are not shown for plicity.

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Figure 3-21 (a) A clock (b) The timing diagram for the

clock (c) Generation of an asymmetric clock.

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Figure 3-22 (a) NOR latch in state 0 (b) NOR latch in state 1 (c) Truth table for NOR .

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Q

Q R

Clock

Figure 3-23 A clocked SR latch.

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∆

Figure 3-25 (a) A pulse generator (b) Timing at four points in the circuit.

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D

Q

Figure 3-26 A D flip-flop.

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Figure 3-27 D latches and flip-flops.

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Q

CKCLR

PRQ

D Q

CKCLR

PRQ

19 18 17 16 15 14 13 12 11

GND(b)

CK CLR

Figure 3-28 (a) Dual D flip-flop (b) Octal flip-flop.

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Data in

Writegate

I0

I1

I2

QDCK

Word 1selectline

Word 2selectline

QDCK

Figure 3-29 Logic diagram for a 4 × 3 memory Each row is one of the four 3-bit words A read or write operation always reads or writes a complete word.

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(b) (a)

Data

in

Data out

Control

(d) (c)

Figure 3-30 (a) A noninverting buffer (b) Effect of (a) when

control is high (c) Effect of (a) when control is low (d) An inverting buffer.

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WE (a)

512K 3 8 Memory chip (4 Mbit)

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

RAS CAS

D

WE (b)

4096K 3 1 Memory chip (4 Mbit)

Figure 3-31 Two ways of organizing a 4-Mbit memory chip.

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Byte alterable Volatile Typical use

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Typical Micro- Processor

Symbol for electrical ground Symbol

for clock signal

Bus arbitration Addressing

Coprocessor Status

Miscellaneous Interrupts

Bus control

Power is 5volts +5v

Data

Φ

Figure 3-33 The logical pinout of a generic CPU The arrows

indicate input signals and output signals The short diagonal

lines indicate that multiple pins are used For a specific CPU, a

number will be given to tell how many.

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Memory bus

I/O bus

DiskOn-chip bus

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RD delay from falling edge of Φ in T1Data setup time prior to falling edge of ΦMREQ delay from falling edge of Φ in T3

RD delay from falling edge of Φ in T3Data hold time from negation of RD

6

5

0(b)

11

88

nsecnsecnsecnsecnsecnsecnsecnsec

ADDRESS

Time(a)

Read cycle with 1 wait state

Memory address to be read

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Bus grant

Bus request

I/O devices (a)

Bus request level 1

Bus grant level 1

Bus request level 2

Bus grant level 2

Arbiter

Figure 3-39 (a) A centralized one-level bus arbiter using

daisy chaining (b) The same arbiter, but with two levels.

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In Out In Out In Out In Out

Figure 3-40 Decentralized bus arbitration.

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Memory address to be read

Count ADDRESS

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8259A Interrupt controller CPU

D0-D7 CS A0 WR

INTA RD

IR1 IR2 IR3 IR4 IR5 IR6 IR7

+5 v

Keyboard Clock

Disk Printer

Figure 3-42 Use of the 8259A interrupt controller.

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512 KBunifiedL2 cache

Pentium IIprocessor

Contact

1.6 cm

16 KB level 1data cache

Tolocalbus

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Interrupts

Compatibity Diagnostics Initialization Power management Miscellaneous 64

3

27 Power

5 VID

TRDY#

Response

RS#

3 Misc#

5 Misc#

ADS#

33 A#

Figure 3-44 Logical pinout of the Pentium II Names in

upper case are the official Intel names for individual signals Names in mixed case are groups of related signals or signal

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Figure 3-45 Pipelining requests on the Pentium II’s memory bus.

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Pin 1 Index

Figure 3-46 The UltraSPARC II CPU chip.

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Bus arbitration

Memory address Address parity Address valid

Wait

Reply

Level 1 caches

to main memory

UPA interface

UltraSPARC II CPU

Tag address Tag valid

Tag data Tag parity

Level 2

cache

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