A Three-Phase UPS That Complies With the Standard IEC 62040-3

A Three-Phase UPS That Complies With the Standard IEC 62040-3 Fernando Botterón and Humberto Pinheiro Abstract—This paper proposes a down-sampled discrete-time internal-model-based contr

A Three-Phase UPS That Complies With the Standard IEC 62040-3

Fernando Botterón and Humberto Pinheiro

Abstract—This paper proposes a down-sampled discrete-time

internal-model-based controller in the synchronous reference

frame with a reduced number of poles This controller is

suit-able for three-phase pulsewidth modulation inverters with output

transformer for double-conversion uninterruptible power supply

applications It is demonstrated that the use of a down-sampled

rate and fewer poles in the internal model results in a number

of benefits, among which are the following: 1) improvement of

the transient response; 2) increase of the stability margin of

the closed-loop system; 3) a straightforward implementation in

fixed-point digital signal processor (DSP) and microcontroller

implementation as well as a reduction of the required

mem-ory space; and 4) a simple solution for the saturation of the

output transformer As a result, it is possible to obtain output

voltages with reduced total harmonic distortion while ensuring

good transient performance for both linear and nonlinear loads.

To confirm the advantages claimed for the proposed

synchro-nous reference dq frame internal-model-based controller and to

demonstrate the steady-state and transient performance under the

test conditions of the International Electrotechnical Commission

Standard 62040-3, the experimental results from a 10-kVA

space-vector-modulated three-phase inverter, which is fully

con-trolled by a DSP TMS320F241, are presented.

Index Terms—Digital control, discrete-time control, internal

model principle, power transformers, uninterruptible power

systems (UPSs).

I INTRODUCTION

THE USE of uncontrolled rectifiers within critical loads,

e.g., in computers and medical equipment, requires

unin-terruptible power supplies (UPSs) that are capable of

maintain-ing low total harmonic distortion (THD) at the output voltages

even under highly distorted load currents [1] These types of

loads distort the UPS output voltages as a result of unbalanced

nonlinear currents drawn by them, thus causing voltage drops

across the output inductance–capacitance (LC) filter, which is

used to attenuate the pulsewidth-modulation (PWM) inverter

high-frequency harmonics This becomes a concern in

medium-and high-power UPS, where the switching frequency is low

to limit the switching losses Other factors also contribute to

UPS output voltage distortion Among them are the inherent

Manuscript received November 7, 2005; revised February 28, 2006 This

work was supported in part by CAPES and in part by CNPq.

F Botterón is with the Departamento de Electrónica, Facultad de Ingeniería,

Universidad Nacional de Misiones, Obera 3360, Argentina (e-mail: botteron@

gmail.com).

H Pinheiro is with the Power Electronics and Control Research Group,

Federal University of Santa Maria, Santa Maria 97105-900, Brazil (e-mail:

humberto@ctlab.ufsm.br).

Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2007.894782

nonlinearities of the PWM inverter, fluctuations of the dc bus voltage, and power semiconductor voltage drops More-over, transformerless UPSs are susceptible to interference from spikes and transients caused by assorted devices connected to the utility grid These interferences, transferred through the UPS to the load, reduce the UPS output voltage quality Thus, UPSs with output transformer provide a safer and more robust solution than transformerless UPSs since the transformer offers

a galvanic isolation to the load from undesirable disturbances

of the main supply [2]

In digitally controlled systems, quantization of the analog-to-digital converters, digital PWMs, and roundoff resulting from fixed-point arithmetic can generate errors that result in

a dc component at the inverter output voltage These errors, added to the inevitable nonideal features of real live circuit implementation and amplified by an inappropriate selection

of the controller, can lead the output transformer to saturate, degrading the overall performance of the system [13]–[15] It is important to point out that a standard such as the International Electrotechnical Commission (IEC) 62040-3 recommends that the output voltage dc component shall be less than 0.1% of its root mean square (rms) rated value and specifies that the distortion factor “D” of sinusoidal UPS output voltages must

to be less than 8% To deal with these issues, many discrete-time control structures for single-phase and three-phase UPSs are reported in the literature

With the well-known Repetitive Controller [4]–[6], which

is established on the internal model principle [3], several

high-performance approaches have been proposed to achieve high-quality output voltages in three-phase and single-phase PWM inverters [7]–[23] Reference [7] proposes a discrete-time control strategy using a repetitive controller extended

to a proportional–integral (PI) compensator structure in

sta-tionary αβ frame to compensate voltage distortions due to

nonlinear and unbalanced loads The steady-state performance

is improved by using a 30th-order low-pass finite-impulse response (FIR) filter after implementing the measures to at-tenuate the high-frequency components so that the voltage error contains only lower frequencies However, the proposal referenced above presents a cancellation issue: the zero at

z = 1 (in the discrete-time domain) of the plant introduced

by the transformer cancels with the pole at z = 1 of the repetitive controller, which violates the internal model principle

[3], as demonstrated in [15] This problem may eventually lead the transformer to saturation In [9], the modified

plug-in repetitive controller combplug-ined with the conventional One-sampling-ahead preview compensator in stationary αβ frame

has been reported to improve the output voltage distortion when 0278-0046/$25.00 © 2007 IEEE

BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2121

Fig 1 Three-phase PWM inverter, ∆Y transformer, filter, and load.

three-phase rectifier loads are connected at the UPS output

However, in this case, the output transformer is not considered

Therefore, connecting an insulating transformer at the inverter

output, a pole–zero cancellation occurs with the plug-in

repet-itive controller in closed loop In [10], the author proposes

a two-layer voltage controller scheme in synchronous frame

with a PI regulator to ensure zero steady-state error at the

fundamental frequency and a repetitive-based controller with a

high-pass filter to compensate for the harmonics at the inverter

output voltages However, inadequate choices of the high-pass

filter cutoff frequency may result in dc components that can

saturate the transformer at the inverter output Moreover, the

repetitive controller with a high-pass filter produces pole–zero

cancellation, which may lead to output transformer saturation

Other solutions that are also based on the internal model

principle were presented in [11] and [12] In [11], a

three-layer control scheme is proposed It consists of a proportional

compensator in stationary αβ frame, an integral controller in

synchronous frame to compensate the fundamental component,

and a selective harmonic compensator in stationary frame based

on a passband FIR filter with unit gain and zero phase at

the selected harmonics Reference [12] proposes a robust

con-troller based on the passivity theory framework for three-phase

UPS This controller guarantees asymptotic stability with good

steady-state performance for nonlinear and unbalanced loads

Although the controllers proposed in [11] and [12] may be

ad-equate solutions for reducing distortion in output voltages and

for operating with an insulating transformer, the computational

requirements to implement them increase significantly with

the number of compensating harmonics In addition, since the

controller coefficients are not integer numbers, this controller

is sensitive to quantization and roundoff errors, and as a result,

the tracking at selected harmonics is compromised References

[18] and [19] propose a down-sampled repetitive controller in

synchronous frame with reduced number of poles, which only

compensate odd harmonics in stationary frame This controller

gives reduced THD output voltages of a three-phase UPS It

also makes it possible to solve the output transformer

satu-ration; still more due to the slower sampling rate, it is not

necessary to include a zero-phase-shift low-pass FIR filter [6] to

improve the robustness of the closed-loop system On the other

hand, [20] proposes an odd-harmonic digital repetitive

plug-in controller to reject these kplug-inds of disturbances plug-in stationary frame This odd-harmonic repetitive controller does not have

a pole at z = 1, so it is suitable for operating with an output

transformer However, a low-pass FIR filter must be included

in the periodic signal generator loop to reduce the repetitive frequency gains, and this consequently increases the closed-loop system robustness As a result, this filter compromises tracking and disturbance rejection

On the other hand, it is important to emphasize that few papers explore the UPS transient behaviors Moreover, few papers explore the controller transient behaviors using the discrete-time internal model principle Hence, to obtain output voltages with reduced THD and an improved load transient, this paper proposes a down-sampled internal-model-based con-troller in synchronous reference frame with a reduced number

of poles This internal-model-based controller acts together with a proportional–derivative (PD) predictive compensator, which has the function to stabilize the closed-loop system This compensator results in a simple form for digital implementation and only requires the measure of the UPS output voltage [15], [23] The main feature of the proposed internal-model-based controller is that it is a straightforward solution for output transformer saturation In addition, the reduced number of poles

of the proposed internal model in synchronous frame improves the transient performance for linear and nonlinear loads as well

as enhancing the stability margin of the closed-loop system Thus, it is demonstrated that the transient performance with the proposed controller can be improved by satisfying the rigorous output dynamic performance classification 1 of the standard IEC 62040-3, which classifies UPS by performance

To demonstrate the advantages claimed, the proposed discrete-time controller structure is digitally implemented in a 16-bit fixed-point digital signal processor (DSP), and experimental results in steady state and transient conditions from a 10-kVA prototype are given

II SYSTEMDESCRIPTION

A typical double-conversion UPS power circuit is shown in Fig 1 Among the three-phase inverter configurations, the one

shown is a strong candidate since: 1) it provides galvanic

iso-lation to the load; 2) it allows the output voltage to be selected

according to customer needs; and 3) it provides a neutral by

the delta-star (∆Y) connection The dc-bus voltage is almost

constant and supplied by a six-pulse three-phase uncontrolled

diode rectifier, which provides energy to the inverter in normal

operation mode The dc-to-ac conversion is accomplished by

a space-vector-modulated three-phase three-leg inverter with

insulated-gate bipolar transistor The high-frequency harmonics

introduced by the modulation are attenuated by the LC filter It

is important to point out that the filter inductors are located at

the transformer primary side so as not to introduce distortions

in the output voltages that result from zero-sequence voltages

produced by unbalanced load currents, which will be shorted

on the delta connection at the transformer primary side [15]

Since this inverter is not capable of controlling zero-sequence

voltages, it is important to minimize the zero-sequence

im-pedance to reduce the distortions in the output voltages Hence,

the topology in Fig 1 offers a degree of freedom to minimize

the zero sequence impedance

III THREE-PHASEPWM INVERTER, ∆Y TRANSFORMER,

FILTER,ANDLOADMODEL

A Stationary Frame Model

From the circuit in Fig 1, the dynamic equations of the

inverter, transformer, filter, and load can be obtained by

ap-plying Kirchhoff’s laws To simplify the system modeling, it

is considered that the leakage inductances of the primary and

secondary sides of the transformer are lumped at the secondary

side The coil resistances are also neglected The following

equations are then obtained:



u u1223

u31



=









2L+ M L
d

−L 2L+ M L
d

M +L
d −L

M +L
d









d dt



i i ab bc

i ca





M + L  d



v

 an

v  bn

v  cn



d

dt



i



as

i  bs

i  cs



M + L  d

d dt



i i ab bc

i ca



M + L  d



v

 as

v bs 

v cs 





˙v



an

˙v bn 

˙v cn 



= 1

C 



i

 as

i  bs

i  cs



 − 1

C 



i

 oa

i  ob

i  oc



In these equations, M is the mutual inductance, L is the filter

inductance, L  d is the equivalent leakage inductance, and C is

the filter capacitance In addition, u12, u23, and u31are the

line-to-line PWM voltages produced by the inverter; v  an , v  bn, and

v  cn , and i  oa , i  ob , and i  oc are the phase-to-neutral voltages and

load currents referred to the transformer primary side; and i ab,

i , and i are the phase current in the delta connection

B Synchronous Reference Frame State-Space Model Transforming (1)–(3) to αβ and then to synchronous frame

as in [25], using the linear transformations given in the Appendix, the state-space model is given by ˙xdq (t) =

Adqxdq (t) + B dqudq+ Fdqwdq, where the matrices Adq,

Bdq, and Fdqare given as

Adq=

























Bdq=

























Fdq=

























The state vector has been selected as xdq (t) = [i dp i qp i ds i qs v d v q]T, and the input and disturbance

vectors as udq (t) = [u d u q]T and wdq (t) = [i od i oq]T,

respectively In these matrices, D is defined as D = 3LM + 3LL  d + M L  d

From (1), it is seen that the voltages applied at the trans-former input are the line-to-line voltages produced by the inverter To avoid an additional transformation from line-to-line to phase voltages that must be performed in the DSP, the space vector modulation is accomplished using the line-to-line voltages referred above

C Synchronous Reference Frame Discrete-Time Model

To obtain a discrete-time model for the discrete-time con-troller design, the synchronous frame state equation in the continuous time domain obtained above is solved throughout a

sampling period T For this purpose, it is considered that the

control action udq (t) remains constant in a sampling period

T Thus, the discrete-time state-space equation of the plant

that takes into account the delay of a digital implementation is given by



xdq (k+1)T

udq_d (k+1)T



=



G H0

 

xdq (kT )

udq_d (kT )

 +



H1 I



udq (kT ).

(5)

In (5), the additional state variable udq_d represents the delayed control action that models the real-time digital

BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2123

Fig 2. Timing chart of DSP controller Tpwm: switching period T : sampling period and PD compensator computing period T d : time delay Tim :

internal-model-based controller computing period Tim= 2T , and T d = T

implementation delay, and the matrices G, H0, and H1 are

given as

G = eAdq T

H 0= eAdq (T −T d)A−1 dq (eAdq T d − I)B dq

H 1 = A−1 dq

eAdq (T −T d)− I Bdq (6)

where T d is the time delay mentioned above, which is related

to a given DSP implementation

It is important to note that to obtain (5), the sampling of

the variables of interest and the updating of the control law

are performed as shown in the timing chart of Fig 2 With

this sampling scheme, it is possible to use a low switching

frequency to limit the switching losses while preserving an

acceptable sampling frequency Also, since sampling is carried

out at zero vectors, the resulting low-frequency harmonics over

the sampled data are reduced when compared with one sample

per sampling period [24]

Since the discrete-time controller proposed here is modeled

using an input–output approach, it is useful to obtain the

input–output description of the plant, which can be found from

(5), by applying theZ transform Strictly speaking, since the

plant represented by (5) is multiple-input–multiple-output, it is

obtained a sampled transfer function matrix of the system, i.e.,

Gp (z) = C dq (zI − G dq)−1Hdq+ Ddq (7)

where

Gdq=



G H0



Hdq=



H1 I



Cdq= [ 02×4 I2×2 02×2]

In this case, the resulting sampled transfer function matrix can be written as

Gp (z) =



g1(z) g2(z)

−g2(z) g1(z)



(9)

where the sampled transfer functions g1(z) and g2(z) are given

by the proper rational functions

g1(z) = b0z

4+ b1z3+ b2z2+ b3z + b4

z5− a1z4+ a2z3− a3z2+ a4z

g2(z) = −c0z4− c1z3− c2z2+ c3z + c4

z5− a1z4+ a2z3− a3z2+ a4z . (10)

Note that (9) shows that the system presents a cross coupling

given by the transfer functions g2(z) and −g2(z) In order

to simplify the controller design, is useful to work with a single-input–single-output (SISO) system It is shown that the influence of the cross transfer functions is negligible, or in another words, the system is weakly coupled It is possible to see in Fig 3 that for a large variation in frequency, the transfer

function g2(z) significantly attenuates the output v q when an

input signal in u dis applied or vice versa Hence, the system can

be treated as a SISO control problem with a transfer function

given by g1(z) without significantly affecting the closed-loop

performance

In order to define a proper discrete-time voltage controller for

the plant described by g1(z), upon the internal model principle

foundation, it is important to show the impact that the zeros of the plant have in the selection of the controller structure Fig 4

shows the zeros of g1(z).

Fig 4 shows that this plant presents a pair of zeros at the fun-damental frequency in synchronous frame, which is associated with the insulating transformer These zeros indicate that the transformer does not transfer the dc component to its output This means that an inadequate selection of the discrete-time

Fig 3. Frequency responses of g1(z) and g2(z) T = 198.41 µs.

Fig 4 Zero map of the input–output-sampled transfer function of the

plant g1(z).

controller may produce a pole–zero cancellation, which causes

any residual dc component from the digital implementation

to be amplified, which in turn may lead the transformer to

saturate, as demonstrated in [15] To avoid this problem, a new

discrete-time voltage controller in synchronous frame based on

the internal model principle, and adequate for the system in

Fig 1, will be described in the next section

IV PROPOSEDDISCRETE-TIMEINTERNAL-MODEL-BASED

CONTROLLER INSYNCHRONOUSREFERENCEFRAME

This section develops the proposed discrete-time voltage

controller based on the internal model principle in synchronous

reference frame Let us consider the design problem of a SISO

Fig 5 Discrete-time feedback SISO LTI system.

linear time-invariant (LTI) system in the discrete-time domain shown in Fig 5, where the strictly proper transfer function of

the plant is given by g1(z) The problem is to design a controller with a proper transfer function g c (z) so that the feedback

system is asymptotically stable and meets the specifications of zero error tracking in steady state even with disturbance signals present in the plant

The design procedure, which was developed from the inter-nal model principle theory presented in [15] for discrete-time systems, can be summarized in two steps: 1) introduction of

1/φ(z), a model of the reference and disturbance signals inside the loop, where φ(z) is the least common denominator of the unstable poles of r(z) and w(z) and 2) stabilization of the

feedback system using a conventional compensator It must be

emphasized that neither root of the internal model φ(z) must be

a zero of the transfer function of the plant so as to ensure the exact cancellations of the unstable modes of the reference and disturbance signals

A Proposed Internal Model

With the aim of defining an adequate internal model for the

plant g1(z), five candidate internal models are presented below.

Fig 6 shows the pole map of a discrete-time internal model that is often used in conventional repetitive controllers [5] When this internal model is implemented in stationary frame,

the pole at z = 1 is cancelled with the zero of the plant at

the same location On the other hand, if this internal model

BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2125

Fig 6 Pole map Internal model of the conventional repetitive controller [5].

T = 198.41 µs, and 1/φ(z) = 1/(z N − 1).

Fig 7 Pole map Internal model with poles at odd multiples of 60 Hz.

T = 198.41 µs, and 1/φ(z) = 1/(z N/2+ 1).

is implemented in synchronous frame, the same pole–zero

cancellation occurs at 60 Hz So this particular internal model

is inappropriate for this application as demonstrated in the

experimental result of Fig 20 It can be seen that the output

phase voltages have the desired levels with a low THD, but

the currents at the transformer primary side appear with a

significant offset, which increases continuously, shutting down

the PWM inverter as a result of overcurrents

Fig 7 shows a discrete internal model with poles at

frequen-cies that are odd multiples of 60 Hz, while Fig 8 presents an

internal model with poles at frequencies that are even multiples

of 60 Hz These internal models have been employed in

three-phase UPS controllers [18], [19] as well as in an odd-harmonic

repetitive controller [20] for single-phase applications [21],

[22] When the internal model in Fig 8 is implemented in

Fig 8 Pole map Internal model with poles at even multiples of 60 Hz.

T = 198.41 µs, and 1/φ dq (z) = 1/(z N/2 − 1).

Fig 9 Pole map Internal model with reduced number of poles.

T = 198.41 µs.

synchronous frame, there is no pole–zero cancellation with the plant Similarly, the pole–zero cancellation is not a concern for the internal model of Fig 7 in stationary frame On the other hand, when operating with low switching frequencies, it

is desirable to keep the sampling frequency as high as possible

to improve the closed-loop performance Usually, Tpwm= 2T

In this case, the high gains of the poles close to the Nyquist frequency may lead to system instability In order to overcome this limitation, a zero-phase-shift low-pass FIR filter can be included [6] to improve the robustness at high frequencies However, this filter will increase the tracking error and com-promise disturbance rejection

Fig 9, on the other hand, presents an internal model with a reduced number of poles In this case, the internal model has been chosen to compensate the fundamental and the harmonics

Fig 10 Internal model with reduced number of poles and roundoff error in

coefficients T = 198.41 µs.

Fig 11 Pole map of the proposed internal model in synchronous frame.

N = T1/2 T , T1= 1/60, T = 198.41 µs, Tim= 2T , and 1/φ dq (zim ) =

1/(zimN/2 − 1).

from 2nd to 7th Note that it is possible to include more poles

if desired This internal model is adequate for the system in

Fig 1 since it does not cancel the zeros of g1(z) However, the

poles of this internal model are sensitive to roundoff errors in

the polynomial coefficients, which are a concern in fixed-point

arithmetic implementation As a result, the pole location of

the internal model can be significantly modified, as illustrated

in Fig 10

Based on the internal models presented above, and having

considered them inadequate for the system in Fig 1, we now

propose a suitable discrete-time internal model for the plant

g1(z) The pole map of the proposed internal model in

syn-chronous frame is shown in Fig 11 This internal model has

half the poles of the internal model shown in Fig 8, and no

root of φ dq (zim) is a zero of the plant Also, this proposed internal model is computed with a reduced sampling rate As

a result, the Nyquist frequency of the internal-model-based controller is smaller than the first set of harmonics generated

by the switching operation of the PWM inverter, i.e., there are

no internal model poles in the model uncertainty region of the plant Note that this internal model results in a reduced compu-tational effort controller without the roundoff error of the fixed-point implementation since the coefficients of its polynomial are integer numbers Therefore, we propose here a discrete-time

control structure with a faster loop at a sampling period T to

keep a satisfactory sampling rate and a down-sampled internal-model-based controller This results in a multirate closed-loop system, as presented in Fig 12

From the two-step design procedure presented at the begin-ning of this section, the proposed internal-model-based

con-troller, which operate at a sampling period Tim= 2T , can be

included in the closed loop To complete the

internal-model-based controller design, the numerator Nim(z) of the transfer function Gim(z) shown in Fig 12 must be selected To avoid

compromising the simplicity of this controller being

consid-ered, this numerator can be selected as Nim(zim) = kimzimd As

a result, the sampled transfer function of this controller can be written as

Gim(zim) =Nim(zim)

φ dq (zim), where φ dq (zim) = z

N/2

im −1. (11)

In this transfer function, the controller gain kim determines the convergence time of the voltage error to zero, and the

pa-rameter d is the time advance step size used to compensate the

closed-loop phase at high frequencies [23] These parameters must be chosen to ensure the asymptotic stability of the closed loop and to meet a desired performance

The next step is to design the conventional compensator

G c (z) to stabilize the closed loop with the plant G p (z) = g1(z).

In this case, a predictive PD compensator has been selected

whose proper transfer function G c (z) is given as

G c (z) = k1z −1 + k2z −2 (12) This compensator has been selected mainly for its simple structure, which only requires the measurement of the phase

to neutral output voltages In addition, it provides a significant phase and gain margin to the closed-loop system The predictive

PD controller gains k1 and k2 are determined by placement

of the dominant poles of the closed-loop system [23] It is

important to point out that the tandem connection of G c (z) with G p (z) is completely characterized by the proper transfer function G c (z)G p (z) since there is no pole–zero cancellation between G c (z) and G p (z), as established in [15].

B Stability Analysis

Since the closed-loop system operates with two different sampling rates, the stability analysis can be performed in two steps

Step 1: The closed-loop stability of the tandem connection of the plant with the PD compensator must be ensured This faster

BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2127

Fig 12. Control structure of the proposed closed-loop multirate SISO discrete-time voltage controller in synchronous frame for axis “d.” z = e T s, and

zim= e Tims.

Fig 13 Closed-loop system Tandem connection of the plant plus predictive PD compensator.

Fig 14. Nyquist plot of G c (z)G p (z) k1= 0.12, k2 =−0.08, and T =

198.41 µs.

loop operates with a sampling period T , which results in the

control structure shown in Fig 13

To ensure the closed-loop asymptotic stability of the

sys-tem represented in Fig 13, the roots of the polynomial 1 +

G c (z)G p (z) = 0 must be inside the unit circle To demonstrate

that this closed loop is stable, the Nyquist plot of the open-loop

transfer function G c (z)G p (z) can be used, as shown in Fig 14.

It can be seen that the tandem connection of G p (z) with G c (z)

has a large gain margin, which in this case is about 16 dB, and

an infinite phase margin Therefore, the closed-loop system in

Fig 13 is asymptotically stable

Step 2: This step is to ensure the overall stability when the

proposed internal-model-based controller (11) is introduced To

extend the previous stability criteria to the multirate controller

Fig 15 Single-rate equivalent of the multirate closed-loop system with a

sampling period Tim system in Fig 12, we transform it to an equivalent system

sampled at slower rate Tim As a result, the equivalent closed-loop system becomes as that shown in Fig 15

The sampled transfer function of the equivalent slow-rate

plant GMF(zim) can be found from the equivalent slow-rate state-space representation of the plant and PD compensator, which is given in the Appendix This transfer function can be expressed as

GMF(zim)

6

im− n1z5

im− n2z4

im+ n3z3

im− n4z2

im+ n5zim

z7

im−d1z6

im−d2z5

im+ d3z4

im+ d4z3

im−d5z2

im+ d6zim−d7

.

(13) The closed-loop stability of the tandem connection of

Gim(zim) with GMF(zim) can be proved using the Nyquist criterion plots of the open-loop transfer function, i.e.,

Gim(zim)GMF(zim) Fig 16 shows the Nyquist plot for

N = 42, kim = 1, and d = 1 It can be seen that the closed-loop

system with an internal-model-based controller remains stable with a significant gain and phase margin

To demonstrate the benefit of performing the proposed discrete-time down-sampled internal-model-based controller,

Fig 16. Nyquist plot of G(zim) = Gim(zim)GMF(zim) N = 42, and

Tim= 396.82 µs.

Fig 17 Nyquist plot of the single-rate system operating at lower sampling

frequency G(z) = Gim(z)G p (z)/(1 + G p (z)G c (z)), N = 42, kim = 1,

d = 1, and T = 396.82 µs.

the Nyquist plot of the closed-loop system in Fig 12, which

op-erates with a single rate at lower sampling frequency, is shown

in Fig 17 It can be seen that the gain margin stays almost

the same if compared with the gain margin in Fig 16, but the

phase margin decreases significantly when the system operates

at a single rate Therefore, the stability margin of the proposed

multirate system in Fig 12 is significantly bigger than the

single-rate system at lower sampling frequency, which therefore

represents the benefit of the proposed multirate controller

Concerning digital implementation, by applying the inverse

Z-transform to (12) and (11), we can obtain the respective

re-cursive difference equations of the predictive PD controller and

the proposed down-sampled internal-model-based controller as

ucd(kT ) = k1e d (k − 1) + k2e d (k − 2) (14)

uimd(mTim) = kime d [mTim− (N/2) + d]

From Fig 12, we can see that the control law applied to the plant is given by

u d (kT ) = ucd(kT ) + uimd(mTim). (16)

Note that (14)–(16) are written for the axis “d”; therefore, similar equations can be written for the axis “q.” Regarding the gain, kim must be selected to guarantee a fast convergence of the voltage error to zero, maintaining the closed-loop system

stability The values of kim and d are given in Table II It

is important to emphasize here that simplicity is a significant advantage of the proposed controller if compared with the controller presented in [11] It becomes clear by realizing that the proposed internal-model-based controller implementation

is just (15) In fixed-point arithmetic, the quantization and rounding errors may result in roots of the polynomial internal model to be quite different from the desired one (see Fig 10) However, since the proposed internal-model-based controller polynomial coefficients are 1s or 0s, the internal model roots have low sensitivity to these errors This is another advantage if compared with the controllers of [11, eq (9)] and [12, eq (27)]

V STEADY-STATE ANDDYNAMICOUTPUTVOLTAGE

CHARACTERISTICS OF THEUPS The UPS output specifications according to IEC 62040-3 must have output voltage dynamic performance characteristics not exceeding the limits in [1, Figs 1, 2, or 3] for the application

of increasing/decreasing load steps under linear and reference nonlinear load for the test conditions in Section 6.3 of this standard The objective of classifying UPS by performance is

to provide a common base on which all UPS manufacturer and supplier data are to be compared This enables purchasers of equipment with similar UPS power ratings to compare products from different manufacturers under the same measurement conditions

A Reference Nonlinear Load Steps in Normal Mode

Step nonlinear loading is defined as the application of the test circuit, which is shown in Fig 18, for dissipating the required steady-state output active power for the percentage load step relative to the rated steady-state output active power

of the UPS The load circuit is then first deenergized before application so that its capacitor voltage starts from zero voltage when applied to the UPS output To determine the UPS output dynamic performance, the deviation from the under/overvoltage limits defined [1] must be obtained Then, using the test circuit

in Fig 18, the required step loads (33% of the rated output apparent power) must be applied or reduced in accordance with those in [1, Section 6.3.8.5] monitoring the load capacitor voltage The capacitor voltage changes should remain within the stated tolerances in [1, Figs 1 or 2, Section 5.3.1] In

Fig 18, U c is the rectified voltage, R1 is the load resistor set

to dissipate an active power equal to 66% of the total apparent

power, and R sis a series line resistor set to dissipate an active power equal to 4% of the total apparent power The procedure

BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2129

Fig 18 Reference nonlinear load test [1].

Fig 19 Resistive load test [1].

for calculating the passive elements of this reference nonlinear

load is described in [1, Annex E]

B Linear Load Steps

With the UPS operating in normal mode, a resistive load

equal to 100% of the output active power must be applied in

two steps using the circuit in Fig 19: one equal to 20% and one

equal to 80% The step must be performed at the peak value of

the output waveform Similarly, unloading must be measured

by reducing the load to 20% of the rated output active power by

switching off the 80% load In both cases, the output waveform

must be observed and stored so as to permit calculation of any

dynamic performance deviation This deviation is referred as

the rms value above or below the rated value, which is obtained

on a successive half-cycle by half-cycle The computed values

of this dynamic deviation must remain within the stated limits

in [1, Figs 1, 2, or 3, Section 5.3.1]

VI EXPERIMENTALRESULTS

The circuit in Fig 1 has been tested experimentally to

verify the proposed discrete-time-voltage internal-model-based

controller using a DSP TMS320F241 to control a 10-kVA

UPS The steady-state load tests have been performed using

resistive linear loads and nonlinear single-phase and

three-phase uncontrolled diode rectifiers The reference nonlinear

load, as described in Fig 18 and designed according to the

standard IEC 62040-3, has an input series resistor R = 0.5 Ω,

TABLE I

S ETUP P ARAMETERS

TABLE II

C ONTROLLER P ARAMETERS

Fig 20. Experimental result Line current i aat the transformer primary side with dc component With the internal model of the conventional repetitive controller Output phase-to-neutral voltages Voltage scale: 50 V/div Current

scale: 10 A/div N = 84, and T = 198.41 µs φ(z) is in Fig 6.

a load resistor R1= 30 Ω, and a filter capacitor C c = 4700 µF,

and allow to obtain a crest factor of 3 The setup parameters are given in Table I, and the controller parameters are given

in Table II

A Steady-State Performance

Fig 20 shows the output phase voltages and the input current

at the transformer primary side with a significant dc component when the system in Fig 1 operates with an internal model based on the conventional repetitive controller This fact can

be proven through the harmonic spectrum presented in Fig 21, which denote a dc component around 140% On the other