Applied reconfigurable computing architectures, tools, and applications 2018

Machine Learning and Neural Networks Approximate FPGA-Based LSTMs Under Computation Time Constraints.. mem-In this work, an approximate computing scheme along with a novel hardwarearchit

Nikolaos Voros · Michael Huebner

Georgios Keramidas · Diana Goehringer Christos Antonopoulos · Pedro C Diniz (Eds.)

123

14th International Symposium, ARC 2018

Santorini, Greece, May 2–4, 2018

Proceedings

Applied Reconfigurable Computing

Architectures, Tools, and Applications

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Reconfigurable computing platforms offer increased performance gains and energy

efficiency through coarse-grained and fine-grained parallelism coupled with theirability to implement custom functional, storage, and interconnect structures As such,they have been gaining wide acceptance in recent years, spanning the spectrum fromhighly specialized custom controllers to general-purpose high-end programmablecomputing systems Theflexibility and configurability of these platforms, coupled withincreasing technology integration, have enabled sophisticated platforms that facilitateboth static and dynamic reconfiguration, rapid system prototyping, and early designverification Configurability is emerging as a key technology for substantial productlife-cycle savings in the presence of evolving product requirements, standards, andinterface specifications

The growth of the capacity of reconfigurable devices, such as FPGAs, has created awealth of new research opportunities and intricate engineering challenges Within thepast decade, reconfigurable architectures have evolved from a uniform sea of pro-grammable logic elements to fully reconfigurable systems-on-chip (SoCs) with inte-grate multipliers, memory elements, processors, and standard I/O interfaces One of theforemost challenges facing reconfigurable application developers today is how to bestexploit these novel and innovative resources to achieve the highest possible perfor-mance and energy efficiency; additional challenges include the design and imple-mentation of next-generation architectures, along with languages, compilers, synthesistechnologies, and physical design tools to enable highly productive designmethodologies

The International Applied Reconfigurable Computing (ARC) symposium seriesprovides a forum for dissemination and discussion of ongoing research efforts in thistransformative research area The series of editions started in 2005 in Algarve,Portugal The second edition of the symposium (ARC 2006) took place in Delft, TheNetherlands, and was the first edition of the symposium to have selected paperspublished as a Springer LNCS (Lecture Notes in Computer Science) volume Subse-quent editions of the symposium have been held in Rio de Janeiro, Brazil (ARC 2007),London, UK (ARC 2008), Karlsruhe, Germany (ARC 2009), Bangkok, Thailand (ARC2010), Belfast, UK (ARC 2011), Hong Kong, SAR China (ARC 2012), California,USA (ARC 2013), Algarve, Portugal (ARC 2014), Bochum, Germany (ARC 2015),Rio de Janeiro, Brazil (ARC 2016), and Delft, The Netherlands (ARC 2017).This LNCS volume includes the papers selected for the 14th edition of the sym-posium (ARC 2018), held in Santorini, Greece, during May 2–4, 2018 The symposiumattracted a large number of very good papers, describing interesting work on recon-figurable computing-related subjects A total of 78 papers were submitted to thesymposium from 28 countries In particular, the authors of the submitted papers arefrom the following countries: Australia (3), Belgium (5), Bosnia and Herzegovina (4),Brazil (24), China (22), Colombia (1), France (3), Germany (40), Greece (44),

India (10), Iran (4), Ireland (4), Italy (5), Japan (22), Malaysia (2), The Netherlands (5),New Zealand (1), Norway (2), Poland (3), Portugal (3), Russia (8), Singapore (7),South Korea (2), Spain (4), Sweden (3), Switzerland (1), UK (18), and USA (11).Submitted papers were evaluated by at least three members of the ProgramCommittee The average number of reviews per submission was 3.7 After carefulselection, 29 papers were accepted as full papers (acceptance rate of 37.2%) and 22 asshort papers These accepted papers led to a very interesting symposium program,which we consider to constitute a representative overview of ongoing researchefforts in reconfigurable computing, a rapidly evolving and maturing field In addition,the symposium included a special session dedicated to funded research projects Thepurpose of this session was to present the recent accomplishments, preliminary ideas,

or work-in-progress scenarios of on-going research projects Nine EU- andnational-funded projects were selected for presentation in this session

Several people contributed to the success of the 2018 edition of the symposium Wewould like to acknowledge the support of all the members of this year’s symposiumSteering and Program Committees in reviewing papers, in helping the paper selection,and in giving valuable suggestions Special thanks also to the additional researcherswho contributed to the reviewing process, to all the authors who submitted papers tothe symposium, and to all the symposium attendees In addition, special thanks to

Dr Christos Antonopoulos from the Technological Educational Institute of WesternGreece for organizing the research project special session Last but not least, we areespecially indebted to Anna Kramer from Springer for her support and work in pub-lishing this book and to Pedro C Diniz from INESC-ID, Lisbon, Portugal, for hisstrong support regarding the publication of the proceedings as part of the LNCS series

Michael HuebnerGeorgios KeramidasDiana Goehringer

The 2018 Applied Reconfigurable Computing Symposium (ARC2018) was organized

by the Technological Educational Institute of Western Greece, by the Ruhr-Universität,Germany, and by the Technische Universität Dresden, Germany The symposium tookplace at Bellonio Conference Center in Fira, the capital of Santorini in Greece

Luigi Carro UFRGS, Brazil

Chao Wang USTC, China

Dimitrios Soudris NTUA, Greece

Stephan Wong TU Delft, The Netherlands

EU Projects Track Chair

Christos Antonopoulos Technological Educational Institute of Western Greece

Hideharu Amano Keio University, Japan

Jürgen Becker Universität Karlsruhe (TH), Germany

Mladen Berekovic Braunschweig University of Technology, GermanyKoen Bertels Delft University of Technology, The Netherlands

João M P Cardoso University of Porto, Portugal

Katherine (Compton)

Morrow

University of Wisconsin-Madison, USAGeorge Constantinides Imperial College of Science, UK

Pedro C Diniz INESC-ID, Portugal

Philip H W Leong University of Sydney, Australia

Walid Najjar University of California Riverside, USA

Roger Woods The Queen’s University of Belfast, UK

Program Committee

Hideharu Amano Keio University, Japan

Zachary Baker Los Alamos National Laboratory, USA

Jürgen Becker Karlsruhe Institute of Technology, Germany

Mladen Berekovic C3E, TU Braunschweig, Germany

Nikolaos Bellas University of Thessaly, Greece

Neil Bergmann University of Queensland, Australia

Alessandro Biondi Scuola Superiore Sant’Anna, Italy

João Bispo FEUP/Universidade do Porto, Portugal

Michaela Blott Xilinx, Ireland

Vanderlei Bonato University of São Paulo, Brazil

Christos Bouganis Imperial College, UK

João Cardoso FEUP/Universidade do Porto, Portugal

Luigi Carro Instituto de Informática/UFRGS, Brazil

Ray Cheung City University of Hong Kong, SAR China

Daniel Chillet AIRN - IRISA/ENSSAT, France

Steven Derrien Université de Rennes 1, France

Giorgos Dimitrakopoulos Democritus University of Thrace, Greece

Pedro C Diniz INESC-ID, Portugal

António Ferrari Universidade de Aveiro, Portugal

João Canas Ferreira INESC TEC/University of Porto, Portugal

Ricardo Ferreira Universidade Federal de Viçosa, Brazil

Apostolos Fournaris Technological Educational Institute of Western Greece,

GreeceCarlo Galuzzi TU Delft, The Netherlands

Roberto Giorgi University of Siena, Italy

Marek Gorgon AGH University of Science and Technology, PolandFrank Hannig Friedrich-Alexander University Erlangen-Nürnberg,

GermanyJim Harkin University of Ulster, UK

Christian Hochberger TU Darmstadt, Germany

Christoforos Kachris ICCS, Greece

Kimon Karras Think Silicon S.A., Greece

Fernanda Kastensmidt Universidade Federal do Rio Grande do Sul - UFRGS,

BrazilChrysovalantis Kavousianos University of Ioannina, Greece

Tomasz Kryjak AGH University of Science and Technology, Poland

Krzysztof Kepa GE Global Research, USA

Andreas Koch TU Darmstadt, Germany

Stavros Koubias University of Patras, Greece

Dimitrios Kritharidis Intracom Telecom, Greece

Vianney Lapotre Universit de Bretagne-Sud - Lab-STICC, FranceEduardo Marques University of São Paulo, Brazil

Konstantinos Masselos University of Peloponnese, Greece

Cathal Mccabe Xilinx, Ireland

Antonio Miele Politecnico di Milano, Italy

Takefumi Miyoshi e-trees.Japan, Inc., Japan

Walid Najjar University of California Riverside, USA

Horácio Neto INESC-ID/IST/U Lisboa, Portugal

Dimitris Nikolos University of Patras, Greece

Roman Obermeisser University of Siegen, Germany

Kyprianos Papadimitriou Technical University of Crete, Greece

Monica Pereira Universidade Federal do Rio Grande do Norte, BrazilThilo Pionteck Otto-von-Guericke Universität Magdeburg, GermanyMarco Platzner University of Paderborn, Germany

Mihalis Psarakis University of Piraeus, Greece

Kyle Rupnow Advanced Digital Sciences Center, USA

Marco Domenico

Santambrogio

Politecnico di Milano, ItalyKentaro Sano Tohoku University, Japan

Yukinori Sato Tokyo Institute of Technology, Japan

António Beck Filho Universidade Federal do Rio Grande do Sul, BrazilYuichiro Shibata Nagasaki University, Japan

Cristina Silvano Politecnico di Milano, Italy

Dimitrios Soudris NTUA, Greece

Theocharis Theocharides University of Cyprus, Cyprus

George Theodoridis University of Patras, Greece

David Thomas Imperial College, UK

Chao Wang USTC, China

Markus Weinhardt Osnabrück University of Applied Sciences, GermanyTheerayod Wiangtong KMITL, Thailand

Roger Woods Queens University Belfast, UK

Yoshiki Yamaguchi University of Tsukuba, Japan

Additional Reviewers

Dimitris Bakalis University of Patras, Greece

Guilherme Bileki University of São Paulo, Brazil

Ahmet Erdem Politecnico di Milano, Italy

Panagiotis Georgiou University of Ioannina, Greece

Adele Maleki University of Siegen, Germany

Farnam Khalili Maybodi University of Siena, Italy

André B Perina University of São Paulo, Brazil

Marco Procaccini University of Siena, Italy

Jose Rodriguez University of California Riverside, USA

Bashar Romanous University of California Riverside, USA

Leandro Rosa University of São Paulo, Brazil

Skyler Windh University of California Riverside, USA

Vasileios Zois University of California Riverside, USA

Sponsors

The 2018 Applied Reconfigurable Computing Symposium (ARC2018) is sponsoredby:

Machine Learning and Neural Networks

Approximate FPGA-Based LSTMs Under Computation Time Constraints 3Michalis Rizakis, Stylianos I Venieris, Alexandros Kouris,

and Christos-Savvas Bouganis

Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic

for ImageNet Classification 16Jiang Su, Julian Faraone, Junyi Liu, Yiren Zhao, David B Thomas,

Philip H W Leong, and Peter Y K Cheung

Accuracy to Throughput Trade-Offs for Reduced Precision Neural

Networks on Reconfigurable Logic 29Jiang Su, Nicholas J Fraser, Giulio Gambardella, Michaela Blott,

Gianluca Durelli, David B Thomas, Philip H W Leong,

and Peter Y K Cheung

Deep Learning on High Performance FPGA Switching Boards:

Flow-in-Cloud 43Kazusa Musha, Tomohiro Kudoh, and Hideharu Amano

SqueezeJet: High-Level Synthesis Accelerator Design for Deep

Convolutional Neural Networks 55Panagiotis G Mousouliotis and Loukas P Petrou

Efficient Hardware Acceleration of Recommendation Engines:

A Use Case on Collaborative Filtering 67Konstantinos Katsantonis, Christoforos Kachris, and Dimitrios Soudris

FPGA-Based Design and CGRA Optimizations

VerCoLib: Fast and Versatile Communication for FPGAs via PCI Express 81

Oğuzhan Sezenlik, Sebastian Schüller, and Joachim K Anlauf

Lookahead Memory Prefetching for CGRAs Using Partial Loop Unrolling 93Lukas Johannes Jung and Christian Hochberger

Performance Estimation of FPGA Modules for Modular Design

Methodology Using Artificial Neural Network 105Kalindu Herath, Alok Prakash, and Thambipillai Srikanthan

Achieving Efficient Realization of Kalman Filter on CGRA Through

Algorithm-Architecture Co-design 119Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay,

Soumyendu Raha, S K Nandy, and Ranjani Narayan

FPGA-Based Memory Efficient Shift-And Algorithm for Regular

Expression Matching 132Junsik Kim and Jaehyun Park

Towards an Optimized Multi FPGA Architecture with STDM Network:

A Preliminary Study 142Kazuei Hironaka, Ng Anh Vu Doan, and Hideharu Amano

Applications and Surveys

An FPGA/HMC-Based Accelerator for Resolution Proof Checking 153Tim Hansmeier, Marco Platzner, and David Andrews

An Efficient FPGA Implementation of the Big Bang-Big Crunch

Optimization Algorithm 166Almabrok Abdoalnasir, Mihalis Psarakis, and Anastasios Dounis

ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs 178Santhi Natarajan, N KrishnaKumar, Debnath Pal, and S K Nandy

FPGA-Based Parallel Pattern Matching 192Masahiro Fukuda and Yasushi Inoguchi

Embedded Vision Systems: A Review of the Literature 204Deepayan Bhowmik and Kofi Appiah

A Survey of Low Power Design Techniques for Last Level Caches 217Emmanuel Ofori-Attah, Xiaohang Wang, and Michael Opoku Agyeman

Fault-Tolerance, Security and Communication Architectures

ISA-DTMR: Selective Protection in Configurable

Heterogeneous Multicores 231Augusto G Erichsen, Anderson L Sartor, Jeckson D Souza,

Monica M Pereira, Stephan Wong, and Antonio C S Beck

Analyzing AXI Streaming Interface for Hardware Acceleration

in AP-SoC Under Soft Errors 243Fabio Benevenuti and Fernanda Lima Kastensmidt

High Performance UDP/IP 40Gb Ethernet Stack for FPGAs 255Milind Parelkar and Darshan Jetly

Tackling Wireless Sensor Network Heterogeneity Through Novel

Reconfigurable Gateway Approach 269Christos P Antonopoulos, Konstantinos Antonopoulos,

Christos Panagiotou, and Nikolaos S Voros

A Low-Power FPGA-Based Architecture for Microphone Arrays

in Wireless Sensor Networks 281Bruno da Silva, Laurent Segers, An Braeken, Kris Steenhaut,

and Abdellah Touhafi

A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial

Testing and On-chip Sensing 294Lampros Pyrgas and Paris Kitsos

HoneyWiN: Novel Honeycomb-Based Wireless NoC Architecture

in Many-Core Era 304Raheel Afsharmazayejani, Fahimeh Yazdanpanah, Amin Rezaei,

Mohammad Alaei, and Masoud Daneshtalab

Reconfigurable and Adaptive Architectures

Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven

Routing Approach 319Luca Sterpone and Ludovica Bozzoli

A Dynamic Partial Reconfigurable Overlay Framework for Python 331Benedikt Janßen, Florian Kästner, Tim Wingender,

and Michael Huebner

Runtime Adaptive Cache for the LEON3 Processor 343Osvaldo Navarro and Michael Huebner

Exploiting Partial Reconfiguration on a Dynamic Coarse Grained

Reconfigurable Architecture 355Rafael Fão de Moura, Michael Guilherme Jordan,

Antonio Carlos Schneider Beck, and Mateus Beck Rutzig

DIM-VEX: Exploiting Design Time Configurability

and Runtime Reconfigurability 367Jeckson Dellagostin Souza, Anderson L Sartor, Luigi Carro,

Mateus Beck Rutzig, Stephan Wong, and Antonio C S Beck

The Use of HACP+SBT Lossless Compression in Optimizing Memory

Bandwidth Requirement for Hardware Implementation of Background

Modelling Algorithms 379Kamil Piszczek, Piotr Janus, and Tomasz Kryjak

A Reconfigurable PID Controller 392Sikandar Khan, Kyprianos Papadimitriou, Giorgio Buttazzo,

and Kostas Kalaitzakis

Design Methods and Fast Prototyping

High-Level Synthesis of Software-Defined MPSoCs 407Jens Rettkowski and Diana Goehringer

Improved High-Level Synthesis for Complex CellML Models 420

Björn Liebig, Julian Oppermann, Oliver Sinnen, and Andreas Koch

An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System

for Embedded Processors 433Habib ul Hasan Khan, Ahmed Kamal, and Diana Goehringer

Rapid Prototyping and Verification of Hardware Modules Generated

Using HLS 446Julián Caba, João M P Cardoso, Fernando Rincón, Julio Dondo,

and Juan Carlos López

Comparing C and SystemC Based HLS Methods for Reconfigurable

Systems Design 459Konstantinos Georgopoulos, Pavlos Malakonakis,

Nikolaos Tampouratzis, Antonis Nikitakis, Grigorios Chrysos,

Apostolos Dollas, Dionysios Pnevmatikatos, and Ioannis Papaefstathiou

Fast DSE for Automated Parallelization of Embedded

Legacy Applications 471Kris Heid, Jakob Wenzel, and Christian Hochberger

Control Flow Analysis for Embedded Multi-core Hybrid Systems 485Augusto W Hoppe, Fernanda Lima Kastensmidt, and Jürgen Becker

FPGA-Based Design and Applications

A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core

Processors in FPGAs 499Pedro H Exenberger Becker, Anderson L Sartor, Marcelo Brandalero,

Tiago Trevisan Jost, Stephan Wong, Luigi Carro,

and Antonio C Beck

A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency

Scaling for 5G Systems 511

Mário Lopes Ferreira, João Canas Ferreira, and Michael Huebner

Area-Energy Aware Dataflow Optimisation of Visual Tracking Systems 523Paulo Garcia, Deepayan Bhowmik, Andrew Wallace, Robert Stewart,

and Greg Michaelson

Fast Carry Chain Based Architectures for Two’s Complement to CSD

Recoding on FPGAs 537Ayan Palchaudhuri and Anindya Sundar Dhar

Exploring Functional Acceleration of OpenCL on FPGAs and GPUs

Through Platform-Independent Optimizations 551Umar Ibrahim Minhas, Roger Woods, and George Karakonstantis

ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated

Preprocessing and Assembly of Genomic Short Reads 564Santhi Natarajan, N KrishnaKumar, H V Anuchan, Debnath Pal,

Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks

for Quantum Computing Systems 615Johannes Pfau, Shalina Percy Delicia Figuli, Steffen Bähr,

and Jürgen Becker

Reconfigurable IP-Based Spectral Interference Canceller 627Peter Littlewood, Shahnam Mirzaei,

and Krishna Murthy Kattiyan Ramamoorthy

FPGA-Assisted Distribution Grid Simulator 640Nikolaos Tzanis, Grigorios Proiskos, Michael Birbas,

and Alexios Birbas

Analyzing the Use of Taylor Series Approximation in Hardware

and Embedded Software for Good Cost-Accuracy Tradeoffs 647Gennaro S Rodrigues,Ádria Barros de Oliveira,

Fernanda Lima Kastensmidt, and Alberto Bosio

Special Session: Research Projects

CGRA Tool Flow for Fast Run-Time Reconfiguration 661Florian Fricke, André Werner, Keyvan Shahin, and Michael Huebner

Seamless FPGA Deployment over Spark in Cloud Computing:

A Use Case on Machine Learning Hardware Acceleration 673Christoforos Kachris, Ioannis Stamelos, Elias Koromilas,

and Dimitrios Soudris

The ARAMiS Project Initiative: Multicore Systems

in Safety- and Mixed-Critical Applications 685

Jürgen Becker and Falco K Bapp

Mapping and Scheduling Hard Real Time Applications on Multicore

Systems - The ARGO Approach 700Panayiotis Alefragis, George Theodoridis, Merkourios Katsimpris,

Christos Valouxis, Christos Gogos, George Goulas, Nikolaos Voros,

Simon Reder, Koray Kasnakli, Marcus Bednara, David Müller,

Umut Durak, and Juergen Becker

Robots in Assisted Living Environments as an Unobtrusive, Efficient,

Reliable and Modular Solution for Independent Ageing:

The RADIO Experience 712Christos Antonopoulos, Georgios Keramidas, Nikolaos S Voros,

Michael Huebner, Fynn Schwiegelshohn, Diana Goehringer,

Maria Dagioglou, Georgios Stavrinos, Stasinos Konstantopoulos,

and Vangelis Karkaletsis

HLS Algorithmic Explorations for HPC Execution on Reconfigurable

Hardware - ECOSCALE 724Pavlos Malakonakis, Konstantinos Georgopoulos, Aggelos Ioannou,

Luciano Lavagno, Ioannis Papaefstathiou, and Iakovos Mavroidis

Supporting Utilities for Heterogeneous Embedded Image Processing

Platforms (STHEM): An Overview 737Ahmad Sadek, Ananya Muddukrishna, Lester Kalms, Asbjørn Djupdal,

Ariel Podlubne, Antonio Paolillo, Diana Goehringer, and Magnus Jahre

Author Index 751

Machine Learning and Neural Networks

Approximate FPGA-Based LSTMs Under

Computation Time Constraints

Michalis Rizakis(B), Stylianos I Venieris , Alexandros Kouris ,

and Christos-Savvas Bouganis

Department of Electrical and Electronic Engineering,

Imperial College London, London, UK

{michail.rizakis14,stylianos.venieris10,a.kouris16,

christos-savvas.bouganis}@imperial.ac.uk

Abstract Recurrent Neural Networks, with the prominence of Long

Short-Term Memory (LSTM) networks, have demonstrated art accuracy in several emerging Artificial Intelligence tasks Neverthe-less, the highest performing LSTM models are becoming increasinglydemanding in terms of computational and memory load At the sametime, emerging latency-sensitive applications including mobile robots andautonomous vehicles often operate under stringent computation timeconstraints In this paper, we address the challenge of deploying com-putationally demanding LSTMs at a constrained time budget by intro-ducing an approximate computing scheme that combines iterative low-rank compression and pruning, along with a novel FPGA-based LSTMarchitecture Combined in an end-to-end framework, the approximationmethod parameters are optimised and the architecture is configured

state-of-the-to address the problem of high-performance LSTM execution in constrained applications Quantitative evaluation on a real-life imagecaptioning application indicates that the proposed system required up to6.5× less time to achieve the same application-level accuracy compared

under the same computation time constraints

Recurrent Neural Networks (RNNs) is a machine learning model which offersthe capability of recognising long-range dependencies in sequential and temporaldata RNN models, with the prevalence of Long Short-Term Memory (LSTMs)networks, have demonstrated state-of-the-art performance in various AI appli-cations including scene labelling [1] and image generation [2] Moreover, LSTMshave been successfully employed for AI tasks in complex environments includinghuman trajectory prediction [3] and ground classification [4] on mobile robots,with more recent systems combining language and image processing in taskssuch as image captioning [5] and video understanding [6]

c

 Springer International Publishing AG, part of Springer Nature 2018

N Voros et al (Eds.): ARC 2018, LNCS 10824, pp 3–15, 2018.

4 M Rizakis et al.

Despite the high predictive power of LSTMs, their computational and ory demands pose a challenge with respect to deployment in latency-sensitiveand power-constrained environments Modern intelligent systems such as mobilerobots and drones that employ LSTMs to perceive their surroundings often oper-ate under time-constrained, latency-critical settings In such scenarios, retrievingthe best possible output from an LSTM given a constraint in computation timemay be necessary to ensure the timely operation of the system Moreover, therequirements of such applications for low absolute power consumption, whichwould enable a longer battery life, prohibit the deployment of high-performance,but power-hungry platforms, such as multi-core CPUs and GPUs In this context,FPGAs constitute a promising target device that can combine customisation andreconfigurability to achieve high performance at a low power envelope

mem-In this work, an approximate computing scheme along with a novel hardwarearchitecture for LSTMs are proposed as an end-to-end framework to address theproblem of high-performance LSTM deployment in time-constrained settings.Our approach comprises an iterative approximation method that applies simul-taneously low-rank compression and pruning of the LSTM model with a tunablenumber of refinement iterations This iterative process enables our framework to(i) exploit the resilience of the target application to approximations, (ii) explorethe trade-off between computational and memory load and application-levelaccuracy and (iii) execute the LSTM under a time constraint with increasingaccuracy as a function of computation time budget At the hardware level, oursystem consists of a novel FPGA-based architecture which exploits the inherentparallelism of the LSTM, parametrised with respect to the level of compressionand pruning By optimising the parameters of the approximation method, theproposed framework generates a system tailored to the target application, theavailable FPGA resources and the computation time constraints To the best ofour knowledge, this is the first work in the literature to address the deployment

of LSTMs under computation time constraints

2.1 LSTM Networks

A vanilla RNN typically processes an input and generates an output at eachtime step Internally, the network has recurrent connections from the output atone time step to the hidden units at the next time step which enables it to cap-ture sequential patterns The LSTM model differs from vanilla RNNs in that itcomprises control units named gates, instead of layers A typical LSTM has four

gates The input gate (Eq (1)), along with the cell gate (Eq (4)) are responsiblefor determining how much of the current input will propagate to the output The

the LSTM will be forgotten or not, while the output gate (Eq (3)) determineshow much of the current state will be allowed to propagate to the final output ofthe LSTM at the current time step Computationally, the gates are matrix-vector

Approximate FPGA-Based LSTMs Under Computation Time Constraints 5

multiplication blocks, followed by a nonlinear elementwise activation function.The equations for the LSTM model are shown below:

i (t) , f (t) and o (t) are the input, forget and output gates respectively, c (t)

is the current state of the LSTM, h (t−1) is the previous output, x (t) is thecurrent input at timet and σ(·) represents the sigmoid function Equation (5) isfrequently found in the literature ash (t)=c (t)  tanh(o (t)) withtanh(·) applied

to the output gate In this work, we follow the image captioning LSTM proposed

in [5] which removes thetanh(·) from the output gate and therefore we end up

with Eq (5) Finally, all theW matrices denote the weight matrices that contain

the trainable parameters of the model, which are assumed to be provided

The effectiveness of RNNs has attracted the attention of the architecture andreconfigurable computing communities Li et al [7] proposed an FPGA-basedaccelerator for the training of an RNN language model In [8], the authors focus

on the optimised deployment of the Gated Recurrent Unit (GRU) model [9] indata centres with server-grade FPGAs, ASICs, GPUs and CPUs and propose analgorithmic memoisation-based method to reduce the computational load at theexpense of increased memory footprint The authors of [10] present an empir-ical study of the effect of different architectural designs on the computationalresources, on-chip memory capacity and off-chip memory bandwidth require-ments of an LSTM model Finally, Guan et al [11] proposed an FPGA-basedLSTM accelerator optimised for speech recognition on a Xilinx VC707 FPGAplatform

From an algorithmic perspective, recent works have followed a hardware co-design approach Han et al [12] proposed an FPGA-based speechrecognition engine that employs a load-balance-aware compression scheme inorder to compress the LSTM model size Wang et al [13] presented a methodthat addresses compression at several levels including the use of circulant matri-ces for three of the LSTM gates and the quantisation of the trained parameters,together with the corresponding ASIC-based hardware architecture Zhang et al.[14] presented an FPGA-based accelerator for a Long-Term Recurrent Convo-lutional Network (LRCN) for video footage description that consists of a CNNfollowed by an LSTM Their design focuses on balancing the resource allocationbetween the layers of the LRCN and pruning the fully-connected and LSTMlayers to minimise the off-chip memory accesses [12–14] deviate from the faith-ful LSTM mapping of previous works but also require a retraining step in order

model-6 M Rizakis et al.

to compensate for the introduced error of each proposed method Finally, Heand Sun [15] focused on CNNs and investigated algorithmic strategies for modelselection under computation time constraints for both training and testing.Our work differs from the majority of existing efforts by proposing a hardwarearchitecture together with an approximate computing method for LSTMs that

is application-aware and tunable with respect to the required computation timeand application-level error Our framework follows the same spirit as [12–14]

by proposing an approximation to the model, but in contrast to these methodsdoes not require a retraining phase and assumes no access to the full training set.Instead, with a limited subset of labelled data, our scheme compensates for theinduced error by means of iterative refinement, making it suitable for applica-tions where the dataset is privacy-critical and the quality of the approximationimproves as the time availability increases

In this section, the main components of the proposed framework are presented(Fig.1) Given an LSTM model with its set of weight matrices and a small appli-cation evaluation set, the proposed system searches for an appropriate approx-imation scheme that meets the application’s needs, by applying low-rank com-pression and pruning on the model The design space is traversed by means of aroofline model to determine the highest performing configuration of the proposedarchitecture on the target FPGA In this manner, the trade-off between com-putation time and application-level error is explored for different approximationschemes The design point to be implemented on the device is selected based onuser-specified requirements for the maximum computation time or application-level error tolerance

Fig 1 Design flow of the proposed framework

Approximate FPGA-Based LSTMs Under Computation Time Constraints 7

Low-rank approximation Based on the set of LSTM Eqs (1)–(4), each gateconsists of two weight matrices corresponding to the current input and previousoutput vectors respectively In our scheme, we construct an augmented matrix

by concatenating the input and output weight matrices as shown in Eq (7).Similarly, we concatenate the input and previous output vectors (Eq (6)) andthus the overall gate computation is given by Eq (8)

where nonlin(·) is either the sigmoid function σ(·) or tanh(·) In this way, a

single weight matrix is formed for each gate, denoted by W i ∈ R R×C for the

i thgate We perform a full SVD decomposition on the four augmented matricesindependently as W i =U i Σ i V T

by keeping the singular vectors that correspond to the largest singular value

Pruning by means of network sparsification The second level of

approx-imation on the LSTM comprises the structured pruning of the connectivitybetween neurons With each neural connection being captured as an element

of the weight matrices, we express network pruning as sparsification applied

on the augmented weight matrices (Eq (7)) To represent a sparse LSTM, weintroduce four binary mask matrices F i ∈ {0, 1} R×C, ∀i ∈ [1, 4], with each

entry representing whether a connection is pruned or not Overall, we employthe following notation for a (weight, mask) matrix pair{W i , F i | i ∈ [1, 4]}.

In the proposed scheme, we explore sparsity with respect to the connectionsper output neuron and constrain each output to have the same number of inputs

We cast LSTM pruning as an optimisation problem of the following form

8 M Rizakis et al.

entries in a vector The solution to the optimisation problem in Eq (9) is given

by keeping the NZ elements on each row ofW i with the highest absolute valueand setting their indices to 1 inF i

In contrast to the existing approaches, the proposed pruning method doesnot employ retraining and hence removes the computationally expensive step

of retraining and the requirement for the training set, which is important forprivacy-critical applications Even though our sparsification method does notexplicitly capture the impact of pruning on the application-level accuracy, ourdesign space exploration, detailed in Sect.5, searches over different levels of spar-sity and as a result it explores the effect of pruning on the application

Hybrid compression and pruning By applying both low-rank

approxima-tion and pruning, we end up with the following weight matrix approximaapproxima-tion:

In this setting, for the i th gate the ranking of the absolute values in each row

of the rank-1 approximationσ i

1 )T x˜(t)

(12)

In order to obtain a refinement mechanism, we propose an iterative algorithm,presented in Algorithm 1, that employs both the low-rank approximation andpruning methods to progressively update the weight matrix On lines 4–6 thefirst approximation of the weight matrix is constructed by obtaining the rank-1approximation of the original matrix and applying pruning in order to have NZnon-zero elements on each row, as in Eq (11) Next, the weight matrix is refined

its pruned rank-1 approximation as an update (line 15)

Different combinations of levels of sparsity and refinement iterations respond to different design points in the computation-accuracy space In thisrespect, the number of non-zero elements in each binary mask vector and thenumber of iterations are exposed to the design space exploration as tunableparameters (NZ,N steps) to explore the LSTM computation-accuracy trade-off

cor-4.2 Architecture

The proposed FPGA architecture for LSTMs is illustrated in Fig.2 The mainstrategy of the architecture includes the exploitation of the coarse-grained par-allelism between the four LSTM gates and is parametrised with respect to the

Approximate FPGA-Based LSTMs Under Computation Time Constraints 9

Algorithm 1 Iterative LSTM Model Approximation

Inputs:

2: Number of non-zero elements, NZ

u i(0)1 , σ i(0)1 , v i(0)1 = SVD(W i)

5: f i(0) ← solution to Eq (9) for vector v i(0)1

u i(n)1 , σ1i(n) , v i(n)1 = SVD(E)1

13: f i(n) ← solution to optimisation problem (9) for vector v i(n)1

-15: W(n) i = W (n−1) i +σ1i(n) u i(n)1 f i(n)  v i(n)1 T

17: end for

fine-grained parallelism in the dot-product and elementwise operations of theLSTM, allowing for a compile-time tunable performance-resource trade-off

SVD and Binary Masks Precomputation In Algorithm 1, the number ofrefinement iterations (N steps), the level of sparsity (NZ) and the trained weightmatrices are data-independent and known at compile time As such, the requiredSVD decompositions along with the corresponding binary masks are precom-puted for all N steps iterations at compile time As a result, the singular values

σ i(n)

1 , the vectorsu i(n)

1 and only the non-zero elements of the sparsef i(n) v i(n)

1

are stored in the off-chip memory, so that they can be looked-up at run time

Inter-gate and Intra-gate Parallelism In the proposed architecture, each

gate is allocated a dedicated hardware gate unit with all gates operating in

parallel At each LSTM time-step t, a hardware gate unit computes its output

by performing N steps refinement iterations as in Eq (12) At the beginning ofthe time-step, the current vector ˜x (t)is stored on-chip as it will be reused in eachiteration by all four gates The vectors u i(n)

10 M Rizakis et al.

Fig 2 Diagram of proposed hardware architecture

memory in a tiled manner.u i(n)

1 are tiled with tile sizes ofT r andT c

respectively, leading to T R

r and T C

c tiles sequentially streamed in the architecture

At each gate, a dot-product unit is responsible for computing the dot product

of the current tile ofv i(n)

1 with the corresponding elements of the input ˜x (t) Thedot-product unit is unrolled by a factor ofT cin order to process one tile ofv i(n)

1

per cycle After accumulating the partial results of all the C

T c tiles, the result isproduced and multiplied with the scalarσ i(n)

1 The multiplication result is passed

as a constant operand to a multiplier array, withu i(n)

1 as the other operand Themultiplier array has a size ofT r in order to match the tiling ofu i(n)

1 As a finalstage, an array of T r accumulators performs the summation across the N steps

iterations as expressed in Eq (12), to produce the final gate output

The outputs from the input, forget and output gates are passed through a sigmoid unit while the output of the cell gate is passed through a tanh unit.

After the nonlinearities stage, the produced outputs are multiplied element as dictated by the LSTM equations to produce the cell state c (t) (Eq.(4)) and the current output vectorh (t)(Eq (5)) The three multiplier arrays andthe one adder array all have a size ofT r to match the tile size of the incomingvectors and exploit the available parallelism

Having parametrised the proposed approximation method over NZ andN steps

and its underlying architecture over NZ and tile sizes (T r, T c), correspondingmetrics need to be employed for exploring the effects of each parameter on perfor-mance and accuracy The approximation method parameters are studied based

on an application-level evaluation metric (discussed in Sect.5.2), that measuresthe impact of each applied approximation on the accuracy of the target appli-cation In terms of the hardware architecture, roofline performance modelling isemployed for exhaustively exploring the design space formed by all possible tilesize combinations, to obtain the highest performing design point (discussed inSect.5.1) Based on those two metrics, the computation time-accuracy trade-off

is explored

Approximate FPGA-Based LSTMs Under Computation Time Constraints 11

5.1 Roofline Model

The design space of architectural configurations for all tile size combinations

of T r and T c is explored exhaustively by performance modelling The rooflinemodel [17] is used to develop a performance model for the proposed architecture

by relating the peak attainable performance (in terms of throughput), for eachconfiguration on a particular FPGA device, with its operational intensity, whichrelates the ratio of computational load to off-chip memory traffic Based on thismodel, each design point’s performance can be bounded either by the peak plat-form throughput or by the maximum performance that the platform’s memorysystem can support In this context, roofline models are developed for predictingthe maximum attainable performance for varying levels of pruning (NZ).Given a tile size pair, the performance of the architecture is calculated as:

max(N steps max( Tr R , NZ Tc ), 37 Tr R)clk (13)where each gate performs 2NZ+2R+1 operations per iteration and 37R accounts

for the rest of the operations to produce the final outputs The initiation interval

the computations Similarly, a gate’s initiation interval depends on the slowestbetween the dot-product unit and the multiplier array (Fig.2)

Respectively, the operational intensity of the architecture, also referred to inthe literature as Computation-to-Communication ratio (CTC), is formulated as:

CT C(ops/byte) = mem access(bytes) operations(ops) =4N steps(2NZ + 2R + 1) + 37R

where the memory transfers include the singular vectors and the singular valuefor each iteration of each gate and the write-back of the output and the cell statevectors to the off-chip memory The augmented input vector ˜x (t) is stored on-chip in order to be reused across the N stepsiterations All data are representedwith a single-precision floating-point format and require four bytes

The number of design points allows enumerating all possible tile size nations for each number of non-zero elements and obtaining the performance andCTC values for the complete design space Based on the target platform’s peakperformance, memory bandwidth and on-chip memory capacity, the subspacecontaining the platform-supported design points is determined The proposedarchitecture is implemented by selecting the tile sizes (T r, T c) that correspond

combi-to the highest performing design point within that subspace

5.2 Evaluating the Impact of Approximations on the Application

The proposed framework requires a metric that would enable measuring theimpact of the applied approximations on the application-level accuracy for dif-ferent (NZ, N steps) pairs In our methodology, the error induced by our approx-imation methods is measured by running the target application end-to-end over

12 M Rizakis et al.

an evaluation set with both the approximated weight matrices given a selected

model By treating the output of the reference model as the ground truth, anapplication-specific metric is employed that assesses the quality of the outputthat was generated by the approximate model, exploring in this way the rela-tionship between the level of approximation and the application-level accuracy

The image captioning system presented by Vinyals et al [5] (winner of the 2015MSCOCO challenge) is examined as a case study for evaluating the proposedframework Input images are encoded by a CNN and fed to a trained LSTMmodel to predict corresponding captions In the proposed LSTM, each gate con-sists of twoR×R weight matrices, leading to a (R×C) augmented weight matrix

per gate withR = 512 and C = 2R, for a total of 2.1 M parameters To determine

the most suitable approximation scheme, we use a subset of the validation set

of the Common Objects in Context (COCO) dataset1, consisting of 35 images

To obtain image captions that will act as ground truth for the evaluation of theproposed approximation method, the reference image captioning application isexecuted end-to-end over the evaluation set, using TensorFlow2 As a metric ofthe effect of low-rank approximation and pruning on the LSTM model, we selectBilingual Evaluation Understudy (BLEU) [18], which is commonly employedfor the evaluation of machine translation’s quality by measuring the number

of matching words, or “blocks of words”, between a reference and a candidatetranslation Due to space limitations, more information about adopting BLEU

as a quality metric for image captioning can be found in [5]

Experimental Setup In our experiments, we target the Xilinx Zynq ZC706

board All hardware designs were synthesised and placed-and-routed with XilinxVivado HLS and Vivado Design Suite (v17.1) with a clock frequency of 100 MHz.Single-precision floating-point representation was used in order to comply withthe typical precision requirements of LSTMs as used by the deep learning com-munity Existing work [7,12] has studied precision optimisation in specific LSTMapplications, which constitutes a complementary method to our framework as

an additional tunable parameter for the performance-accuracy trade-off

Baseline Architecture A hardware architecture of a faithful implementation

of the LSTM model is implemented to act as a baseline for the proposed system’sevaluation This baseline architecture consists of four gate units, implemented inparallel hardware, that perform matrix-vector multiplication in a tiled manner.Parametrisation with respect to the tiling along the rows (T r) and columns (T c)

of the weight matrices is applied to this architecture and roofline modelling

is used to obtain the highest performing configuration (T r, T c), similarly tothe proposed system’s architecture (Fig.3) The maximum platform-supported

Approximate FPGA-Based LSTMs Under Computation Time Constraints 13

attainable performance was obtained for T r= 2 and T c= 1, utilising 308 DSPs(34%), 69 kLUTs (31%), 437 kFFs (21%) and 26 18 kbit BRAMs (2%) As Fig.3

demonstrates, the designs are mainly memory bounded and as a result not allthe FPGA resources are utilised To obtain the application-level accuracy of thebaseline design under time constrained scenarios, the BLEU of the intermediateLSTM output at each tile step of T r is examined (Fig.4)

Fig 3 Roofline model of the proposed and baseline architectures on the ZC706 board

6.1 Comparisons at Constrained Computation Time

This section presents the gains of using the proposed methodology compared tothe baseline design under computation time constraints This is investigated byexploring the design space, defined by (NZ,T r,T c), in terms of (i) performance(Fig.3) and (ii) the relationship between accuracy and computation time (Fig.4)

As shown in Fig.3, as the level of pruning increases and NZ becomes smaller,the computational and memory load per refinement iteration becomes smallerand the elementwise operations gradually dominate the computational intensity(Eq (14)), with the corresponding designs moving to the right of the rooflinegraph With respect to the architectural parameters, as the tiling parametersT r

and T c increase, the hardware design becomes increasingly unrolled and movestowards the top of the roofline graph In all cases, the proposed architecturedemonstrates a higher performance compared to the baseline design reaching

up to 3.72× for a single non-zero element with an average of 3.35× (3.31× geo.

mean) across the sparsity levels shown in Fig.3

To evaluate our methodology in time-constrained scenarios, for each sity level the highest performing design of the roofline model is implemented.Figure4 shows the achieved BLEU score of each design over the evaluation setwith respect to runtime, where higher runtime translates to higher number ofrefinements In this context, for the target application the design with 512 non-zero elements (50% sparsity) achieves the best trade-off between performanceper refinement iteration and additional information obtained at each iteration.The highest performing architecture with NZ of 512 has a tiling pair of (32, 1)

spar-14 M Rizakis et al.

Fig 4 BLEU scores over time for all methods

and the implemented design consumes 862 DSPs (95%), 209 kLUTs (95%), 437kFFs (40%) and 34 18kbit BRAMs (3%) In the BLEU range between 0.4 and0.8, our proposed system reaches the corresponding BLEU decile up to 6.51×

faster with an average speedup of 4.19× (3.78× geo mean) across the deciles.

As demonstrated in Fig.4, the highest performing design of the proposedmethod (NZ = 512) constantly outperforms the baseline architecture in terms

of BLEU score at every time instant up to 2.7 ms, at which a maximum BLEUvalue of 0.9 has been achieved by both methods As a result, given a specific timebudget below 2.7 ms, the proposed architecture achieves a 24.88× higher BLEU

score (geo mean) compared to the baseline Moreover, the proposed methoddemonstrates significantly higher application accuracy during the first 1.5 ms

of the computation, reaching up to 31232× higher BLEU In this respect, our

framework treats a BLEU of 0.9 and a time budget of 2.7 ms as switching points

to select between the baseline and the architecture that employs the proposedapproximation method and deploys the highest performing design for each case

The high-performance deployment of LSTMs under stringent computation timeconstraints poses a challenge in several latency-critical applications This paperpresents a framework for mapping LSTMs on FPGAs in such scenarios The pro-posed methodology applies an iterative approximate computing scheme in order

to compress and prune the target network and explores the computation accuracy trade-off A novel FPGA architecture is proposed that is tailored to thedegree of approximation and optimised for the target device This formulationenables the co-optimisation of the LSTM approximation and the architecture

time-in order to satisfy the application-level computation time constratime-ints Futurework includes the extension of the proposed methodology to scenarios where thetraining data are available to perform retraining, leading to even higher gains

Approximate FPGA-Based LSTMs Under Computation Time Constraints 15

Acknowledgements The support of the EPSRC Centre for Doctoral Training in

High Performance Embedded and Distributed Systems (HiPEDS, Grant ReferenceEP/L016796/1) is gratefully acknowledged This work is also supported by EPSRCgrant 1507723

5 Vinyals, O., Toshev, A., Bengio, S., Erhan, D.: Show and tell: lessons learned from

the 2015 MSCOCO image captioning challenge TPAMI 39, 652–663 (2017)

6 Donahue, J., et al.: Long-term recurrent convolutional networks for visual

recog-nition and description TPAMI 39(4), 677–691 (2017)

7 Li, S., Wu, C., Li, H., Li, B., Wang, Y., Qiu, Q.: FPGA acceleration of recurrentneural network based language model In: FCCM, pp 111–118 (2015)

8 Nurvitadhi, E., et al.: Accelerating recurrent neural networks in analytics servers:comparison of FPGA, CPU, GPU, and ASIC In: FPL, pp 1–4 (2016)

9 Chung, J., et al.: Empirical evaluation of gated recurrent neural networks onsequence modeling In: NIPS Workshop on Deep Learning (2014)

10 Chang, A.X.M., Culurciello, E.: Hardware accelerators for recurrent neural works on FPGA In: ISCAS, pp 1–4 (2017)

net-11 Guan, Y., Yuan, Z., Sun, G., Cong, J.: FPGA-based accelerator for long short-termmemory recurrent neural networks In: ASP-DAC, pp 629–634 (2017)

12 Han, S., et al.: ESE: efficient speech recognition engine with sparse LSTM onFPGA In: FPGA, pp 75–84 (2017)

13 Wang, Z., Lin, J., Wang, Z.: Accelerating recurrent neural networks: a

memory-efficient approach TVLSI 25(10), 2763–2775 (2017)

14 Zhang, X., et al.: High-performance video content recognition with long-term rent convolutional network for FPGA In: FPL, pp 1–4 (2017)

recur-15 He, K., Sun, J.: Convolutional neural networks at constrained time cost In: CVPR(2015)

16 Denil, M., Shakibi, B., Dinh, L., Ranzato, M.A., de Freitas, N.: Predicting eters in deep learning In: NIPS, pp 2148–2156 (2013)

param-17 Williams, S., et al.: Roofline: an insightful visual performance model for multicore

architectures Commun ACM 52(4), 65–76 (2009)

18 Papineni, K., Roukos, S., Ward, T., Zhu, W.-J.: BLEU: a method for automaticevaluation of machine translation In: ACL, pp 311–318 (2002)

Redundancy-Reduced MobileNet

Acceleration on Reconfigurable Logic

for ImageNet Classification

Jiang Su1,2(B), Julian Faraone1,2, Junyi Liu1,2, Yiren Zhao1,2,

David B Thomas1,2, Philip H W Leong1,2, and Peter Y K Cheung1,2

1Imperial College London, London, UK

j.su13@ic.ac.uk

Abstract Modern Convolutional Neural Networks (CNNs) excel in

image classification and recognition applications on large-scale datasetssuch as ImageNet, compared to many conventional feature-based com-puter vision algorithms However, the high computational complexity ofCNN models can lead to low system performance in power-efficient appli-cations In this work, we firstly highlight two levels of model redundancywhich widely exist in modern CNNs Additionally, we use MobileNet as adesign example and propose an efficient system design for a Redundancy-Reduced MobileNet (RR-MobileNet) in which off-chip memory traffic isonly used for inputs/outputs transfer while parameters and intermedi-ate values are saved in on-chip BRAM blocks Compared to AlexNet, our

inference but 9%/5.2% higher Top1/Top5 classification accuracy on geNet classification task The latency of a single image inference is only7.85 ms

Algorithm acceleration

Modern CNNs have achieved unprecedented success in large-scale image tion tasks In order to obtain higher classification accuracy, researchers proposedCNN models with increasing complexity The high computational complexitypresent challenges for power-efficient hardware platforms like FPGAs mainly due

recogni-to the high memory bandwidth requirement On one hand, the large amount

of parameters leads to an inevitably off-chip memory storage Together withinputs/outputs and intermediate computation results, current FPGA devicesstruggle to provide enough memory bandwidth for sufficient system parallelism

On the other hand, the advantages of the large amount of flexible on-chip ory blocks are not sufficiently explored as they are mostly used as data buffers

mem-c

 Springer International Publishing AG, part of Springer Nature 2018

N Voros et al (Eds.): ARC 2018, LNCS 10824, pp 16–28, 2018.

RR-MobileNet Acceleration on FPGA 17

which have to match with off-chip memory bandwidth In this work, we addressthis problem by reducing CNN redundancy so that the model is small enough

to fit on-chip and our hardware system can benefit from the high bandwidth ofFPGA on-chip memory blocks

There are existing works that have explored redundancy in CNNs on level and data-level separately Model-level redundancy leads to redundantparameters which barely contribute to model computation For example, atrained AlexNet may have 20% to 80% kernels with very low values and thecomputation can be removed with very limited effect to the final classificationaccuracy [1] Data-level redundancy, on the other hand, refers to unnecessarilyhigh precision for data representation to parameters However, there are verylimited work that quantitatively consider both redundancy at the same time,especially in a perspective of their impacts to a hardware system design Thecontributions of this work is as follows:

model-– We consider both model-level and data-level redundancy, which widely exist

in CNNs, in hardware system design A quantitative analysis is conducted toshow the hardware impacts of both types of redundancy and their cooperativeeffects

– We demonstrate the validity of the proposed redundancy reduction analysis

by applying it to a recent CNN model called MobileNet Compared to abasedline AlexNet model, our RR-MobileNet has 25× less parameters, 3.2×

less operations per image computation but 9% and 5.2% higher Top1/Top5accuracy on ImageNet classification

– An FPGA based system architecture is designed for our RR-MobileNet modelwhere all parameters and intermediate numbers can be stored with on-chipBRAM blocks Therefore, the peak memory bandwidth within the system canachieve 1.56 Tb/s As a result, our system costs only 7.85 ms on each imageinference computation

About this topic, several works have explored in one perspective or another

In terms of data-level redundancy, [2 4] and several other works explores FPGAbased acceleration system for CNN models with fixed point parameters and acti-vation values But model-level redundancy is not considered for further through-put improvement On the other side, works like [1,5] explored model-level redun-dancy in CNN hardware system design, but these works are presented withoutquantitative discussion about hardware impacts of reduced-precision parame-ters used in CNN models In this work, we consider both types of redundancyand report our quantitative consideration for a MobileNet acceleration systemdesign

The two-level redundancy in neural networks and its impacts to hardwaresystem design are introduced in Sect.2 Section3 introduces an FPGA systemdesign for our Redundancy-Reduced MobileNet for ImageNet classification tasks.The experimental results are discussed in Sects.4 and 5 finally concludes thepaper

2.1 MobileNet Complexity Analysis

MobileNet [6] is a recent CNN model that aims to present decent classificationaccuracy with reduced amount of parameters compared to CNN models withconventional convolutional (Conv) layers Figure1 shows the building blocks ofMobileNet called depthwise separable convolutional (DSC) layer, which consist

of a depthwise convolutional (DW Conv) layer and a pointwise convolutional

(PW Conv) layer A DW Conv layer has a K ×K ×N kernel which is essentially

consist of a K × K kernel for each Input Feature Map (IFM) channel So 2

dimensional convolutions are conducted independently in a channel-wise manner.Differently, PW Conv layer is a special case of a general Conv layer and it haskernel size of 1× 1 × N × M while a general Conv layer may have kernels with

a more general size of K × K × N × M MobileNet models, as shown in Table2,can be formed by several general Conv layers and mostly DSC layers

Input Feature Maps Output Feature Maps

(PW_Conv layers)

Fig 1 Tilling in depthwise separable layer for MobileNet

For a general Conv layer, below equations show the resulting operation count

C Conv and parameter amount P Conv given that a IFM is I ×I×N and an Output

Feature Map (OFM) size is O × O × M:

where 2 in Eq.1 indicates that we consider either a single multiplication or

an addition as a fundamental operation in this work On the other side, theoperation count and parameter amount of a DSC layer are as listed below:

RR-MobileNet Acceleration on FPGA 19

(2)

As shown in Eq.2, the amount of parameters in a DSC layer is an addition ofthe parameters in both DW Conv and PW Conv layers In practice, a DSC layer

has a parameter complexity of O(n3) while a Conv layer has O(n4) and this leads

to a much smaller model for MobileNet compared to conventional CNNs [6]

2.2 Model-Level Redundancy Analysis

As mentioned in Sect.1, there are several works that address model-level dancy, we use an iterative pruning strategy Firstly, a quantization training pro-cess, which will be shortly described in Algorithm1, is conducted on the baselineMobileNet model (Table2) Then, an iterative pruning and re-training process

redun-is conducted In each iteration of such process, P rune( ∗) is applied to remove

the model kernels according to β by layer-wisely thresholding the kernels values.

Noticeably, our iterative pruning process is similar to strategy in [7] However,

in our strategy, a kernel is either removed or kept as a whole according to thesummation of its values rather than turning it into a sparse kernel This is calledkernel-level pruning in [8] By doing such structured pruning, we avoid usingextra hardware resources to build sparse matrix formatting modules as needed

in unstructured pruning strategies [5] Finally, each pruning step inevitably leads

to model accuracy loss although only less important kernels are removed So weconduct re-training to compensate the lost model accuracy

What pruning essentially does is changing M in Eqs.1 and 2 to β × M.

Correspondingly, such kernel pruning leads to a reduction of sizes of the OFMand kernels, which results in a smaller memory requirement to hardware For

example, β l is the pruning rate of l-th layer Kernel parameters are represented by

DW p -bit numbers while feature maps are represented by DW a-bit numbers For

a pruned Conv layer, the memory footprint required to store kernel parameters

M em p l is as below:

While to an SDC layer, the memory footprint is changed to following:

Equation4 implies that the reduced parameters in the DW Conv of a DSC

layer is determined by the pruning rate of its preceding layer β l−1 while the

PW Conv layer memory saving is from β l Specially, β0 is 1 for the input layer

Meanwhile, the memory footprint for storing IFMs M em I

portion of β The reduced operation counts can be illustrated by Eqs.1 and 2

20 J Su et al.

with M displaced by its discounted value M ∗ β when calculating C Conv and

C DSC separately for Conv and DSC layers

In the next part, we will show the relationship between data-level redundancyand above-mentioned model-level redundancy as well as their cooperative effects

to the hardware resources

2.3 Data-Level Redundancy Analysis

Data-level redundancy studied in this work, mainly aims to use reduced-precisionparameters to replace their high-precision alternatives such as single/double-precision floating numbers that are widely used in CPU/GPU computing plat-forms Instead, we explore fixed point representations with arbitrary bitwidthfor parameters and activation values and quantitatively analyse their hardwareimpacts Firstly, we introduce our quantization training strategy in Algorithm

2, which is used in this work for training reduced-precision neural networks.Specially, the training procedure is completed off-line with GPU platforms.Only the trained model with reduced-precision parameters is loaded to ourFPGA system for inference computation, which is the focus of this work

Algorithm 1 Quantization Training Process for A L-layer neural network

θ, maximum iteration number MaxIter, lower bound value min, upper bound value max.

RR-MobileNet Acceleration on FPGA 21

values, or activations, a are quantized before actual computations during ence The Quantize( ∗) function converts real values to the nearest pre-defined

infer-fixed point representation layer f orward( ∗) conducts the inference

computa-tion we described in Sect.2.1

In backward propagation, parameters are updated with the gradient in terms

of the quantized weights g W Qso that the network learns to do classification withthe quantized parameters However, the updating is applied to the real-valued

weights W rather than their quantized alternatives W Qso that the training error

can be reserved in higher precision during training Additionally, Clip( ∗) helps

the training to provide the quantized parameters within a particular range wherevalues can be presented by a pre-defined fixed point representation Concretedata representation will be introduced in Sect.4 At last, we use the same hyper-parameters for training provided by [9]

Particularly, our iterative pruning and quantization training strategy rithm 1) is different from the pruning and weight sharing method proposed in[7] in several ways Their method highlights weight sharing rather than changingthe data representation Their iterative training for pruning purposes is a sepa-rate process before weight sharing while in our approach, we do iterative pruningtogether with quantization training process so that model-level and data-levelredundancy are both considered during training

(Algo-Above training process eventually generates a model with fixed point

rep-resentations for parameters and feature map values represented with DW p  and

DW a  bits separately So the memory ratio between a pruned value and the its

high-precision alternative are α p = DW p  /DW p and α a = DW a  /DW a Based onEqs.3 4, the memory requirement for parameters after removing both model-level and data-level redundancy is shown below for Conv layers:

We refer α as data-level memory saving factor and β as model-level memory

saving factor These two factors affects memory requirement for parameters in

a multiplication way (Eqs.6 8) This effect can be represented as a final saving

factor of α p × β l−1 for DW Conv and α p × β l for PW Conv and general Convlayers as shown in Eqs.6 and 7 Similarly, feature map values are affected by

a factor of α a × β l−1 for IFMs and α a × β l for OFMs as shown in Eq.8 InSect.4, we will further show that the cooperative effects of α and β are vital to

our FPGA hardware architecture implementation on FPGA that provides highsystem performance

22 J Su et al.

Based on the model-level and data-level redundancy analysis in the preceding

sections, we introduce in this part what values of α and β can lead to a

high-performance architecture design In this work, we aim to achieve On-Chip ory (OCM) storage for both parameters and feature map values This can beachieved only with careful memory system design which is supported by a corre-sponding redundancy removal strategy Firstly, we introduce the building blockmodule design Next, we show the conditions its memory system design shouldsatisfy in order to implement the architecture within given FPGA resources

Mem-3.1 System Architecture

We design a loop-back architecture, which processes our RR-MobileNet modellayer by layer Only neural network inputs, such as images, and the classificationresults are transferred to external of the programmable logic So all parameters,feature maps and intermediate values are stored on FPGA OCM resources Theoverall system architecture is shown in Fig.2

Ext Memory

DW

RAM

PW RAM

Fig 2 System architecture design for RR-MobileNet

Network inputs are stored in external memory and streamed into our eration system by DMA through AXI bus After Computation, the classificationresults are transfered back to the external memory for further usage Withinthe system on the programmable logic, there are two on-chip buffers for storingfeature map values They are Feature Map (FM) buffer P and Q Initially, theinputs from external memory are transferred to the FM buffer P and the com-putation can be started from this point The computing engine module is thecomputational core that can process one layer at a time Once the computingengine completes the computation of the first layer, the OFMs of the first layer

accel-RR-MobileNet Acceleration on FPGA 23

will be stored in FM buffer Q Noticeably, FM buffer P and Q are used for age of IFMs and OFMs in an alternating manner for consecutive layers due tothe fact that the OFMs of a layer are the IFMs of its following layer

stor-DW and PW RAMs are for parameter storage As the module names gested, DW RAM is for DW Conv layer parameters while PW RAM is forones in PW Conv layers There are also non-DSC layers in MobileNet struc-ture, whose parameters are also stored in these two memory blocks Due to thefact that DW Conv layers have much smaller amount of parameters compared to

sug-PW Conv layers, the DW RAM is hence used for Conv layer parameters as well

as batch normalization parameters More details about OCM utilization will beintruduced in Sect.4

The computing engine consists of DW Conv, Conv, BN and ReLU modules,which conduct the computation of either a Conv or a DSC layer For DSC layers,its DW Conv layer is computed by the DW Conv module followed by a BNmodule for batch normalization and ReLU for activation function computations.Meanwhile, its PW Conv layer is computed in the Conv module and its following

BN and ReLU modules Due to the fact that PW Conv layer is a special case of

a Conv layer with all 1×1×M kernels, the Conv module is also used for general

Conv layer computation

The DW module and its following BN/ReLU blocks are an array of ing Elements (PE) as shown in Fig.3 Each PE has 32 parallel dataflow pathsthat are capable of processing 32 channels in parallel As we use pre-trainedbatch normalization parameters, each BN module essentially takes inputs andapply a multiplication and an addition for scaling operations defined in batchnormalization [10] ReLU simply caps negative input values with 0 The Convmodule is designed by conducting loop unrolling based on output feature chan-

Process-nels M , i.e M dataflow paths can produce outputs for the output chanProcess-nels in

parallel Similarly, Conv module is also consist of an array of PEs as shown

in Fig.4 Each PE can produce values for 32 OFM channels in parallel Thepatch buffers are used for loading the feature map numbers involved in eachkernel window step and broadcasting these numbers to all computational unitswithin the PE for OFM computations Finally, FC modules are designed for the

FM_P_2 PW_M

FM_P_N

FM_Q_1

FM_Q_2

FM_Q_M Patch

and7, the overall memory requirement for our Redundancy-reduced MobileNet

(RR-Mobi), which contains I Conv layers and J DSC layers, is shown below:

be reused among layers because of the fact that the OFMs of layer i are only used to compute IFMs of layer i + 1 Therefore, the memory accolated for OF M i

can be reused for storing the feature maps of the following layers So the ory requirement for feature map storage is capped by the layer with the largestfeature map values:

l=1 (I l2× N l × β l−1 × DW a × α a + O2l × M l × DW a × β l × α a ),

(10)where l=I+J

l=1 returns the maximum memory requirement for feature maps of

any single layer among all I +J layers If M em OCMrepresent the OCM resourcesavailable on a particular FPGA device, below condition should be valid in amemory system design:

So our redundancy removal strategy should ideally provide values of α and

our resulting strategy of redundancy removal for above-mentioned purposes

3.3 Layer Tilling

As introduced in Sect.3.1, feature maps are organized based on channels forparallel access However, some layers have just a few channels but with largeamount of numbers in each channel or the other way around, which lead to an