VLSI Physical Design Automation

Other Design Styles: FPGA• Field Programmable Gate Array • First introduced by Xilinx in 1984.. Comparison of Design StylesFull-Custom Standard Cell Gate Array FPGA Cell size variable fi

VLSI Physical Design Automation

Prof David Pandpan@ece.utexas.eduOffice: ACES 5.434

Misc Topics and Conclusion

Other Design Styles: FPGA

• Field Programmable Gate Array

• First introduced by Xilinx in 1984

• Pre-fabricated devices and interconnect, which are

programmable by user

• Advantages:

– short turnaround time.

– low manufacturing cost.

– fully testable.

– re-programmable.

• Particularly suitable for prototyping, low or

medium-volume production, device controllers, etc

Comparison of Design Styles

Full-Custom Standard Cell Gate Array FPGA Cell size variable fixed height fixed fixed Cell type variable variable fixed programmableCell placement variable in row fixed fixed

Interconnections variable variable variable programmable

Fabrication

layers all layers

all layers layers onlyrouting no layers

Comparison of Design Styles

Full-Custom Standard Cell Gate Array FPGA Area compact compact to moderate moderate large

Performance high high

to moderate moderate low

Time-to-market long medium medium short

Programming Technologies

• SRAM to control pass transistor / multiplexer

• EPROM – UV light Erasable PROM

• EEPROM – Electrically Erasable PROM

• Antifuses – One time programmable

• They are different in ease of manufacturing,

manufacturing reliability, area, ON and OFF

resistance, parasitic capacitance, power consumption, re-programmability

Typical FPGA Architecture

• Consists of: Logic modules, Routing resources, and

FPGA Architecture Examples

Logic Module

Routing

resources

overlayed

on logic

Two Types of Logic Modules

Look-Up Table (LUT) based:

• A block of RAM to store the truth table

• A k-input 1-output functions needs 2k bits

• k is usually 5 or 6

Multiplexer based: e.g., f=ABC+ABC

CBAAB

f

Two Types of Switchboxes

• First Type:

Several Segmentation Models

Fuse or Programmable

switch

Several Segmentation Models

• Uniform Staggered Segmentation Model:

• Non-uniform Staggered Segmentation Model:

Comparison of Segmentation Models

• The segmented model provides better utilization of

routing resources

• However, segmented model uses more fuses or

programmable switches

• The delay of a net is directly proportional to the # of

fuses or programmable switches in the route

– Manhattan-distance based delay model does NOT work

anymore

– The segmented model is slower in general

Physical Design of FPGAs

• Very different from other design styles

• Architecture dependent:

– LUT or Multiplexer in logic modules

– Type of switchboxes used

– Type of segmentation model used

• Want to partition the circuit such that each partition

(cluster) can be implemented by a logic module

• Also called Clustering

• # of I/O pins, not cluster sizes, is important

(For multiplexer based logic modules, functionality of

clusters is also important.)

Example:

Using 4-LUTs

• Global routing:

– Similar to global routing in other design styles.

– Minimize wire length and balance densities.

• Detailed routing:

– Very different from other design styles.

– Different algorithms for different segmentation models.

– Channels and switchboxes have fixed capacities.

Structured ASIC

• New buzz word, but essentially gate array

– Mask reconfigurable

– Not field reconfigurable

• Between FPGA and standard cells

– Balance delay/performance and mask cost

• Only programmable once

– by vias (e.g., Via-Programmable Gate Array – VPGA)

Physcial Design Automation

of MCMs and SiPs

Physcial Design Automation

of MCMs and SiPs

MCM and SiP

• Multi-Chip Module

• System in package (SiP)

– Different package styles

– Thermal consideration for 3D

• Alternative packaging approach for high performance systems

• Similar to PCB and IC layout problems, but

– PCB layout tools cannot handle the dense and complex

wiring structure of MCM.

– IC layout tools cannot handle the complex electrical, thermal and geometrical constraints.

Example: Pentium

Substrate size: 32mmx32mm

Package size: 43mmx43mm (4 times smaller)

• Partitioning a circuit so that each sub-circuit can be

implemented into a chip

• MCM may contain as many as 100 chips

• Need to consider timing constraints and thermal

constraints

• In addition, also need to consider traditional I/O

constraints and area constraints

• # of components is much less as compared to IC

placement

• However, need to consider timing constraints and

thermal constraints (as bare chips are placed close to each other)

• Routing is done in routing layers, not between chips

• So no routing region needs to be allocated

• Main objective is to satisfy timing constraints

• Another objective is to minimize # of routing layers, not to minimize routing area

– Cost is directly proportional to # of layers

• Crosstalk, skin effect and parasitic effect are important

considerations

• Wires are of smaller pitch and more dense than PCB layout

EE382 V Conclusions

What Have Been Taught?

• Introduced different problems in Physical Design

• Numerous algorithms which are different in terms of

What Is Important?

• Understand the problems

– How to formulate the problems, represent the constraints, solutions, etc.

– Reasonable assumptions/abstractions

• Know fundamental algorithms to solve the problems

• However, the world keeps on changing:

• It is more important to learn how to think

– formulate the problem

– solve it smartly

Problem Solving Techniques

• Reduction to graph problems

– min-cut, max-cut, shortest path, longest path, bipartite

matching, minimum spanning tree, etc.

• Divide-and-Conquer

• Many different heuristics

•

System Specification

Micro-Architectural Specification

Timing & Relationship Between Units

Conventional Physical Design Cycle

Partitioning

Floorplanning & Placement

Routing

Technology Trend and Challenges

Source:

ITRS’03

 Interconnect determines the overall performance

 In addition: noise, power => Design closure In addition: noise, power => Design closure

 Furthermore: manufacturability => Manufacturing closure Furthermore: manufacturability => Manufacturing closure

New Trends in Physical Design

• For nanometer IC designs, interconnect dominates

• New physical effects

– Noise: coupling, P/G noise

– Power: leakage, power/voltage islands

– Manufacturability: yield, printability

– Reliability, …

• More and more vertical integration

– Logic synthesis coupled with physical design

– Interconnect optimizations & design planning

– Physical design as a bridge between lower level modeling

and higher level optimization/planning

• Existing CAD algorithms are far away from optimal

Check points

design algorithms

 Know the trend and critique ability if given a new

research paper

 Project study of a topic of your choice and

implementation (through class project)

 Presentation skill