DSpace at VNU: Dual Three-Phase Indirect Matrix Converter With Carrier-Based PWM Method

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Dual Three-Phase Indirect Matrix Converter With

Carrier-Based PWM Method

Tuyen D Nguyen, Member, IEEE, and Hong-Hee Lee, Senior Member, IEEE

Abstract—This paper proposes an indirect matrix converter

(IMC) topology with dual three-phase outputs and its effective

carrier-based pulse width modulation (PWM) method The

pro-posed IMC topology can independently supply ac power for two

three-phase loads from a single three-phase ac power source This

converter consists of a rectifier stage used in traditional three-phase

IMC and a five-leg inverter Besides a proposed IMC topology, the

carrier-based PWM method suitable for this converter is also

in-troduced The proposed PWM method is easily implemented by

using only one symmetrical triangular carrier signal to generate

the PWM signals for a rectifier and five-leg inverter Proposed

IMC topology features the advantages of conventional three-phase

IMC, such as sinusoidal input/output current waveforms,

control-lable input power factor, and simple commutation at the rectifier

stage Analysis, simulation, and experimental results are provided

to demonstrate the advantages of the proposed IMC topology with

dual three-phase outputs and to validate the effectiveness of the

applied modulation strategy.

Index Terms—Carrier-based pulse width modulation (PWM),

direct matrix converter (DMC), dual inverters, five-leg inverter,

indirect matrix converter (IMC), space vector PWM (SVPWM).

I INTRODUCTION

THE three-phase to three-phase ac/ac matrix converters

(MCs) are originally presented in [1] MCs allow direct

ac/ac power conversion without the dc energy storage

compo-nent They have recently received considerable attention as an

al-ternative to the conventional ac/ac converter, which is composed

of rectifier/dc-link capacitor/inverter structures MCs have many

advantages such as sinusoidal input and output current

wave-forms, unity power factor at the input side, increased power

density, and inherent four-quadrant operation In addition, MCs

are highly reliable and durable due to the lack of a dc-link

electrolytic capacitor for energy storage [2]

MCs are classified into two types: direct matrix

convert-ers (DMC) and indirect matrix convertconvert-ers (IMC) The DMC

is a one stage ac/ac direct converter, where three-phase input

Manuscript received September 6, 2012; revised November 26, 2012, January

15, 2013, and February 7, 2013; accepted March 12, 2013 Date of current

version August 20, 2013 This work was supported by the National Research

Foundation of Korea (NRF) grant funded by the Korea government (MEST)

under Grant 2010-0025483 Recommended for publication by Associate Editor

J R Rodriguez.

T D Nguyen is with the Faculty of Electrical and Electronics Engineering,

Ho Chi Minh City University of Technology, Ho Chi Minh City, Vietnam

(e-mail: ndtuyen@hcmut.edu.vn).

H.-H Lee is with the School of Electrical Engineering, University of Ulsan,

Ulsan 680-749, Korea (e-mail: hhlee@mail.ulsan.ac.kr).

Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2013.2255067

Fig 1 DMC topology.

Fig 2 IMC topology.

voltages are directly connected to three-phase output loads through nine bidirectional switches as shown in Fig 1 [3], [4]

On the other hand, the IMC topology is based on the ac/dc/ac power conversion with no intermediate capacitor The IMC com-prises two stages such as rectifier stage and inverter stage, which are illustrated in Fig 2 [5]–[13] DMC and IMC provide the same input/output performance, maximum voltage transfer ra-tio, and number of power switches However, the IMC topology provides a soft switching commutation that is not applicable in DMC Furthermore, the IMC needs the simpler clamp circuit for overvoltage protection as compared to the DMC

IMC topology has recently been widely discussed and many researchers have developed the various IMC topologies suitable

for specific applications Kolar et al [14]–[16] concentrated

to modify the rectifier stage structure with the reduced power devices by utilizing the zero current commutation In part of the inverter stage, some novel IMC topologies have recently

been proposed such as the hybrid IMC [17], [18] and Z-source

IMC [19], [20] to increase the output voltage transfer ratio, the four-leg IMC for unbalanced loads [21], and the multilevel IMC

to improve the output voltage quality [22], [23]

0885-8993 © 2013 IEEE

Fig 3 Dual three-phase output IMC topology based on the parallel connection

of two three-leg inverters.

Fig 4 Dual three-phase output IMC topology based on the nine-switch

inverter.

On the other hand, the IMC with dual three-phase outputs

is also introduced in order to reduce the total cost and

sys-tem volume [24], [25] Dual ac-drive syssys-tems from

conven-tional voltage source inverter (VSI) have been studied for

spe-cial industrial applications such as electric vehicles, railway

traction system, steel processing, textile manufacturing, and

winders [26]–[33] However, they have the same drawbacks

as-sociated with the rectifier/dc-link capacitor/inverter conversion

system Dual three-phase outputs IMC topology consists of an

input stage and two output stages with a pair of conventional

three-leg inverters, as shown in Fig 3 The drawback of this

topology is the large number of power switches in the inverter

stage, 12 power switches are used in the inverter stage Another

approach to the IMC topology is proposed in [34] for

indepen-dent control of two three-phase loads with fewer reduced power

switches This topology is based on the traditional IMC, but the

inverter stage is replaced by a nine-switch inverter as shown in

Fig 4 Even if this topology works with reduced numbers of

power switches, the switch capacity in the nine-switch inverter

stage is doubled

Fig 5 Proposed dual three-phase output IMC topology.

In order to overcome the disadvantages in the previous IMC topologies as shown in Figs 3 and 4, this paper proposes the IMC topology composed from a five-leg inverter connected to

a rectifier stage to generate dual three-phase outputs effectively

by using a common leg supplying both of two loads, which

is shown in Fig 5 As shown in Fig 5, two phases of each load are supplied independently from four legs of the inverter stage while each remaining phase for the two loads is connected

to the same leg The proposed IMC topology can reduce two power switches, in comparison to the conventional IMC topol-ogy shown in Fig 3, and can halve the switch capacity compared

to the IMC topology with nine-switch inverter stage shown in Fig 4 except the switches in leg C due to the common current path for both the currents of load 1 and load 2 Moreover, the number of power switch in the proposed topology can be re-duced by three in the case of unidirectional power flow from the power supply to the loads

Besides interest in the IMC topology for particular applica-tions, modulation methods to effectively drive IMC have also been investigated in recent technical publications The space vector PWM (SVPWM) method has been generally used to control IMC because it has a good performance such as a lower current harmonic and higher modulation index [5]–[10] How-ever, this method needs many calculations and lookup tables

to generate the switching pattern On one hand, the carrier-based PWM method has been presented for three to three phase IMC [35], [36] However, the carrier signal used for the rectifier stage is different from that of the inverter stage The carrier sig-nal used for the rectifier stage is a symmetrical triangular sigsig-nal with constant frequency, while the carrier signal with different slope in the rising and falling edge is used for the inverter stage Furthermore, these slopes of the carrier signal are changed in every sampling period due to the variation of the dc-link voltage

In this paper, in order to overcome the limitation of the SVPWM and the conventional carrier-based PWM method, we introduce the carrier-based PWM method for the proposed IMC topology, which uses only one symmetrical triangular carrier signal with constant frequency and magnitude to generate PWM signals for all switches of both the rectifier and five-leg inverter stage The proposed carrier-based PWM method can be implemented easily by using only one up/down counter, which is available

in most of digital signal processors The proposed modulation

method is established based on space vector analysis

This paper is organized as follows: the operational principles

and the SVPWM for the proposed IMC topology are introduced

in Section II Section III describes the proposed carrier-based

PWM method, which is based on the space vector analysis in

Section II Simulations studies and experiments on two

three-phase inductive loads are implemented and provided in Sections

IV and V, respectively, to demonstrate that two three-phase loads

are fed independently from single three-phase power supply

Finally, Section VI offers some conclusions

II OPERATIONALPRINCIPLES OF THEPROPOSEDIMC

TOPOLOGYWITHDUALTHREE-PHASEOUTPUTS

In order to explain the operational principles of the proposed

IMC topology, we use the space vector theory, which is a

well-known technique commonly adopted in the previous technical

literatures As shown in Fig 5, the proposed topology comprises

a rectifier stage connected to a five-leg inverter stage The

tar-get of the rectifier stages is to generate the maximum dc output

voltage at the dc-link bus as well as to produce the sinusoidal

input current waveforms The desired output voltages with

vari-able frequency for two loads can be obtained by controlling the

five-leg inverter stage The rectifier stage is controlled based on

the reference input current vector, and the five-leg inverter stage

is controlled based on two reference output voltage vectors of

two loads The two stages are controlled separately and both

switching patterns of the two stages are synthesized together

A Rectifier Stage Control

The rectifier stage is connected to a three-phase power supply

with constant amplitude and frequency It is assumed that

three-phase input voltages are balanced as follows:

v a = V i cos (ω i t)

v b = V i cos (ω i t − 2π/3)

v c = V i cos (ω i t+2π/3) (1)

where V i and ω iare the amplitude and angular frequency of the

input phase voltage, respectively

We can describe the input current vector and input voltage

vector as follows:

i i= 2

3



i a + i b e j 2π /3 + i c e j 4π /3



= I i e j α i (2)

 i= 2

3



v a + v b e j 2π /3 + v c e j 4π /3



= V i e j β i (3)

where α i and β i are current and voltage phase angles,

respectively

Fig 6 shows the space vector diagram of the rectifier stage

Each active current vector represents the switching condition

between the input phase voltage and the dc-link bus For

exam-ple, the current vector I ab represents the input phase “a” and

“b” are connected to the positive pole and the negative pole of

dc-link bus, respectively The zero vector means that the input

voltage is not applied to dc-link bus Assume that the reference

Fig 6 Space vector diagram and the generation of reference input current vector in the rectifier stage.

input current vector is located in sector 1(−π/6 ≤ α i ≤ π/6)

and lags behind the input voltage vector with the angle δ The duty cycle of the active vectors for the rectifier stage I ab and I ac

are determined as follows:

d γ = m i sin (π/6 − (β i − δ)) (4)

d δ = m i sin (β i − δ + π/6) (5)

where m iis the rectifier stage modulation index

Because the zero vectors are not used to synthesis the

refer-ence input current vector, the duty ratio d γ and d δfor two active

vectors I ab and I acare recalculated as follows:

d x= d γ

d δ + d γ

= cos (β i − 2π/3 − δ)

d y = d δ

d δ + d γ

= cos (β i − 4π/3 − δ)

The dc-link voltage has two values, vba with the duty cycle

d x , and vca with the duty cycle d y Thus, the average value of the dc-link voltage in one sampling period is

Vdc = d x (v a − v b ) + d y (v a − v c) =3

2

V i cos (β i − δ) cos δ.

(8)

From (8), the minimum value of the Vdcis

Vdc(m in) = 3

Depending on the position of the reference input current vec-tor, suitable active vectors are chosen to generate the dc-link voltage By similar analysis, Table I summarizes the switching state of all power switches, the corresponding dc-link voltage and its average value according to the input current sector In the odd sector, the upper switch of the positive input phase voltage

is in the ON state at any time, and two lower switches of two negative input phase voltages are modulated In the other case (i.e., in the even sector), the lower switch of the negative input

TABLE I

M ODULATED S WITCHES AND DC-L INK V OLTAGE A CCORDING TO THE I NPUT C URRENT S ECTOR

Fig 7 Generation of reference output voltage for (a) Load 1 (b) Load 2.

phase voltage is in the ON state, and two upper switches of two

positive input phase voltages are modulated

B Five-Leg Inverter Stage Control

The SVPWM techniques have been widely used in inverter

control due to the lower current harmonic and higher modulation

index The purpose of the SVPWM technique is to generate the

reference output voltage vector by conjoining the switching

states corresponding to the active and zero vectors Fig 7(a)

and (b) illustrates the active vectors, the zero vectors, and the

position of the reference output voltage vector in the case of

load 1 and load 2, respectively The eight space vectors are used

in the SVPWM technique, where V1∼V6are active vectors, and

V0 and V7 are zero vectors Each vector is denoted by the set

of switching functions: [SA SB SC] in the case of load 1, and

[SE SD SC] in the case of load 2 The switching function of the

upper switch in each leg is defined as

S X =



1 if S X is ON state

0 if S X is OFF state X = A∼ E. (10)

It is assumed that the reference output phase voltages of the

load 1 are

v A 1 = Vo1cos (ωo1t + ϕo1)

v B 1 = Vo1cos (ω o1 t + ϕo1− 2π/3)

v C 1 = Vo1cos (ω o1 t + ϕ o1 + 2π/3) (11)

and the reference output phase voltages of the load 2 are

vA 2 = Vo2cos (ω o2 t + ϕ o2)

v B 2 = V o2 cos (ω o2 t + ϕ o2 − 2π/3)

v C 2 = V o2 cos (ω o2 t + ϕ o2 + 2π/3) (12)

where V o1 , ω o 1 , and ϕ o 1 are the amplitude, angular fre-quency, and initial phase of the output phase voltage of load 1, respectively

V o2 , ω o2 , and ϕ o2 are the amplitude, angular frequency, and initial phase of the output phase voltage of load 2, respectively

We can describe the reference output voltage vectors of two loads as follows:

 o1 = 2 3



vA 1+ vB1e j 2π /3 + vC 1e j 4π /3



= V o1 e j α o 1(13)

 o2 = 2 3



vA 2+ vB2e j 2π /3 + vC 2e j 4π /3



= V o2 e j α o 2(14)

where α o 1 and α o 2are the angles between each reference output voltage vector and the basic active vector V1 as shown in Fig 7 Without loss of generality, the reference output voltage vec-tors of load 1 and load 2 are assumed to be located in sector

1 (0≤α o1 ≤π/3) and sector 2 (π/3≤α o2 ≤2π/3), respectively.

From Fig 7(a) and (b), the reference output voltage vector of the two loads can be synthesized as follows:

 o1 = T1(1)V 1+ T2(1)V 2 (15)

 o2 = T2(2)V 2+ T3(2)V 3. (16) Therefore, the application time of active vectors and zero vectors of load 1 are written as

T1(1)=√

3V o1

VdcT s sin (π/3 − αo1) (17)

T2(1)=√

3V o1

T7(1)= T0(1)= 1

2



T s − T1(1)− T2(1)



(19)

Fig 8 Switching pattern of load 1 when the reference output voltage vector

is in sector 1.

Fig 9 Switching pattern of load 2 when the reference output voltage vector

is in sector 2.

and those of load 2 are written as

T2(2)=√

3Vo2

VdcT s sin (2π/3 − αo2) (20)

T3(2)=√

3Vo2

VD C

T s sin (αo2− π/3) (21)

T7(2)= T0(2) =1

2



T s − T2(2)− T3(2)



The symmetric arrangement of two active vectors and two

zero vectors of load 1 and load 2 are shown in Figs 8 and 9,

respectively Also, the sequence and the application time of all

upper switches are shown individually for each output load

Two loads share the common leg C Therefore, the two upper

switches of phases C1 and C2 have the same application time

Hence, the application time for zero vectors V0 and V7 of two

loads should be changed, while the application time for active

vectors is unchanged to ensure that the magnitude of two

ref-erence output voltages are kept constant The application time

of all upper switches of the five-leg inverter in one sampling

period is determined as follows:

T A = T7(1)+ T2(1)+ T1(1)+ T7(2)− T s

T B = T7(1)+ T2(1)+ T7(2)− T s

T C = T7(1)+ T7(2)− T s

T D = T7(2)+ T2(2)+ T7(1)+ T3(2)− T s

T E = T7(2)+ T2(2)+ T7(1)− T s

Fig 10 Switching pattern for the five-leg inverter stage.

Fig 10 shows the symmetric switching scheme of the five-leg inverter stage when two phases of two loads are connected to the same point at leg C It can be seen that the distribution of application time for active vectors of each load is unchanged

The distribution of application time for zero vectors V0 and V7

of each load is changed; however, the amount of application time of zero vectors is kept constant

C Maximum Voltage Transfer Ratio

The application time of all switches in the five-leg inverter stage has to be positive Therefore, we can obtain (28) from (17)–(27)

V o1 + V o2 ≤ V √dc

If we define q1 and q2 as the voltage transfer ratio of load 1 and load 2, respectively, then the voltage transfer ratios become

q1 = Vo1

q2 = Vo2

From (9) and (28), there is the constraint of output voltages for two loads such as

q1+ q2 ≤

√

3

From (31), we can see the maximum voltage transfer ratio,

0.866, is obtained under the unity power factor constraint (δ

= 0) However, the maximum voltage transfer ratio becomes

smaller by the factor cosδ for nonunity input power factor.

D Switching Patterns and the Safe Commutation

In one sampling period the dc-link voltage has two values, which depend on the switching state of the rectifier stage There-fore, the five-leg inverter is fed by two positive line-to-line input voltages In order to obtain the balanced output voltages within

a sampling period, the switching pattern of the converter has to mix the switching states of the rectifier stage and the five-leg inverter stage

Considering one half of sampling period T s/2, the values of

the dc-link voltage are two line-to-line input voltages v ab and v ac with the duration Tbn = d x T s /2 and Tcn= d y T s /2, respectively.

Fig 11 Switching states of the rectifier and inverter stages.

Consequently, the application time of all upper switches in the

five-leg inverter stage is separated into two parts These values

are obtained by the cross product of the duty ratio of the rectifier

stage and the application time of the switches in the inverter

stage as follows:

T A (ab) = T A d x /2; T A (ac) = T A d y /2 (32)

T B (ab) = T B d x /2; T B (ac) = T B d y /2 (33)

T C (ab) = T C d x /2; T C (ac) = T C d y /2 (34)

T D (ab) = T D d x /2; T D (ac) = T D d y /2 (35)

T E (ab) = T E d x /2; T E (ac) = T E d y /2. (36)

The switching states of the rectifier stage and the five-leg

inverter stage are arranged as shown in Fig 11 in order to

maintain the zero dc-link current commutation at the rectifier

stage The commutation of the rectifier stage always happens

during the time when the zero vectors in the five-leg inverter

stage are applied to synthesize two reference output voltage

vectors Therefore, the complex multistep commutation can be

avoided Furthermore, the switching losses in the rectifier stage

are reduced by applying the zero dc-link current commutation

In the inverter stage, a complementary signal controls the upper

and lower switch in the same leg Therefore, safe operation of

the inverter stage is implemented by the conventional dead-time

commutation

III CARRIER-BASEDPWM METHOD FORDUAL

THREE-PHASEOUTPUTS

Two independent SVPWMs are used to analyze the rectifier

and five-leg inverter stages As aforementioned, there are six

switching patterns in the rectifier stage and 32 switching

pat-terns in the inverter stage The switching patpat-terns of the whole

Fig 12 Closed-loop control block diagram based on the proposed carrier-based PWM method.

system are obtained by coordinating the switching states of the rectifier and five-leg inverter stages Therefore, the space vector modulation approach for the proposed converter needs many cal-culations and tables to obtain the switching patterns according

to the positions of input current vector and two output reference voltage vectors In order to simplify the control technique, the carrier-based PWM method is developed instead of SVPWM Fig 12 shows the closed-loop control block diagram of the proposed IMC based on the carrier-based PWM method After detecting the three-phase output voltages for each load, they

are transformed to dc values in the dq rotating reference frame.

The desired output voltages are compared with the measured voltages, and the reference output voltages, which are used to calculate the modulation signals, are generated through the PI voltage controller

In the carrier-based PWM method, the PWM signals are gen-erated by comparing the modulation signals with a triangular carrier signal The modulation signals are calculated based on the duty cycles in the rectifier stage, the average value of dc-link voltage and the reference output voltages To correlate the SVPWM with the carrier-based PWM, the set of modulation signals have to be obtained to generate the same PWM sig-nals as the SVPWM method The proposed carrier-based PWM method is discussed in detail in the following sections

A Carrier-Based PWM for the Rectifier Stage

In the carrier-based PWM method, the PWM signals are gen-erated by comparing the modulation signals with a triangular carrier signal To correlate the SVPWM with the carrier-based PWM, the set of modulation signals (which are compared with the carrier signal) have to be obtained to generate the same PWM signals as the SVPWM method

Fig 13(a) illustrates the sequence and timing of modulated switches in the rectifier stage when the reference input current vector is in sector 1 In half of a sampling period, the duration

T , T , and T of the gating pulses for switches S , S ,

Fig 13 (a) Sequence and timing of effective switches in the rectifier stage.

(b) Modulation signals and symmetrical carrier signals to generate PWMs for

the rectifier stage.

and Scn are

Tap= T s

2 ; Tbn = d x

T s

2 ; Tcn= d y

T s

Fig 13(b) shows two modulation signals vap and vbn, and

the triangular carrier signal v t The gating pulses for the switch

Sap and Sbn are obtained from the intersection between the

modulation signals vapand vbnand the carrier signal The gate

pulse for switch Scn is complementary to that of switch Sbn.

As shown in Fig 13(b), the symmetrical triangular carrier

signal can be described by

v t =

 4

T s

t − 1



V i , 0≤ t ≤ T s

2 (38)

where v t and V i are the instantaneous and peak value of the

carrier signal, respectively

Therefore, the modulation signals for the rectifier stage are

easily obtained from (37) and (38)

vap= V i ; vbn = (2d x − 1) V i (39)

All remaining switches (San, Sbp, Scp) are OFF state

There-fore, the modulation signals, which are used to generate gating

pulses for these switches, are determined as follows:

v an =−V i ; v bp=−V i ; v cp =−V i (40)

B Carrier-Based PWM for Five-Leg Inverter

Fig 14(a) shows the sequence and the application time of all

upper switches in the five-leg inverter stage In one half

sam-pling period, the switching period of each switch is divided into

two parts with unequal values For example, the application time

of the upper switch of leg A (T A/2) is separated into two values

T A (ab) and T A (ac) , which are determined in (32) .The duration

time T A (ab) has to be applied to the switch S Awhen the dc-link

voltage is v ab ; otherwise, the duration time T A (ac) has to be

applied when the dc-link voltage is v ac Unlike in the case of

the rectifier stage (where the switching frequency is equal to the

carrier signal frequency), the switching frequency in the

five-leg inverter stage is twice that of the carrier signal Therefore,

Fig 14 (a) Switching pattern of the five-leg inverter stage (b) Waveforms of

two modulation signals and carrier signal (c) PWM waveforms for switch S A.

we cannot use one modulation signal that is compared with the carrier signal to generate a gate signal in the inverter stage In or-der to elucidate the proposed carrier-based PWM in the inverter stage, we consider how to generate the gate signal for the switch

S A To create the gate signal for switch S A, two modulation signals are needed Fig 14(b) shows two modulations signals

v A (upp er) and v A (lower), and the carrier signal The PWM0 and PWM1 are the results of comparing two modulation signals with the carrier signal As shown in Fig 14(c), the switching pattern

of switch S A is obtained by

S A = PWM0• PWM1 + PWM0 • PWM1. (41)

We then have to determine the instantaneous value of two

modulation signals The time intervals T A (upp er) and T A (lower)

in Fig 14(b) are calculated as follows:

T A (upp er)= T s

2 − T A (ac)=T s

2 −1

2

×



T7(1)+T1(1)+T2(1)+T7(2)− T s

2



d y (42)

T A (lower) = T A (ab) =1

2

×



T7(1)+T1(1)+T2(1)+T7(2)− T s

2



d x (43)

By substituting T A (upp er) and T A (lower) from (42) and (43)

into (38) for variable t, two modulation signals v A (upp er) and

v A (lower)are obtained as follows:

v A (upp er) = V i



−2d y

v A 1 + v C 2 + voff set1+ voff set2

¯

Vdc

+ d x



(44)

v A (lower) = V i



2d x

v A 1 + v C 2 + voff set1+ voff set2

¯



(45)

where voff set1 and voff set2 are two offset voltages, which are

written as

voff set1 =−0.5v A 1 − 0.5v C 1 (46)

voff set1 =−0.5v B 2 − 0.5v C 2 (47)

Likewise, the couple of modulation signals, which are used

to generate PWM signals for the remaining upper switches S X

(X = B ∼ E), are obtained as follows:

v B (upp er) = V i



−2d y

v B 1 + v C 2 + voff set1+ voff set2

¯

Vdc

+ d x



(48)

v B (lower) = V i



2d x

v B 1 + v C 2 + voff set1+ voff set2

¯

Vdc

− d y



(49)

v C (upp er) = V i



−2d y

v C 1 + v C 2 + voff set1+ voff set2

¯



(50)

v C (lower) = V i



2d x v C 1 + v C 2 + v¯off set1+ voff set2



(51)

v D (upp er) = V i



−2d y

v B 2 + v C 1 + voff set1+ voff set2

¯

Vdc

+ d x



(52)

v D (lower) = V i



2d x v B 2 + v C 1 + v¯off set1+ voff set2



(53)

v E (upp er) = V i



−2d y

v A 2 + v C 1 + voff set1+ voff set2

¯

Vdc

+ d x



(54)

v E (lower) = V i



2d x

v A 2 + v C 1 + voff set1+ voff set2

¯

Vdc

− d y



.

(55) Equations (44)–(55) are established under the assumption

that the reference output voltages of loads 1 and 2 are located

in sectors 1 and 2, respectively However, these results are valid

for all the other sectors when two offset voltages are chosen as

voff set1 =−0.5 (vm ax 1+ vm in 1) (56)

voff set2 =−0.5 (vm ax 2+ vm in 2) (57)

where

vm ax 1 = max (v A 1 , v B 1 , v C 1 ) ; vm in 1

= min (v A 1 , v B 1 , v C 1) (58)

vm ax 2 = max (v A 2 , v B 2 , v C 2 ) ; vm in 2

Fig 15. Couple modulation signals v A ( u p p e r) and v A ( low e r)to generate the

gate signal for switch S A (a) f1 = f2= 50 Hz (b) f1= 50 Hz, f2 = 100 Hz.

Fig 16 Block diagram of the proposed carrier-based PWM method.

Fig 15 shows the waveforms of the normalized modulation

signals v A (upp er) and v A (lower) at the output frequencies: f1 =

f2 = 50 Hz and f1 = 50 Hz, f2 = 100 Hz, where f1 and

f2 are output frequencies of load 1 and load 2, respectively

In case of the conventional VSI, the modulation signals have sinusoidal waveforms because they have the only information about the reference output voltage However, the modulation signals in the inverter stage contain the information about both input voltage and reference output voltage in (44) and (45), so that they cannot be sinusoidal as shown in Fig 15

The principle of the proposed carrier-based PWM method explained up to now is shown in Fig 16, which shows how to generate gating signals for six bidirectional switches in the rec-tifier stage and ten unidirectional switches in the inverter stage All required functions are easily implemented without a lookup table or complex calculations, and there is no need to coordinate the switching state of the rectifier and five-leg inverter stages The performance of the proposed modulation is the same as that

of the SVPWM including the zero current commutation of the rectifier stage because the proposed carrier-based PWM method

is derived based on the mathematical analysis with SVPWM

Fig 17 Simulation waveforms of input voltage/current and output currents

under in-phase CF mode.

Fig 18 Simulation waveforms of input voltage/current and currents under

CF mode with the phase shift 45◦.

IV SIMULATIONRESULTS

The proposed IMC topology with dual three-phase outputs

shown in Fig 5 has been simulated using Psim 9.0 software In

this simulation, the proposed IMC is evaluated using two

three-phase RL loads The simulation parameters are as follows:

1) three-phase power supply: the input line-to-line voltage is

200 V and the input frequency is 60 Hz;

2) LC input filter: L = 1.4 mH, C = 27 μF;

3) the carrier signal frequency is 10 kHz (T s = 100 μs);

4) three—phase RL load 1: R = 10 Ω, L = 5 mH;

5) three—phase RL load 2: R = 12 Ω, L = 5 mH.

The performance of the proposed dual three-phase output

IMC with the carrier based-PWM modulation method is

eval-uated for two cases to determine whether it has similar

perfor-mance as two independent three-phase IMCs: common output

terminal frequency (CF mode) and different output terminal

frequency (DF mode) For each case, the desired output

fre-quencies (f1, f2) and the voltage transfer ratios (q1, q2) are set

as follows: in CF mode, f1 = 50 Hz, q1 = 0.3 for load 1, and

the f2 = 50 Hz, q2= 0.5 for load 2; in DF mode, f1 = 50 Hz,

q1= 0.3 for load 1, and the f2 = 100 Hz, q2 = 0.5 for load 2,

and open-loop control is applied

Figs 17 and 18 show the simulation results in CF mode

obtained by adjusting the current phase between two output

loads Fig 17 shows input voltage (v a )/current (i a) and output

currents of two loads in CF mode, when the output currents

of two loads, i A 1 and i A 2 are set in-phase Both the input and

output current are sinusoidal waveforms Due to the LC filter,

Fig 19 Simulation waveforms of input voltage/current and output currents under DF mode.

Fig 20 Simulated waveforms of input voltage/current and output currents at

different load step: The load condition 1 changes from q1= 0.25, f1 = 50 Hz

to q1 = 0.5, f1 = 100 Hz and the load condition 2 changes from q2 = 0.5, f2

= 100 Hz to q2= 0.25, f2 = 50 Hz.

there is a displacement angle between the input current and input voltage

In order to verify that the output phase can be controlled independently by using the proposed IMC, only current phase commands is changed in Fig 18 under the same conditions as shown in Fig 17; the current of load 1 lags behind that of load

2 by 45◦, while the output frequencies remain the same All waveforms are the same as those shown in Fig 17 except for the output current phase difference, and the proposed IMC is shown to control two output phases independently

Fig 19 shows the simulated waveforms of the input volt-age/current and two output currents of two loads in DF mode Similar to the CF mode, the input/output currents have good sinusoidal waveforms with the desired frequencies

Fig 20 shows the input voltage/current and two output cur-rents of two loads in DF mode when the load condition 1 changes

from q1= 0.25, f1= 50 Hz to q1= 0.5, f1= 100 Hz and the load

condition 2 changes from q2 = 0.5, f2 = 100 Hz to q2= 0.25,

f2 = 50 Hz We can see the proposed converter maintains the

sinusoidal input/output currents and good dynamic performance even though the load condition changes suddenly

Fig 21 shows the transient responses of the input current and

output voltages with the closed-loop V /f control The output

voltage reference of load 1 steps up from 20 to 30 V and the frequency also steps up from 20 to 30 Hz In case of the load

Fig 21 Simulated waveforms of input currents, output voltages of load 1 and

load 2 with closed-loop V/f control.

Fig 22 THD of the input current and output voltages.

Fig 23. Input power factor according to the voltage transfer ratio q1and q2

2, the output voltage reference steps up from 30 to 60 V and

the frequency steps up from 30 to 60 Hz It can be found that

the balanced and sinusoidal input currents and output voltages

are obtained, and the dynamic response of the output voltages

is very good

The total harmonic distortion (THD) of the input current and

output voltages according to the output frequency variation are

shown in Fig 22, where q1 = 0.3 and q2 = 0.5; THD of input

current is lower than 1.8% and THD of output voltages are

lower than 1.4% Fig 22 shows the proposed converter has a

good power quality Fig 23 shows the input power factor of

the converter according to the voltage transfer ratios for two

Fig 24 Laboratory setup of the proposed IMC experiment: (a) Controller board (b) Power circuit board.

loads The input power factor is almost unity when the total

voltage transfer ratio (q1+ q2) is near to the maximum voltage

transfer ratio 0.866, and the power factor characteristic of the total voltage transfer ratio is almost the same as that of the conventional IMC

According to the simulated results, the proposed IMC topol-ogy provides the sinusoidal input current on both of in-put and outin-put sides Thus, the proposed carrier-based PWM method can effectively control the proposed converter with high-performance current at the power supply and loads

V EXPERIMENTALRESULTS

To validate the proposed theory and simulated results, an ex-perimental platform is setup in the laboratory Fig 24 shows the laboratory IMC with dual three-phase outputs The pro-totype consists of a controller board that executes the control program, A/D converter, the generating PWM signals, and the power board The controller board is developed with a high-performance DSP TMS320F28335 by Texas Instruments and

a complex programmable logic device EPM7128LC84-15 by Altera The power switch IGBTs – G4PF50WD – have been used to implement the power circuit in the rectifier and the