Introduction to output compare

OUTPUT COMPARE MODULE The output compare module has the task of comparing the value of the time base counter with the value of one or two compare registers depending on the Operation mod

OUTPUT COMPARE MODULE

The output compare module has the task of comparing the value of the time base counter with the value of one or two compare registers depending on the Operation mode selected

It is able to generate a single output pulse or a sequence of output pulses when the compared values match; also, it has the ability to generate interrupts on compare match events

Ex:

Ex: The dsPIC30F4013 controller has 4 output compare modules whereas controller dsPIC6014A has 8 Each output compare channel can select which of the time base counters, TMR2 or TMR3, will be compared with the compare registers The counter is selected by using control bit OCTSEL (OCxCON<3>)

The output compare module has several modes of operation selectable by using control bits OCM<2:0> (OCXCON<2:0>):

• Single compare match mode

• Dual compare match mode generating either one output pulse or a sequence of output pulses,

• Pulse Width Modulation (PWM) mode

Fig 1 Functional diagram of output compare module

1

1 SINGLE COMPARE MATCH MODE SINGLE COMPARE MATCH MODE SINGLE COMPARE MATCH MODE

When control bits OCM<2:0> are set to 001, 010, or 011, the ouput compare module is set to the Single compare match mode Now, the value loaded in the compare register OCxR is compared with time base counter TMR2 or TMR3 On a compare match event, depending on the value of OCM<2:0>,

at the OCx output pin one of the following situations is possible:

• OCx pin is high, initial state is low, and interrupt is generated,

• OCx pin is low, initial state is high, and interrupt is generated,

• State of OCx pin toggles and interrupt is generated

• SINGLE COMPARE MATCH, PIN OCX DRIVEN HIGH SINGLE COMPARE MATCH, PIN OCX DRIVEN HIGH

In order to configure the output compare module for this mode, control bits OCM<2:0> are set to 001 Also, the time base counter (TMR2 or TMR3) should be selected Initially, output pin OCx is set low and will stay low until a match event occurs between the TMRy and OCxR registers One instruction clock after the compare match event, OCx pin is driven high and will remain high until a change of the mode or the module is disabled TMRy goes on counting Twop instruction clocks after OCx pin is driven high, the interrupt, OCxIF flag, is generated Timing diagram of the single compare mode, set OCx high on compare match event is shown in Fig 2

Fig 2 Timing diagram of the single compare mode, set OCx high on compare

match event

• Single compare match, pin OCx driven low Single compare match, pin OCx driven low

In order to configure the output compare module for this mode, control bits OCM<2:0> are set to 010 Also, the time base counter (TMR2 or TMR3) should be enabled Initially, output pin OCx is set high and it stays high until a match event occurs between the TMRy and OCxR registers One instruction clock after the compare match event OCx pin is driven low and will remain low until a change of the mode or the module is disabled TMRy goes on counting Two instruction clocks after OCx pin is driven low, the interrupt flag, OCxIF, is generated Timing diagram of the single compare mode, set OCx low on compare match event is shown in Fig 3

Fig 3 Timing diagram of the single compare mode,set OCx low on compare

match event

• SINGLE COMPARE MATCH, PIN OCX TOGGLES SINGLE COMPARE MATCH, PIN OCX TOGGLES

In order to configure the output compare module for this mode, control bits OCM<2:0> areset to 011 Also, the time base counter (TMR2 or TMR3) should be enabled Initially, output pin

OCx is set low and then toggles on each subsequent match event between the TMRy and OCxR reg

event between the TMRy and OCxR registersisters OCX pin is toggled one instruction clock the compare match event TMRy goes on counting Two instruction clocksafter the OCX pin is toggled, the interrupt flag, OCxF, is generated Figs 4 and 5 show the timing diagrams of the single compare mode, toggle output on compare match event when timer register PRy (PR2

or PR3)>OCxR (Fig 4) or timer register PRy (PR2 or PR3)=OCxR (Fig 5)

Fig

Fig 4 Timing diagrams of the single compare mode, toggle output on compare 4 Timing diagrams of the single compare mode, toggle output on compare

match event when timer register PRy>OCxR match event when timer register PRy>OCxR

Fig 5 Timing diagrams of the single compare mode, toggle output on compare

match event when timer register PRy=OCxR

In the interrupt routine the request for the flag Output compare interrupt module is reset At setting time base 2, preset register PR2 is set to the maximum value in orde to enable the free-running mode over the whole range, 0-65335 The value of OC1R defines the time of the change of state of pin OC1, i.e of the duty cycle The output compare module is configured to change the state of pin OC1 on single compare match with the value of OC1R

2

2 DUAL COMPARE MATCH MODEDUAL COMPARE MATCH MODEDUAL COMPARE MATCH MODE

When control bits OCM<2:0> are set to 100 or 101, the output compare module is configured for the dual compare match mode In this mode the module uses two registers, OCxR and OCxRS, for the compare match events

The values of both registers are compared with the time base counter TMR2 or TMR3 On a compare match event of the OCxR register and register TMR2 or TMR3 (selectable by control bit

OCTSEL), the leading edge of the pulse is generated at the OCx pin; the register OCxRS is then compared with the same time base register and on a compare match event, the trailing edge

at the OCx pin is generated

Depending on the value of control bit OCM<2:0> at the output pin OCx is generated:

- Single pulse and an interrupt request,

- A sequence of pulses and an interrupt request

PIN OCX

PIN OCX

When control bits OCM<2:0> are set to 100, the output compare module is configured for the dual compare match (OCxR and OCxRS registers), single output pulse mode By setting the control bits OCTSEL the time base counter for comparison is selected v Two instruction clocks after pin OCx

is driven low, an interrupt request OCxIF for the output compare module is generated Pin OCx will remain low until a mode change has been made or the module is disabled If the contents of time base register PRy<OCxRS, no trailing edge and the interrupt request are generated and if PRy<OCxR no leading edge is generated at pin OCx Fig 6-6 shows timing diagram of the operation of the output compare module in the dual compare match mode, single pulse at the output pin OCx (OCxR < OCxRS < PRy)

Fig 6 Timing diagram of the operation of the output compare module in the dual

compare match mode, single pulse at the output pin OCx

PULSES

PULSES AT PIN OCXAT PIN OCXAT PIN OCX

When control bits OCM<2:0> are set to 101 the output compare module is configured for the dual compare match (OCxR and OCxRS registers), a sequence of output pulses is generated at the output OCx pin After a compare match occurs between the compare time base (TMR2 or TMR3) and OCxR registers, the output pin OCx is driven high, i.e the leading edge is generated at pin OCx When a compare match occurs between the time base (TMR2 or TMR3) and OCxRS registers, the trailing edge at pin OCx is generated, i.e pin OCx is driven low Two instruction clocks after, an interrupt request for the otput compare module is generated In this mode it is not it is not

necessary to reset the ouput compare module

necessary to reset the ouput compare module in order that the module could react on equalization of the TRy and OCxR or OCxRS registers Even if the interrupt of the output compare module is enabled (OCxIE is set), it is required that in the the interrupt routine the interrupt request flag of the output compare module OCxIF is reset

compare module OCxIF is reset

If the preset register PRy < OCxRS, the trailing edge at pin OCx will not be generated Fig 6-7 shows an example of operation

of the output compare module in the dual compare match mode, a sequence of output pulses at the output pin OCx (OCxR < OCxRS < PRy)

Fig 7 Timing diagram of the operation in the dual compare match mode, pulse

sequence at the output pin OCx

3

3 THE PULSE WIDTH MODULATION (PWTHE PULSE WIDTH MODULATION (PWTHE PULSE WIDTH MODULATION (PWM) MODEM) MODEM) MODE

When control bits OCM<2:0> are set to the values 110 or 111, the output compare module is configured for the pulse width modulation (PWM) mode The PWM mode is available without fault protection input or with fault protection input For the second PWM mode the OCxFA or OCxFB input pin is used Fig

8 shows an example of microcontroller dsPIC30F4013 connection to the inverter including the feedback error signal The inverter controls the operation of motor M

Fig 8 dsPIC30F4013 connection to the inverter including the feedback error

signal

• PWM MODE WITHOUT FAULT PROTECTION INPUT PWM MODE WITHOUT FAULT PROTECTION INPUT

When control bits OCM<2:0> are set to 110, the output compare module operates in this mode In PWM mode the OCxR register is a read only slave duty cycle register The OCxRS is a buffer register written by the user to update the PWM duty cycle.On every timer to period register match event (end of PWM period), the duty cycle register, OCxR, is loaded with the contents of OCxRS.The interrupt flag is asserted at the end of each PWM period

When configuring the output compare module for PWM mode of

operation, the following steps should be taken:

1 Set the PWM period by writing to the selected timer period register, PRy

2 Set the PWM duty cycle by writing to the OCxRS register

3 Write the OCxR register with the initial duty cycle

4 Enable interrupts for the selected timer

5 Configure the output compare module for one of two PWM operation modes by writing 100 to control bits OCM<2:0> (OCxCON<2:0>)

6 Set the TMRy prescale value and enable the selected time base

• PWM MODE WITH FAULT PROTECTION INPUT PIN PWM MODE WITH FAULT PROTECTION INPUT PIN

When the control bits OCM<2:0> areset to 111, the outpu

compare module is configured for the PWM mode of operation

All functions derscribed in section above are applied, with the

addition that in this mode in addition to the output pin OCX the

use is made of the signal from the input pin OCxFA for the

output compare channels 1 to 4 or from the inpit pin OCxFB for

the output compare channels 5 to 8 The signal at input pin

OCxFA or OCxFB is a feedback error signal of the inverter

related to a possible hazardous state of operation of the

inverter If the input pin OCxFA or OCxFB is low, the inverter is

onsidered to be in a hazardous (error) state Then the output

OCx pin of the output compare module operating in the PWM

mode is disabled automatically and the pin is driven to the high

module In the state of inverter fault, upon detection of the fault condition and disabling of pin OCx, the respective interrupt flag is asserted and in the register OCxCON the OCFLT bit (OCxCON<4>) is set If enabled, an interrupt of the output compare module will be generated

4

4 PWM PERIOD AND DUTY CYCLE CALULATIONPWM PERIOD AND DUTY CYCLE CALULATIONPWM PERIOD AND DUTY CYCLE CALULATION

• PWM PERIOD PWM PERIOD

The PWM period, specified by the value in the PRy register of the selected timer y, is calculated by:

TPWM=(PRy +1)TCY(TMRy prescale value)

TPWM=(PRy +1)TCY(TMRy prescale value)

and the PWM frequencyby:

fPWM=1/TPWM

fPWM=1/TPWM

Example:

Example:

Calculation of the PWM period for a microcontroller having a 10MHz clock with x4 PLL, Device clock rate is 40MHz The instruction clock frequency is FCY=FOSC/4, i.e 10MHz Timer

2 prescale setting is 4 Calculate the PWM period for the maximum value PR2=0xFFFF=65535

TPWM = (65535+1) x 0.1•s x (4) = 26.21 ms, i.e fPWM = 1/TPWM = 38.14 Hz

• PWM DUTY CYCLEPWM DUTY CYCLEWM DUTY CYCLE

The PWM duty cycle is specified by the value written to the register OCxRS It can be written to at any time within the PWM cycle, but the duty cycle value is latched into OCxR when the PWM period is completed OCxR is a read only register This provides a double buffering for the PWM duty cycle

If the duty cycle register,OCxR, is loaded with 0000, the duty cycle is zero and pin OCx will remain low throughout the PWM period

If the duty cycle register is greater that PRy, the output pin OCx will remain high throughout the PWM period (100% duty cycle)

If OCxR is equal to PRy, the OCx pin will be high in the first PWM cycle and low in the subsequent PWM cycle

• MAXIMUM RESOLUTION MAXIMUM RESOLUTION

The maximum resolution is calculated by the following formula: Max

Max PWM resolution [bits] = (log PWM resolution [bits] = (log10TPWM TPWM –––– log log10(TCY x prescale value TMRy)) / log1022

Example:

Example:

Calculation of the PWM period for a microcontroller having a 10MHz clock with x4 PLL, Device clock rate is 40MHz The instruction clock frequency is FCY=FOSC/4, i.e 10MHz Timer

2 prescale setting is 4 Calculate the maximum resolution for PWM frequency 48Hz

Max PWM resolution [bits] = (log10(1/48) – log10(0.1•s x 4)) / log102 = 15.66 bits

For this value of the PWM period and other selected parameters (prescale value, clock) it turns out that the PWM mode operates with almost maximum resolution

Fig 9 Timing diagram of the PWM mode of the output compare module

5

5 OPERATION OF THE OUTPUT COMPARE MODULE IN SLEEP OR OPERATION OF THE OUTPUT COMPARE MODULE IN SLEEP OR IDLE MODE

IDLE MODE

• Operation of the output compare module in SLEEP mode Operation of the output compare module in SLEEP mode

When the device enters SLEEP mode, the system clock is disabled During SLEEP, the state of the output pin OCx is held

at the same level as prior to entering SLEEP For example, if the output pin OCx was high and the CPU entered the SLEEP state, the pin will stay high until the the microcontroller wakes up

• Operation of the output compare module in IDLEOperation of the output compare module in IDLEIDLE mode mode mode

When the device enters IDLE mode, the OCSIDL control bit (OCxCON<13>) selects if the output compare module will stop

or continue operation in IDLE mode

If OCSIDL = 0, the module will continue operation only if if the selected time base is set to operate in IDLE mode (TSIDL = 0)