Introduction to input capture

The input capture module has multiple operating modes selectable via the ICxCON register control bit ICM:  Select by external input signal mode,  Interrupt by external input signal m

INPUT CAPTURE MODULE

mainly used for the frequency or time period measurements and pulse measurements (e.g mean count rate measurement) Microcontroller dsPIC30F4013 contains 4 input capture modules, whereas dsPIC30F6014A contains 8 input capture modules

The input capture module has multiple operating modes selectable via the ICxCON register (control bit ICM<2:0>):

 Select by external input signal mode,

 Interrupt by external input signal mode

setting the control bits a user can select the number of captures from the counter before the input capture module generates an interrupt request

Fig 1 Functional diagram of the inpuit capture module

1 EXTERNAL SIGNAL CAPTURE INPUT MODE

In the family of dsPIC30F microcontrollers the select by external input signal mode implies selecting the value from the TMR2 or TMR3 counter depending on the external input signal at pin ICx The capture can be carried out depending on the external input signal:

 On every falling edge of input signal applied at the ICx pin,

 On every rising edge of input signal applied at the ICx pin,

 On every risinig and every falling edge of input signal applied at the ICx pin,

 On every fourth rising edge of input signal applied at the ICx pin,

 On every 16th rising edge of input signal applied at the ICx pin,

The selection of the input captue mode is carried out by setting the control bits ICM<2:0> in the register ICxCON<2:0> Also,

by setting the control bits ICM<2:0> the reduction ratio in the prescaler 1, 4 , or 16 is set

The simple capture mode, or the mode of simple capture, is the

every rising edge or every falling edge of the external input signal at the input pin ICx In this mode the logic of the input capture module detects the change of the logical level at the input pin ICx, synchronizes the change with the phase of the internal clock, captures the value of the counter TMR2 or TMR3 and puts it into the FIFO buffer memory The prescaler operates wth the ratio 1:1, i.e without reduction

Since the input capture module comprises a four-level FIFO buffer, by setting the control bit ICI<1:0> (ICxCON<6:5>) it is possible to select the number of captures before an interrupt is generated In this way capturing of fast external signals is made possible because while the counter values are captured and put into the FIFO buffer, it is possible to read previous values in the buffer and transfer them to the data memory

Selection of the counter of the timer module which is to be captured is done by setting the control bit ICTMR (ICxCON<7>)

It is possible to select the 16-bit counters TMR2 (ICTMR=1) or TMR3 (ICTMR=0)

During interrupt routine clearing the interrupt Input Capture module request flag is mandatory and the captured value is read form the FIFO buffer In setting timer2 the preset register PR2 is set at the maximum value in order to ensure operation of the timer in the free-running mode over the full range of values, from 0 to 65535 Input Capture module 1 is configured to capture values of timer 2 on falling edge of the signal at IC1 pin

In this mode of operation of the input capture module the external signal is prescaled by the ratio 1:4 or 1:16 by setting the control bit ICM<2:0> to the values 100 or 101 respectively

In this way it is possible that the input capture module captures total value of the counter TMR2 or TMR3 for 4 or 16 periods of

mean count rate by averaging 4 or 16 periods of an external input signal

By setting the control bit IC1<1:0> (ICxCON<6:5>) it is also possible, like in the simple capture mode, to select the number

of captures after which an interrupt request is generated

The selection of the timer module which is to be sampled is done by setting the control bit ICTMR (ICxCON<7>)

During interrupt routine clearing the interrupt Input Capture

read form the FIFO buffer In setting timer2 the preset register PR2 is set at the maximum value in order to ensure operation of the timer in the free-running mode over the full range of values, from 0 to 65535 Input Compaer module 1 is configured to

capture values of timer 2 on each fourth rising edge of the signal at IC1 pin

Capturing the value of TMR2 or TMR3 counter can be done on every rising and every falling edge of the external input signal applied to the ICx pin The edge detection mode is selected by setting the ICM<2:0> (ICxCON<2:0>) control bits to 001 In this mode the prescaler counter can not be used The input capture module interrupt request is generated on every rising and every falling edge (ICxIF bit is set) It not possible to generate an interrupt request after 2, 3, or 4 captures by setting the control bits ICI<1:0> (ICxCON<6:5>) because in

interrupt As a consequence no overflow of the FIFO buffer is possible

Fig 2 An example of setting the captured value delayed by 1 or

2 instruction cycles TCY

Reading data from FIFO buffer – Each input capture module comprises a four-level (16-bit) FIFO buffer for accomodation of the captures The access to the captures in the FIFO buffer is via the ICxBUF register In addition, there are two status flags

of the FIFO buffer The ICBNE status flag denotes that the FIFO buffer is not empty This flag is cleared by hardware when the last word is read from the FIFO buffer or during the reset of the input capture module by setting the control bits ICM<2:0> to value 000 ICBNE is also reset during RESET

The other status flag ICOV denotes the state of overflow of the FIFO buffer, i.e when after four captures which have not been transferred to the data memory the fifith capture is being put in

No interrupt request is generated then, the ICOV bit is set and the values of the five captures and all subsequent captures are ignored Clearing of this bit is done by hardware upon reading

of all four captures from the FIFO buffer, or by resetting of the input capture module Also, the microcontroller RESET clears this flag

2 EXTERNAL SIGNAL INTERRUPT MODE

The input pins of the input capture module can be used as additional external interrupt sources if the input capture module is configured for operation in the external signal

ICM<2:0> are set to 111 Then, the input pins ICx on rising edge generate an interrupt request ICxIF If the interrupt enable bit ICxIE is set and the interrupt priority level ICxIP<2:0>is defined, the microcontroller enters an interrupt

The input capture module is very often used by the UART module for autodetection of the baud rate In the autobaud mode the UART module is configured as follows: the control bit ABAUD (UxMODE<5>) is set i.e the UART RX pin is internally connected to the input capture module input and the ICx pin is disconnected from the rest of the input capture module.The

baud rate is measured by measuring the the width of the START bit when a NULL character is received Care should be taken that the input capture module is configured for the edge detection mode For each microcontroller of the family dsPIC30F the input capture module assignment for each UART has been defined

3 INPUT CAPTURE OPERATION IN SLEEP AND IDLE MODES

In SLEEP mode, the system clock is disabled, i.e the input capture module can only function as an external interrupt source This mode is enabled by setting control bits ICM<2:0>

to 111 A rising edge on the ICx input pin will generate an input capture module interrupt If the interrupt is enabled for this input pin, the microcontroller will wake-up from SLEEP

In the event the input capture module has been configured for

a mode other than ICM<2:0>=111 and the microcontroller enters the SLEEP mode, no external signal, rising or falling, can generate a wake-up condition from SLEEP

Operation of the input capture module in IDLE mode is specified by the control bit ICSIDL (ICxCON<13>) If ICSIDL= 0, the module will continue operation in IDLE mode with full functionality in all the above mentioned modes The prescaler is fully functional in this mode

If ICSIDL=1, the module will stop in IDLE mode Then, the input capture module can operate only in the external signal interrupt mode, i.e the control bits ICM<2:0>=111 A rising edge on the

ICx input pin will generate an input capture module interrupt If

the interrupt is enabled for this input pin, the microcontroller

will wake-up from IDLE state

In the event the input capture module has been configured for

a different mode and the microcontroller enters the IDLE mode

with the control bit ICSIDL is set, no external signal, rising or

falling, can generate a wake-up condition from IDLE state

Ex:

Fig 3 Pin diagram of dsPIC30F4013 Description of the registers of the input capture module of

microcontroller dsPIC30F4013:

Table 1 Input capture module registers

N A M E A D R 1 5 1 4 1 3 1 2

-8 7 6 5 4 3 2 1 0

R E S E T

S T A T E IC1BUF 0x0140 Input 1 Capture Buffer Register 0xuuuu IC1CON 0x0142 - - ICSIDL - ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0x0000 IC2BUF 0x0144 Input 2 Capture Buffer Register 0xuuuu IC2CON 0x0146 - - ICSIDL - ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0x0000 IC7BUF 0x0158 Input 7 Capture Buffer Register 0xuuuu

IC7CON 0x015A - - ICSIDL - ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0x0000 IC8BUF 0x015C Input 8 Capture Buffer Register 0xuuuu IC8CON 0x015E - - ICSIDL - ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0x0000

ICSIDL – Input capture module stop in IDLE control bit

(ICSIDL=0 input capture module will continue to operate

in IDLE mode,

ICSIDL=1 input capture module will halt in IDLE mode)

ICTMR – Input capture timer select bits (ICTMR=0 TMR3

contents are captured on capture event,

ICTMR=1 TMR2 contents are captured on capture event)

ICI <1:0> - Select number of captures per interrupt bits

00 – interrupt on every capture event

01 – interrupt on every second capture event

10 – interrupt on every third capture event

11 – interrupt on every fourth capture event

ICOV – FIFO buffer overflow status flag (read only) bit

ICBNE – FIFO buffer buffer empty status (read only) bit

(ICBNE=0 FIFO buffer empty, ICBNE=1 FIFO buffer contains at least one capture value

ICM <2:0> - Input capture mode select bits

000 – Input capture module turned off

001 – Capture mode, every edge (rising or falling)

010 – Capture mode, every falling edge

011 – Capture mode, every rising edge

100 – Capture mode, every 4th rising edge

101 – Capture mode, every 16th rising edge

110 – Unused (module disabled)

111 – Input capture module in external signal interrupt mode

(external source of interrupt requests)