Homework 5 writing DCT8bit test bench

VLSI DESIGN AUTOMATION Homework 5 Update “INPUTOUTPUT” block function for CPU and writing DCT8bit test bench VLSI DESIGN AUTOMATION Homework 5 Update “INPUTOUTPUT” block function for CPU and writing DCT8bit test bench

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VLSI DESIGN AUTOMATION

Homework #5

Update “INPUT-OUTPUT” block function for CPU and writing DCT-8bit test bench

Student: Bui Huu Nguyen

Student ID: 2016310539 Submit date: 2016/11/15

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A Block System structure that inset IN and OUT port

ALU_Port

RAM_Port

PC_Port

SEQ_Port

IR_Port

1 ACC_bus

2 load_ACC

3 PC_bus

4 load_PC

5 load_IR

6 load_MAR

7 MDR_bus

8 load_MDR

9 ALU_ACC

10 ALU_add

11 ALU_sub

12 INC_PC

13 Addr_bus

14 CS

15 R_NW

16 load_IN

17 load_OUT

18 INS

19 OUTS

20 IN_bus

21 OUT_bus

BUS

z_flag op

5-13

6-7-8-14-15

1-2-9-10-11 3-4-12

CPU_Bus

OUT_Port

IN_Port

17-19-21 15-16-18-20

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B Sequencer state

// Project: Simple CPU

// File : IN.sv

import cpu_defs::*;

module IN (CPU_bus.IN_port bus, input wire

[WORD_W-1:0] Data_IN);

logic [WORD_W-OP_W-1:0] indata;

assign bus.sysbus = bus.IN_bus ? indata : 'z;

//always_ff @(posedge bus.clock, negedge

bus.n_reset)

always_ff @(posedge bus.clock)

begin

if (!bus.n_reset) indata <= 0;

else

if (bus.load_IN) indata <= bus.sysbus;

else if (bus.INS)

if (bus.R_NW) indata <= Data_IN;

end endmodule

S0

n_reset = 1

S3

S9 S10

S8

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//

// File : OUT.sv

//

import cpu_defs::*;

module OUT (CPU_bus.OUT_port bus, output

logic [WORD_W-1:0] Data_OUT);

logic [WORD_W-OP_W-1:0] outdata;

assign bus.sysbus = bus.OUT_bus ? outdata : 'z;

//always_ff @(posedge bus.clock, negedge

bus.n_reset)

always_ff @(posedge bus.clock)

begin

if (!bus.n_reset) begin

Data_OUT <= 0;

outdata <= 0;

end else

if (bus.load_OUT) outdata <= bus.sysbus;

else if (bus.OUTS) Data_OUT <= outdata;

end endmodule

Code CPU test bench for IN and OUT

…

initial begin

n_reset=0;

@(posedge clock)

n_reset=1;

Data_IN = 10'd10;

@(posedge clock)

repeat (5) @(posedge clock);

Data_IN = 10'd12;

………

always@(posedge clock) begin

clk_count = clk_count + 1;

end

CPU CPU_u1(clock, n_reset, sysbus, Data_IN,

Data_OUT);

endmodule

RAM code:

mem[0] <= {IN, 7'd16};// read Input mem[1] <= {ADD, 7'd17}; // Input + mem[17] mem[2] <= {OUT, 7'd18};// write result for Output

……

mem[17] <= 10;

// Output = 10+10 = 20

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C Results

D DCT-8bit

- Code CPU test bench for CPU

- Code RAM that includes extending memory from 5-bit to 16-bit address

//CPU_test bench.sv

……

initial begin

n_reset=0;

@(posedge clock)

n_reset=1;

Data_IN = 10'd1;

@(posedge clock)

Data_IN = 10'd2;

Data_IN = 10'd3;

Data_IN = 10'd4;

Data_IN = 10'd5;

Data_IN = 10'd6;

Data_IN = 10'd7;

Data_IN = 10'd8;

End

……

Data_OUT =20 Data_IN =10

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//

// File : RAM.sv

//

import cpu_defs::*;

module RAM (CPU_bus.RAM_port bus, input wire

[8:0] msb_count);

logic [WORD_W-1:0] mdr;

logic [WORD_W-OP_W-1:0] mar;

logic [WORD_W-1:0] mem [0:(1<<16)-1];

//logic [3:0] j;

int i;

int j;

logic [15:0] count;

assign count = {msb_count, mar};

assign bus.sysbus = bus.MDR_bus ? mdr : 'z;

always_ff @(posedge bus.clock, negedge

bus.n_reset)

begin

if (!bus.n_reset)

begin

mdr <= 0;

mar <= 0;

for (i = 0; i < 65535; i+=1) mem[i] <= 0;

//row1

mem[0] <= 3;

mem[1] <= 8;

mem[2] <= 8;

mem[3] <= 3;

mem[4] <= 8;

mem[5] <= 8;

mem[6] <= 8;

mem[7] <= 8;

//2

mem[8] <= 11;

mem[9] <= 9;

mem[10] <= 6;

mem[11] <= 2;

mem[12] <= -2;

mem[13] <= -6;

mem[14] <= -9;

mem[15] <= -11; //3

mem[16] <= 10; mem[17] <= 4; mem[18] <= -4; mem[19] <= -10; mem[20] <= -10; mem[21] <= -4; mem[22] <= 4; mem[23] <= 10; //4

mem[24] <= 9; mem[25] <= -2; mem[26] <= -11; mem[27] <= -6; mem[28] <= 6; mem[29] <= 11; mem[30] <= 2; mem[31] <= -9; //5

mem[32] <= 8; mem[33] <= -8; mem[34] <= -8; mem[35] <= 8; mem[36] <= 8; mem[37] <= -8; mem[38] <= -8; mem[39] <= 8; //6

mem[40] <= 6; mem[41] <= -11; mem[42] <= 2; mem[43] <= 9; mem[44] <= -9; mem[45] <= -2; mem[46] <= 11; mem[47] <= -6; //7

mem[48] <= 4; mem[49] <= -10; mem[50] <= 10; mem[51] <= -4; mem[52] <= -4; mem[53] <= 10; mem[54] <= -10;

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mem[55] <= 4;

//8

mem[56] <= 2;

mem[57] <= -6;

mem[58] <= 9;

mem[59] <= -11;

mem[60] <= 11;

mem[61] <= -9;

mem[62] <= 6;

mem[63] <= -2;

//

mem[128] <= {IN, 7'd0}; // load input store to

RAM

mem[129] <= {STORE, 7'd64};

mem[130] <= {IN, 7'd0};

mem[131] <= {STORE, 7'd65};

mem[132] <= {IN, 7'd0};

mem[133] <= {STORE, 7'd66};

mem[134] <= {IN, 7'd0};

mem[135] <= {STORE, 7'd67};

mem[136] <= {IN, 7'd0};

mem[137] <= {STORE, 7'd68};

mem[138] <= {IN, 7'd0};

mem[139] <= {STORE, 7'd69};

mem[140] <= {IN, 7'd0};

mem[141] <= {STORE, 7'd70};

mem[142] <= {IN, 7'd0};

mem[143] <= {STORE, 7'd71};

////

for (j = 0; j < 8; j+=1)

begin

mem[500+j*34] <= {LOAD, 7'd0+j*8};

mem[500+j*34] <= {MUL, 7'd64};