tài liệu lập trình PLC S7 300

The result of the logic operation Address Registers AR1 and AR2 32 Bits The address registers contain the area-internal or area-crossing ad-dresses for instructions using indirect addres

Trang 1

CPU 312 IFM, 314 IFM,

313, 314, 315, 315-2 DP, 316-2 DP, 318-2

6ES7 398-8AA03-8BN0

Edition 1

Trang 2

! !

!

! !"!

Bit Logic Instructions 28

Bit Logic Instructions with Parenthetical Expressions 36

ORing of AND Operations 38

Logic Instructions with Timers and Counters 40

Word Logic Instructions with the Contents of Accumulator 1 44

Evaluating Conditions Using AND, OR and EXCLUSIVE OR 46

Edge-Triggered Instructions 60

Setting/Resetting Bit Addresses 64

Instructions Directly Affecting the RLO 70

Timer Instructions 72

Counter Instructions 76

Load Instructions 78

Load Instructions for Timers and Counters 88

Transfer Instructions 90

Load and Transfer Instructions for Address Registers 98

Load and Transfer Instructions for the Status Word 102 Load Instructions for DB Number and DB Length 104 Integer Math (16 Bits) 106

Integer Math (32 Bits) 108

Floating-Point Math (32 Bits) 110

Square Root and Square Instructions (32 Bits) 112

Logarithmic Function (32 Bits) 114

Trigonometrical Functions (32 Bits) 116

Adding Constants 118

Adding Using Address Registers 120

Comparison Instructions with Integers (16 Bits) 122

Comparison Instructions with Integers (32 Bits) 124

Comparison Instructions with Real Numbers (32 Bits) 126

Shift Instructions 128

Rotate Instructions 132

Accumulator Transfer Instructions, Incrementing and Decrementing 134

Program Display and Null Operation Instructions 136

Data Type Conversion Instructions 138

Forming the Ones and Twos Complements 142

Block Call Instructions 144

Block End Instructions 148

Exchanging Shared Data Block and Instance Data Block 150

Jump Instructions 152

Instructions for the Master Control Relay (MCR) 160 ! % !"!

Convention:

In the following, the CPU 312 IFM is called CPU 312*

In the following, the CPU 314 IFM is called CPU 314*

In the following, the CPU 315-2 DP is called CPU 315-2

In the following, the CPU 316-2 DP is called CPU 316-2

Trang 3

Address Identifiers and Parameter

1 PIQ is preset to 256 byte

Trang 4

Addr Parameter Ranges

Data bit in instance DB

Local data bit

1 PII is preset to 256 byte

2 Local data area is preset to 4096 byte

Trang 5

Bit memory bit

Trang 6

Parameter Ranges

316–2

PQB 0 to 31 0 to 31 0 to 767 0 to 751 0 to 767 0 to 1023 0 to 8191 Peripheral output byte

(direct I/O access)Q

(direct I/O access)

124 to 125

(direct I/O access)

256 to 383 256 to 383

PIW 0 to 30 0 to 30 0 to 766 0 to 750 0 to 766 0 to 1022 0 to 8190 Peripheral input word

(direct I/O access)124

W#16#

DW#16#

WordDouble wordhexadecimal

Trang 7

Addr.

316

Trang 8

Abbreviations and Mnemonics

The following abbreviations and mnemonics are used in the

p Hexadecimal constant EA12

q Real number (32-bit

Trang 9

ACCU1 and ACCU2 (32 Bits)

The accumulators are registers for processing bytes, words or

double words The operands are loaded into the accumulators,

where they are logically gated The result of the logic operation

Address Registers AR1 and AR2 (32 Bits)

The address registers contain the area-internal or area-crossing

ad-dresses for instructions using indirect addressing The address

regis-ters are 32 bits long

The area-internal and/or area-crossing addresses have the following

Status Word (16 Bits)

The status word bits are evaluated or set by the instructions.The status word is 16 bits long

1 RLO Result of (previous) logic operation

Trang 10

L B#(100,12) Load 2-byte constant

L B#(100,12,50,8) Load 4-byte constant

L P#10.0 Load area-internal pointer into

L TOD#13:20:33.125 Load time of day

Direct Addressing

ACCU1

Indirect Addressing of Timers/Counters

SP T [LW 8] Start timer; the timer number is

in local word 8

CU C [LW 10] Start counter; the counter

num-ber is in local data word 10

Area-Internal Memory-Indirect Addressing

A I [DBD 1] AND operation: The address of

the input is in data doubleword 1 of the DB as pointer

A Q [DID 12] AND operation: The address of

the output is in data doubleword 12 of the instance DB aspointer

A Q [MD 12] AND operation: The address of

the output is in memory markerdouble word 12 of the instance

DB as pointer

Trang 11

Addressing Examples Description

Area-Internal Register-Indirect Addressing

A I [AR1,P#12.2] AND operation: The address of

the input is calculated from the

“pointervalue in AR1+

P#12.2”

Area-Crossing Register-Indirect Addressing

For area-crossing register-indirect addressing, bits 24 to 26 of the

address must also contain an area identifier The address is in the

address register

identifier (binary) hex.

DI 1000 0101 85 Instance data area

L 1000 0110 86 Local data area

VL 1000 0111 87 Predecessor local data

(access to local data ofinvoking block seepage 15)

L B [AR1,P#8.0] Load byte into ACCU1: The

address is calculated from the

“pointer value in AR1+ P#8.0”

A [AR1,P#32.3] AND operation: The address of

the operand is calculated fromthe “pointer value in AR1+

P#32.3”

Addressing Via Parameters

A Parameter Addressing via parameters

Examples of how to calculate the pointer

Example for sum of bit addresses 7:

LAR1 P#8.2

A I [AR1,P#10.2]

Result: Input 18.4 is addressed (by adding the byte and bit

addresses)

Example for sum of bit addresses 7:

L MD 0 Random pointer, e.g P#10.5LAR1

A I [AR1,P#10.7]

Result: Input 21.4 is addressed (by adding the byte and bit

addresses with carry)

Trang 12

Execution Times with Indirect

Addressing

You must calculate the execution times when using indirect

addres-sing This chapter shows you how

Two-Part Statement

A statement with indirectly addressed instructions consists of two

parts:

Part 1: Load the address of the instruction

Part 2: Execute the instruction

In other words, you must calculate the execution time of a

state-ment with indirectly addressed instructions from these two parts

Calculating the Execution Time

The total execution time is calculated as follows:

Time required for loading the address

+ execution time of the instruction

= Total execution time of the instruction

The execution times listed in the chapter entitled “List of

Instruc-tions” apply to the execution times of the second part of an

instruc-tion, i.e for the actual execution of an instruction

You must then add the time required for loading the address of the

instruction to this execution time (see Table on following page)

The execution time for loading the address of the instruction fromthe various areas is shown in the following table You will also findthis table on the fold-out part of the cover

You do not have to change the page when calculating the executiontime

Execution Time in s Address is in 312*/

1.73.5

0.72.3

0.82.1

0.20.3Data block DB/DX

WordDouble word

5.26.7

2.83.9

3.04.1

0.20.3Local data area L

WordDouble word

2.03.7

0.82.6

0.92.2

0.20.3AR1/AR2 (area-internal) 3.0 1.9 1.7 0.0AR1/AR2 (area-crossing) 4.9 3.9 3.2 0 0Parameter (word) for:

The pages that follow contain examples for calculating the tion run time for the various indirectly addressed instructions

Trang 13

instruc-Examples of Calculations (for the CPU 314)

You will find a few examples here for calculating the execution

times for the various methods of indirect addressing Execution

times are calculated for the CPU 314

Calculating the Execution Times for Area-Internal

Memory-Indirect Addressing

Example: A I [DBD 12]

Step 1: Load the contents of DBD 12 (time required is listed

in the table on page 21)

Address is in Execution Time in s

Bit memory area M

Word

Double word

0.72.3Data block DB/DI

Word

2.8

Step 2: AND the input addressed in this way (you will find

the execution time in the tables in the chapter entitled

“List of Instructions”

Typical Execution Time in s Direct Addressing Indirect Addressing

0.2:

Trang 14

Calculating the Execution Time for Area-Internal

Register-Indirect Addressing

Example: A I [AR1, P#34.3]

Step 1: Load the contents of AR1, and increment it by the

offset 34.3 (the time required is listed in the table on

Typical Execution Time in s

Direct Addressing Indirect Addressing

Typical Execution Time in s Direct Addressing Indirect Addressing

0.2:

Trang 15

Execution Time for Addressing Via Parameters

Example: A Parameter with I 0.5 in the block parameter list

Step 1: Load input I 0.5 addressed via the parameter (the

time required is in the table on page 21)

Address is in Execution Time in s

Direct Addressing Indirect Addressing

Trang 16

List of Instructions

This chapter contains the complete list of S7-300 instructions The

descriptions have been kept as concise as possible You will find a

detailed functional description in the various STEP 7 reference

manuals

Please note that, in the case of indirect addressing (examples see

page 16), you must add the time required for loading the address ofthe particular instruction to the execution times listed (see page 21)

Bit Logic Instructions

Examining the signal state of the addressed instruction and gatingthe result with the RLO according to the appropriate logic function

312*

313

314 314*

315 315-2 316-2

318-2 312*

313

314 314*

315 315-2 316-2

1 2/2

1 2/2222

0.71.52.25.25.2

0.20.60.82.72.7

0.30.60.92.82.8

Area-crossing via (AR2)Via parameter

22222

–––––

+++++

1 Plus time required for loading the address of the instruction

(see page 21)

2 With direct instruction addressing

Adress area 0 to 127

Trang 17

In- Length Typical Execution Time in s

315 315-2 316-2

318-2 312*

313

314 314*

315 315-2 316-2 318-2

1 2/2

1 2/2222

0.40.70.93.6

1.41.92.55.55.5

0.50.70.93.03.0

0.50.81.03.13.1

0.10.10.10.10.1

22222

–––––

+++++

(see page 21)

Adress area 0 to 127

Trang 18

315 315-2 316-2

318-2 312*

313

314 314*

315 315-2 316-2 318-2

1 2/2

1 2/2222

0.71.52.25.25.2

0.20.60.82.72.7

0.30.70.92.92.9

0.10.10.10.10.1

22222

–––––

+++++

+++++ON

13/2

12/2222

1.41.92.55.55.5

0.50.70.93.03.0

0.50.81.03.13.1

0.10.10.10.10.1

22222

–––––

+++++

(see page 21)

Trang 19

315 315-2 316-2

318-2 312*

313

314 314*

315 315-2 316-2 318-2

22222

0.71.52.25.25.2

0.20.60.82.82.8

0.30.70.92.92.9

0.10.10.10.10.1

22222

–––––

+++++

+++++XN

Bit memoryLocal data bitData bitInstance data bit

22222

1.41.92.55.55.5

0.50.70.93.03.0

0.50.81.03.13.1

0.10.10.10.10.1

22222

–––––

+++++

(see page 21)

Trang 20

Bit Logic Instructions with Parenthetical

Expressions

Saving the BR, RLO and OR bits and a function identifier

(A, AN, ) to the nesting stack Seven nesting levels are possible

312*/313 314/314* 315/315-2

entry off the nesting stack, ing the RLO with the currentRLO in the processor

Trang 21

ORing of AND Operations

The ORing of AND operations is implemented according to the

rule: AND before OR

312*/313 314/314* 315/315-2/

according to the rule:

AND before OR

Trang 22

Logic Instructions with Timers and

Counters

Examining the signal state of the addressed timer/counter and

gating the result with the RLO according to the appropriate

315 315-2 316-2

318-2 312*

313

314 314*

315 315-2 316-2 318-2

A

T

C

ANDTimerCounter

1 2/2

2.41.7

0.80.6

0.90.6

0.10.1

Counter p

Timer/counter (addressed via parameter)

–

––

++

AN

T

C

AND NOTTimerCounter

13/2

1 2/2

3.02.4

1.00.8

1.10.9

0.10.1

Counter p

Timer/counter (addressed via parameter)

–

––

++

(see page 21)

Trang 23

0.90.6

0.10.1

Counter p

OR timer/counter(addressed via parameter)

–

––

++

1.00.8

1.10.9

0.10.1

Counter p

OR NOT timer/counter(addressed via parameter)

–

––

++

C

EXCLUSIVE OR timerEXCLUSIVE OR counter

22

2.41.7

0.80.6

0.90.6

0.10.1

Counter p

EXCLUSIVE OR timer/counter(addressed via parameter)

22

––

++

3.02.4

1.01.0

1.10.9

0.10.1

Counter p

EXCLUSIVE OR NOTtimer/counter (addressed viaparameter)

–

––

++

(see page 21)

Trang 24

Word Logic Instructions with the

Contents of Accumulator 1

Gating the contents of ACCU1 and/or ACCU1-L with a word or

double word according to the appropriate function The word or

double word is either a constant in the instruction or in ACCU2.The result is in ACCU1 and/or ACCU1-L

Trang 25

Evaluating Conditions Using AND, OR

and EXCLUSIVE OR

Examining the specified conditions for their signal status, and

gat-ing the result with the RLO accordgat-ing to the appropriate function

<=0 Result<=0

((CC 1=0) and (CC 0=1) or(CC 1=0) and (CC 0=0))

>=0 Result>=0

Trang 26

Trang 27

312*/313 314/314* 315/315-2/

Result=0(CC 1=0) and (CC 0=0)

<=0 Result<=0

>=0 Result>=0

Trang 28

312*/313 314/314* 315/315-2/

<=0 Result<=0

>=0 Result>=0

Trang 29

312*/313 314/314* 315/315-2/

<=0 Result<=0

>=0 Result>=0

Trang 30

312*/313 314/314* 315/315-2/

<=0 Result<=0

>=0 Result>=0

Trang 31

312*/313 314/314* 315/315-2/

<=0 Result<=0

>=0 Result>=0

Trang 32

Edge-Triggered Instructions

Detection of an edge change The current signal state of the RLO is

compared with the signal state of the instruction or “edge bit

memory” FP detects a change in the RLO from “0” to “1”; FN

detects a change in the RLO from “1” to “0”

315 315-2 316-2

318-2 312*

313

314 314*

315 315-2 316-2 318-2

222

2.03.5

3 8

0.71.4

1 5

0.81.5

1 6

0.20.2

3.86.76.7

1.52.02.0

1.64.04.0

0.20.20.2

–––––

+++++

(see page 21)

Trang 33

315 315-2 316-2

318-2 312*

313

314 314*

315 315-2 316-2 318-2

22222

2.63.84.26.86.8

0.91.61.72.22.2

1.01.61.74.14.1

0.20.20.20.20.2

–––––

+++++

(see page 21)

Trang 34

Setting/Resetting Bit Addresses

Assigning the value “1” or “0” or the RLO o the addressed

instruc-tion The instructions can be dependent on the MCR

312*

313

314 314*

315 315-2 316-2

318-2 312*

313

314 314*

315 315-2 316-2 318-2

0.31.40.83.01.23.13.34.53.34.5

0.30.50.82.31.32.93.74.33.74.3

0.20.20.20.20.20.20.20.20.20.2

Register–ind., area–internal(AR2)

Area-crossing via (AR1)Area-crossing via (AR2)Via parameter

22222

–––––

+++++

(see page 21)

Trang 35

313

314 314*

315 315-2 316-2

318-2 312*

313

314 314*

315 315-2 316-2 318-2

0.41.40.93.11.23.23.54.63.54.6

0.40.50.92.41.33.03.84.33.84.3

0.20.20.20.20.20.20.20.20.20.2

Register–ind., area–internal(AR2)

Area-crossing via (AR1)Area-crossing via (AR2)Via parameter

22222

–––––

+++++

(see page 21)

Trang 36

313

314 314*

315 315-2 316-2

318-2 312*

313

314 314*

315 315-2 316-2 318-2

Assign RLO to data bit(MCR-dependent)Assign RLO to instance data bit(MCR-dependent)

0.21.40.93.01.03.13.35.33.35.3

0.30.50.92.31.12.63.84.43.84.4

0.20.20.20.20.20.20.20.20.20.2

Register–ind., nal(AR2)

area–inter-Area-crossing via (AR1)Area-crossing via (AR2)Via parameter

22222

–––––

+++++

(see page 21)

Trang 37

Instructions Directly Affecting the RLO

The following instructions have a direct effect on the RLO

Trang 38

Timer Instructions

Starting or resetting a timer (addressed directly or via a parameter)

The time value must be in ACCU1-L

312*

313

314 314*

315 315-2 316-2

318-2 312*

313

314 314*

315 315-2 316-2 318-2

SP T f Start timer as pulse on edge

SE T f Start timer as exded pulse on

edge change from“0”to“1”

Timer para

pedge change from “0” to “1”

SS T f Start timer as retive ON delay

on edge change from“0”to“1”

SF T f Start timer as OFF delay on

edge change from“1”to“0”

Timer para

yedge change from “1” to “0”

Trang 39

313

314 314*

315 315-2 316-2

318-2 312*

313

314 314*

315 315-2 316-2 318-2

FR T f Enable timer for restarting on

edge change from “0” to “1”(

Trang 40

313

314 314*

315 315-2 316-2

318-2 312*

313

314 314*

315 315-2 316-2 318-2

S C f Presetting of counter on edge

FR C f Enable counter on edge change

from “0” to “1” (reset edge bit

List of Instructions

This chapter contains the complete list of S7- 300 instructions The

descriptions have been kept as concise as possible You will find a

Định dạng
Số trang	89
Dung lượng	685,04 KB