Công nghệ vi điện tử

Công nghệ vi điện tử

CONG NGHE VI DiEN TU (Microelectronic Technology)

Chuong 8: Basic Design

(30 hours)

Noi dung

Eee creer

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Ll Concepts

L] Multiplexers

Ll Encoders

L] Priority Encoders

Ll Decoders

LI Comparators

LI BCD to 7 SEGMENT

LJ ALUs

Slide 2

Module

Eee creer

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module module name ( port _list ); module HalfAdder (A, B, Sum Carry);

port declarations; input A, B;

variable declaration;

description of behavior

endmodule

output Sum, Carry;

assign Sum =A“ B;

//* denotes XOR assign Carry =A & B;

// & denotes AND

endmodule

Description Styles

Eee creer

‘eleeeLe eee eee eee eee ee ee ee eee ee ee ee eee eee eee eee ee eee eee ee eee eee ee ee, eee ee _] Structural: Logic is described in terms of Verilog gate primitives L] Execution: Concurrent

L] Example:

not n1(sel_n, sel);

and a1(sel b,b, sel b);

and a2(sel_a, a, sel);

b

_ | > al

sel sel_n

d

— 1z} — sel_a

sel_b

Slide 4

Description Styles (cont)

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L] Dataflow: Specify output signals in terms of input signals

LJ Uses continuous assignment statement

— Format: assign net = expression;

All continuous assignment statements execute concurrently

Order of the statement does not impact the design

Example:

assign out = (sel & a)

| (~sel & b);

sl-FrÌ>*a,_ 2#

3 3}

>>

Slide 5

out

LÌ

LÌ

Eee creer

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Behavioral: Algorithmically specify the behavior of the

design

Example:

if (select == 0) begin

Out = b;

else if (select == 1) begin b

out = a:

end

out

Sel

Slide 6

Behavioral Modeling (cont.)

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Ll always statement : Sequential Block

LI Sequential Block: All statements within the block are

executed sequentially

L] When is it executed?

— Occurrence of an event in the sensitivity list

— Event: Change in the logical value

-Ì Statements with a Sequential Block: Procedural

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Ll Two Procedural Constructs

— initial Statement

— always Statement

L] initial Statement : Executes only once

Ll always Statement : Executes in a loop

Ll Example:

initial begin always @(A or B) begin

Sum = 0; Sum = A ^B;

Carry = 0; Carry =A&B;

Slide 8

Event Control

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_) Event Control

> Edge Triggered Event Control

>» Level Triggered Event Control

J Edge Triggered Event Control

@ (posedge CLK) //Positive Edge of CLK

Curr State = Next state;

@ negedge @ posedge 1x | 0 ->x 1->Z 0->Z 1->0 | 0 -› {

x->0 x => Í

z->0 | z -> †

_) Level Triggered Event Control

@ (A or B) //change in values of A or B

Out =A&B;

Slide Y

Peieheeieeineiee iteteen ee ieete ai ae ciaee iee i eeie a cei i iea e ee a

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LI Combination logic function can be expressed as:

C] logic_output(t) = f(logic_inputs(t))

logic_inputs(t) logic_outputs(t)

LI Combinational logic can be implemented with

concurrent and sequential statements

_} Concurrent statements are used in dataflow

and structural descriptions

LI Sequential statements are used in behavioral

descriptions Slide 10

Concurrent statements vs

Slide 11

MUX 2-1

module mux4tol [ray x, ¥, 3S):

f/f declare output output m-

_ Strutural/gate ((eechare snput

f/fassign wire variable

y wire sOn, sin;

f/fwrite code

ff and aO [{mO, s1,x)j;

and al [{ml, s,¥):

ff

h uO {ray ra, ra1d] z endmodule

b) Truth table Data flow module mux2tol (m, x, y, s);

input x, y, S;

tput m;

==> output m

wire m;

} 1 m assign m — (~S & X) | (s & y);

endmodule S]jde 12

MUX 2-1

Eee creer

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-|module mux4tol (m, x, y, 3);

// declare output

output reg 1w;

/fdeclare input

input x,Y,3;

Behavior

¬] : begin

| l'bl: m= yy;

-endmodule

¬

Slide 13

Eee creer

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LI Display tasks

— $display : Displays the entire list at the time when

statement is encountered

— $monitor : Whenever there is a change in any

argument, displays the entire list at end of time step

LJ Simulation Control Task

— $finish : makes the simulator to exit

— $stop : suspends the simulation

LÌ Time

Ee ee ee ee

E]module mux4tol th;

ff

reg I0, I1;

reg 50;

if ị

ff

mux4tol mux41(mux_out,I0, 11,50 ];

“ở

[Elbegin

#20 $display($time, "\t IO = %b\t Il = %b\n", I0, I1); Design

“ở

#20 $display([$tirme,"\t 5D = $b, \t mux_out = %b\n", 30, mux_out);

“ở

#20 $display($time,"\t SO = %b, \t mux_out = %b\n", SO, mux out); “ Puts

i!

rend

-endmodule

v

Slide 15

Simulation Results

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# vsin -t lps -L altera_ver -L lpm ver -L syate ver -L altera mf ve:

# v3in -L altera ver -L lpm ver -L sqate ver -L altera mf ver -L cy

# Loading work, mux4tol th

# Loading work muxdtol

# WARNING: No extended dataflow License exists

#

# add wave *

# view structure

# ,Waln pane, structure Interior cs body, struct

# view signals

# Wain pane, objects Interior cs body

acm mul

# run -all

20 Id=1 Il=0

‡

a 40 50 = 0, mux out = 1

‡

# 60 50 = 1, mux out = 0

#