Control and signal processing for lithography

It was demonstrated experimentally that real-time control of bake plate tem-perature to give nonuniform temperature distribution across warped wafer canreduce within-wafer and wafer-to-w

MING CHEN (B.Eng., SJTU)

A THESIS SUBMITTED

FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

NATIONAL UNIVERSITY OF SINGAPORE

2008

I would like to express my appreciation to all those who guided and supported meduring my postgraduate study and research at National University of Singapore.

At the very first, I wish to thank my supervisors, A/P Ho Weng Khuen and

Dr Arthur Tay for their dedicated and persistent guidance through my researchproject They have always done their best to offer timely instructions to thestudents including me And I have indeed benefited a lot from the tremendousdiscussions with them Their patience, wisdom and knowledge have made theresearch work interesting and rewarding for me Beyond researches, I have alsolearned much from them which have benefitted and will benefit my life

Next, I would like to thank Ms Lu Haijing and Dr Shan Xuechuan at pore Institute of Manufacturing They supplied me generous help on many aspects

Singa-of my research there from clean room facility training to guidance on lithographyprocesses I would also like to thank Dr Fu Jun, especially for her help duringthe hard time of machine setup and recipe development

Finally, I would like to thank my family for their long-term love, encouragementand support

ii

trol 71.2.2 CD Uniformity via Real-Time Resist Thickness Control 8

iii

1.2.3 Optimal Feed-Forward Control for Thermal Processing of

Wafers 10

1.3 Organization 11

2 CD and Real-Time Temperature Control for Warped Wafers 12 2.1 Introduction 13

2.2 Thermal Modeling of the Baking Process 15

2.3 Experiment 20

2.3.1 Setup 20

2.3.2 Runs 21

2.3.3 Real-Time Control 26

2.4 Application for One-Zone Bake Plate 29

2.5 Conclusion 32

3 CD Uniformity via Real-Time Photoresist Thickness Control 34 3.1 Introduction 35

3.2 Experimental Setup 37

3.2.1 Thickness Sensor 37

3.2.2 Thickness Controller 41

3.3 Experimental Results 42

3.3.1 Wafer-to-Wafer CD Control 42

3.3.2 Within-Wafer CD Control 45

3.4 Conclusion 50

4 Optimal Feed-Forward Control for Multizone Baking 52

4.1 Introduction 52

4.2 Multizone Bake Plate Thermal Model 54

4.3 Multizone Feed-forward Control 60

4.4 Experimental Results 64

4.5 Conclusion 70

5 Conclusion 71 5.1 Summary of Results 71

5.2 Future Works 73

This thesis investigates the application of advanced control and signal processingmethods to improve lithography performances.

Warped wafers affect the various baking processes in lithography Further,warpage can result in substantial spatial variation in critical dimension (CD) Areal-time temperature control method was proposed for post-exposure bake of re-sist It was demonstrated experimentally that real-time control of bake plate tem-perature to give nonuniform temperature distribution across warped wafer canreduce within-wafer and wafer-to-wafer CD variation

Resist thickness is nonuniform after spin coating (Decre and Vromans, 2000).Nonuniform CD is expected due to the standing wave effects A real time controlmethod was presented to improve thickness and CD uniformity Resist thicknesswas monitored with a spectrometer during post-apply bake, and controlled bymanipulating the heating power of bake plate in real-time Experimental resultsshowed that the thickness nonuniformity was reduced to less than 1nm and CDdeviation was reduced to about 2nm

vi

To improve repeatability for the wafer thermal processing, a multizone forward controller was proposed The objective is to reject the disturbance caused

feed-by placement of a cold wafer on the bake plate The optimal feed-forward controlsignals can be obtained by solving a linear programming problem Experimentalresults showed that the disturbance would be reduced to less than 0.1◦C

2.1 Thermophysical Properties 18

2.2 Thermal Capacitances and Resistances 18

2.3 Experimental Results 24

2.4 Experimental Results (Ta= 24◦C) 32

4.1 Comparison of the settling time, temperature deviation and inte-grated square error for multizone and single-zone feed-forward con-trol algorithm 69

viii

1.1 Steps of Lithography 31.2 Schematic diagram of the baking process 71.3 Post-exposure bake temperature and power Solid line: Flat Wafer;Dashed line: Warped wafer; Dash-dotted line: Warped wafer withsetpoint adjustment 9

2.1 Baking of Flat Wafer 1 Solid-line: center; Dashed-line: edge 162.2 Baking of Warped Wafer 4 Solid-line: center; Dashed-line: edge 172.3 Baking of Wafer 192.4 Critical dimension measurements Circle: center; Square: edge.Wafer 1–3: flat wafer with conventional baking; Wafer 4–6: warpedwafer with conventional baking; Wafer 7–9: flat wafer with opti-mized baking; Wafer 10–12: warped wafer with real-time on-lineadjustment of bake plate temperature setpoints 22

ix

2.5 Temperature measurement on a warped wafer with no photoresist nor pattern Solid-line: center; Dashed-line: edge The first plot shows the wafer temperature measured with RTDs The second plot shows bake plate temperature where setpoint adjustments are

made in the midway The third plot shows the control signal 23

2.6 Bake plate setpoint adjusted to give uniform CD for Flat Wafer 7 Solid-line: center; Dashed-line: edge 25

2.7 Center-zone average air-gap versus bake plate maximum tempera-ture drops 27

2.8 Edge-zone average air-gap versus bake plate maximum temperature drops 28

2.9 Bake plate setpoints adjusted in real-time once warpage was de-tected to give uniform CD for Warped Wafer 10 Solid-line: center; Dashed-line: edge 30

2.10 Estimated profile of warped wafer 10 31

2.11 Estimated profile of warped wafer 3 31

2.12 Nominal air-gap, la, versus maximum temperature drop 33

3.1 Experimental Setup 38

3.2 Plant photo for the post-apply bake process 39

3.3 Block diagram of the control system 41

3.4 Post-apply bake (a) Photoresist thickness (b) Bake plate ature (c) Control signal, u, in Voltage (V) Solid-line: Wafer 1;dashed-line: Wafer 5; dotted-line: desired photoresist thickness 433.5 Wafer-to-Wafer photoresist thickness and CD 443.6 Within-Wafer photoresist thickness and CD Circle: near center ofwafer; square: near edge of wafer 463.7 Within-Wafer photoresist thickness and CD Circle: near center ofwafer; square: near edge of wafer 473.8 Post-apply bake for Wafer 10 within-wafer CD control (a) Photore-sist thickness; (b) Bake plate temperature; (c) Control signal, u, inVoltage (V) Solid-line: near center of wafer; dashed-line: near edge

temper-of wafer; dotted-line: desired photoresist thickness 483.9 Schematic diagram of a two-zone bake plate 493.10 Post-apply bake for Wafer 14 with no photoresist thickness control.(a) Photoresist thickness (b) Bake plate temperature (c) Controlsignal, u, in Voltage (V) Solid-line: near center of wafer; dashed-line: near edge of wafer 51

4.1 Comparison of bake plate temperature disturbance caused by theplacement of a cold wafer on the multizone bake plate Solid-line: multizone feed-forward algorithm; dashed-line: single-zonefeed-forward algorithm; dotted-line: proportional-integral feedbackcontrol only 0∼250s one group of experiments; 250∼500s, repetitiveexperiments 554.2 Schematic Diagram of the multizone bake plate 564.3 Photograph of the multizone bake plate 66

Semiconductor manufacturing has greatly affected the world due to the wide cation of semiconductor devices The industry development can basically be sym-bolized by the so called integrated circuit (IC) scaling The number of transistors

appli-on a single IC doubles every two years according to Moore’s law (Hamiltappli-on, 2003).Critical dimension (CD) of patterns is currently below 100nm A more stringentdemand on the CD variation is imposed By the year 2010, a CD control require-ment of 4.7nm is expected for 45nm technology node (International TechnologyRoadmap for Semiconductors, SIA, 2005) The industry has moved through sev-eral lithography generations to achieve smaller feature sizes However, technology

1

transition is expensive and time consuming To reduce cost, a better way is to tend the life cycle of current lithography generation The challenge is to maintain

ex-CD variations within the desired specifications while pushing feature size to itsabsolute minimum achievable value One solution is the introduction of advancedequipment and process control (Moynes, 2006; Miyagi et al., 2006) This thesiswill investigate the application of advanced control and signal processing to meetsome stringent requirements for CD control in lithography

CD control is required for obtaining adequate transistor, interconnect and sequently overall circuit performance (Edgar et al., 2000) As shown in Figure 1.1,

con-a typiccon-al lithogrcon-aphy includes resist cocon-ating, post-con-apply bcon-ake (or softbcon-ake), sure, post-exposure bake (PEB), development, and an optional post developmentbake The sensitivity of the process to small variations in photoresist coating, ex-posure dose and the bake plate temperature can result in the final CD going out

is the thermal processing in lithography, such as PEB (Li, 2001; Cain et al., 2005),and post-apply bake (Raptis, 2001) Each of the bake steps serves different roles intransferring the desired patterns into the substrate (Suzuki and Smith, 2007) The

Fig 1.1 Steps of Lithography.

principal objective of this thesis is to improve CD uniformity by applying real-timecontrol approaches in the various thermal processes

Optical lithography has been the mainstream technology for volume ing since the earliest days of the microelectronics industry In optical lithographytechniques such as chemical amplification are necessary in order to make photore-sists sensitive enough to achieve wafer throughput goals for manufacturing Inmost chemically amplified resists (CARs), the chemical amplification process is

manufactur-driven by the PEB step Therefore, CD is highly sensitive to PEB temperature.For commercially available CARs, a representative PEB latitude for CD variation

is about 5∼20 nm/◦C (Seegar, 1997) Temperature sensitivity of 193nm CARsphotoresist is in the order of 7∼10nm/◦C (Friedberg et al., 2004) Nordquist et al.(2000) and Berger et al (2004a) reported a representative sensitivity of 8 nm/◦Cfor commercially available deep ultraviolet (DUV) resists

Due to the high sensitivity of CD to PEB temperature, CD can be controlled

by manipulating the PEB process Achieving CD uniformity is one of the majorconcerns Zhang et al (2004) successfully compensated systematic CD variationacross wafers by adjusting the PEB baking profiles on different parts of wafersthrough a multizone bake plate Lee et al (2004b) reduced CD variation from4.8nm 3σ to 3.9nm 3σ using a 25-zone bake plate A similar study (Berger etal., 2004a) reduced the CD variation from 8.9nm to 6.7nm These methods areusually implemented through a run-to-run mode and have proved to be effective

in eliminating systematic errors In run-to-run control method, the informationfrom previous wafer or patch is used for control of the current wafer or batch Inthe presence of random variation, however, the run-to-run methods become lesseffective (Xu et al., 2002)

Warpage is one challenge for PEB processing of wafers (Bhattacharya et al.,2000; Banerji et al., 2005) One factor that contributed to warpage was stress (Fukui

et al., 1997) El-Awady (2000) studied the influences of warpage on baking perature, and gave quantitative results as 1◦C change for a warpage level of 50 µm

tem-through simulation studies Such variation will cause substantial CD mity.

nonunifor-Since warpage is usually different wafer-to-wafer, measurement of warpage isessential for CD nonuniformity compensation The warpage can be measured byvarious methods (Yang et al., 2006) The shadow and projection Moire techniquesare widely used warpage measurement methods (Ding et al., 2002; Powell and Ume,2007) Warpage can also be measured through capacitive probes (Fauque, 2001)and through the pneumatic-electromechanical effects (Fauque and Linder, 1998).All these methods have the advantage that they can give the precise profile of thewarped wafer However, one disadvantage is that they are off-line and need extraprocessing time to obtain the warpage information Further, the delay betweenthe exposure and the PEB steps needs to be reduced due to post-exposure delayeffect of chemically amplified resists (Lee et al., 2001) This would eliminate anytime consuming measurement between these two steps

One objective of this thesis is to adopt an in-situ warpage detection methodfor proper PEB processing of warped wafers to obtain CD uniformity

Shipley UV3, a theoretical model of the thickness variation during post-applybake was developed and matched well with experimental data (Hsu et al., 2001).

It was found that the rate of solvent removal was controlled by its diffusion, whichwas affected by post-apply bake temperature in an Arrhenius mode Thus thepost-apply bake temperature and time will affect the final resist thickness

Lithography properties vary as a sinusoidal function of resist thickness due tothe the standing wave effects, or swing curve effects The swing curve effects for analternating phase shift mask were reported by Singh et al (2006) CD swing curveswere represented in two dimension to optimize lithography performance (Schiltzand Schiavone, 2000) Thus, optimizing the post-apply bake process is crucial toobtain uniform lithography latitude, such as CD Lithographic performance wereenhanced for two negative chemically amplified resists by adjusting post-applybake time (Raptis, 2001) Lee et al (2002) demonstrated that an within-waferthickness nonuniformity of less than 1nm can be obtained by manipulating theprocessing temperature during post-apply bake for an i-line resist Shipley 3612.One goal of this thesis is to obtain resist thickness and CD uniformity by real-timecontrol of post-apply bake processing

In this thesis, the application of advanced metrology, control and signal processingalgorithms to meet some stringent requirements in lithography is investigated.This thesis will address three areas: 1) CD uniformity improvement by real-time

temperature control for warped wafers during PEB, 2) CD uniformity improvementvia real-time resist thickness control in the post-apply bake and 3) optimal feed-forward control for thermal processing of wafers to improve repeatability.

Temper-ature Control

During thermal processing, a wafer at room temperature is dropped onto the bakeplate maintained at a set point temperature with a feedback controller The prox-imity pins produce an air-gap between the wafer and the bake plate to avoidcontamination For flat wafers, this air-gap equals to the pin length as shown

in Figure 1.2(a) For warped wafers, however, the air-gap will be bigger ward warpage) or smaller (downward warpage) as shown in Figure 1.2(b) Wafertemperature will be different also The bigger the air-gap, the lower the wafertemperature

(up-Fig 1.2 Schematic diagram of the baking process

A real-time temperature control method will be proposed to improve CD formity for warped wafers It is noted that bake plate temperature will drop to

uni-a muni-aximum vuni-alue before recovering to the set point It is uni-also noted thuni-at fluni-atwafer and warped wafer give different maximum temperature drop as shown inFigure 1.3, solid line and dashed line respectively Thus wafer warpage can bedetected from the maximum temperature drop Once the warpage is detected, thebake plate temperature can be adjusted in real-time accordingly to reduce wafertemperature variations, as shown by the dash-dotted line in Figure 1.3 CD varia-tions caused by warpage can be compensated before it is formed in the resist Thewafer-to-wafer CD variation compensation will be demonstrated experimentally.There are also temperature and CD nonuniformity across the wafer due tothe different air-gap at different location To realize within-wafer CD uniformity,

a multizone bake plate is used, with the capability to bake different zones todifferent temperature independently When the maximum temperature drops ofdifferent bake plate zones are recorded, the warpage can be detected Bake platetemperature for different zones can be adjusted independently to compensate forthe wafer temperature and CD variations The method will be demonstratedexperimentally

Con-trol

Resist thickness is another major source for CD nonuniformity Photoresist istypically spin coated on the wafer to form a thin film Resist thickness is nonuni-form after spin-coating Nonuniform CDs are expected and they vary as a swing

curve function of photoresist thickness due to the standing wave effects Bothwafer-to-wafer and within-wafer variations exist in practice.

In this thesis, a real-time resist thickness control method will be proposed

to improve resist thickness and CD uniformity During post-apply bake, resistthickness reduces gradually due to solvent removal and different temperature givesdifferent thickness reduction For conventional post-apply bake, the bake platetemperature is maintained at a constant value The resist thickness nonuniformityremains at the end of the bake In the method, a spectrometer is used to monitorthe resist thickness above the wafer during the post-apply bake The thickness can

be controlled to follow a pre-determined trajectory by adjusting the heating power

of the bake plate in real-time It is to be demonstrated experimentally that bothwafer-to-wafer and within-wafer resist thickness nonuniformity of less than 1nmand CD nonuniformity of around 2nm are achieved

Process-ing of Wafers

During thermal processing of wafers, it is extremely important to control the perature within a tight tolerance during the whole bake cycle When a wafer atambient temperature is placed onto the hot bake plate, the bake plate endures asudden drop in temperature due to the heat transferred from the bake plate tothe cold wafer Bake plate controller will adjust the heating power to regulate the

tem-temperature to the setpoint In automated wafer fab, the next wafer arrives diately after the baking of the previous wafer If the processing time is short thanthe recovery time of the bake plate, the bake plate temperature trajectory will bedifferent from wafer to wafer Thus it is important to reject the load disturbanceeffectively to ensure process repeatability.

imme-In this thesis, a multizone optimal feed-forward control strategy is proposed

to eliminate disturbance induced by placement of the cold substrate The bance minimization problem is transformed into a linear programming problemwith constrains Thus optimal feed-forward control signals could be obtained bysolving the linear programming problem Using the proposed optimal controller,

distur-a disturbdistur-ance of less thdistur-an 0.1◦C is obtained experimentally

This thesis consists of 5 chapters and is organized as follows Chapter 2 describes

a real-time temperature control method for warped wafers during PEB to improve

CD uniformity The implementation will be discussed in detail for a double-zonebake plate and briefly for a one-zone bake plate Chapter 3 presents a real-timethickness control method to improve wafer-to-wafer and within-wafer thickness and

CD uniformity An optimal feed-forward control for multizone baking in phy is proposed and implemented in Chapter 4 Chapter 5 summarizes the researchworks and gives recommendations for future works

lithogra-CD and Real-Time Temperature

Control for Warped Wafers

This Chapter discusses the experimental results on Critical Dimension (CD) trol via real-time temperature control for warped wafers As opposed to run-to-runcontrol where information from the previous wafer or batch is used for control ofthe current wafer or batch, the approach here is real-time and make use of currentinformation for control of the current wafer CD In this Chapter it is demonstratedthat real-time control of the post-exposure bake temperature to give nonuniformtemperature distribution across the warped wafer can reduce CD nonuniformityacross the wafer

con-12

2.1 Introduction

The key output in photolithography is the linewidth of the photoresist pattern or

CD and the CD is significantly impacted by several variables that must also bemonitored to ensure quality (May and Spanos, 2006; Postnikov et al., 2003).Thermal processing of semiconductor substrate is common and critical in thephotolithography sequence Temperature uniformity control is an important is-sue with stringent specifications and has a significant impact on the CD (Quirkand Serda, 2001; Narasimhan and Ramanan, 2004; Zhang et al., 2005) Themost temperature sensitive step in the photolithography sequence is the post-exposure bake step As the photolithography industry moves to bigger substrateand smaller CD, the stringent requirements for post-exposure bake processing stillpersist (Kagerer et al., 2006) For commercially available deep ultraviolet resist, arepresentative post-exposure bake latitude for CD variation is 8 nm/◦C (Nordquist

et al., 2000; Berger et al., 2004a) A number of recent investigations also showed theimportance of proper bake plate operation on CD control (Zhang et al., 2005; Steele

et al., 2002; Hisai et al., 2002)

Thermal processing of semiconductor wafers is commonly performed by ment of the substrate on a heated bake plate for a given period of time The heatedbake plate is usually held at a constant temperature by a feedback controller thatadjusts the heater power in response to a temperature sensor embedded in thebake plate near the surface The wafers are usually placed on proximity pins ofthe order of 100 µm to create an air-gap to minimize contamination

place-When a flat wafer at room temperature was placed on the bake plate, thetemperature of the bake plate dropped at first but recovered gradually because ofclosed-loop control as shown in Figure 2.1 (a) One challenge for thermal processing

of wafers in photolithography is the warpage (Bhattacharya et al., 2000) Figure 2.2(a) shows the bake plate temperature when a wafer warped 140µm center-to-edgewas dropped on the bake plate By comparing Figures 2.1 (a) and 2.2(a), itcan be seen that a flat and warped wafer gave rise to different magnitudes ofbake plate temperature drops due to different air-gap sizes and hence differentthermal resistances between the substrates and bake plate Figure 2.3 shows aflat and warped wafer on the bake plate Compared with the flat wafer, becausethe air-gaps between the warped wafer and bake plate were bigger (smaller), themaximum temperature drops at the bake plate were smaller (bigger) Furthermore,the warped wafer is expected to be heated to a lower (higher) temperature thanthe flat wafer Finally, because of nonuniform processing condition, CD across thewarped wafer was also not expected to be uniform

It was demonstrated in Ho et al (2004) and Tay et al (2007a) that the air-gapsize can be estimated from the maximum bake plate temperature drop throughtheir inverse relationship It was further demonstrated in Tay et al (2007a) thatusing the heat transfer model of the baking system and the estimated air-gap,the bake plate temperature can be calculated to give uniform temperatures acrossthe warped wafer In this Chapter the results are extended by demonstratingthat real-time control of the post-exposure bake temperature to give nonuniformtemperature distribution across the warped wafer can reduce CD nonuniformity

It was demonstrated that uniform wafer temperature would not assure uniform

CD Instead, nonuniform wafer temperature profile to achieve uniform CD can bederived from the CD and wafer temperature sensitivity The proposed solution is toadjust the bake plate temperature setpoints on-line and in real-time once warpage

is detected to give desired nonuniform wafer temperature profile Warpage candiffer from wafer-to-wafer and hence not expected to be repeatable If warpagewas repeatable then bake plate setpoints could have been fixed A thermal model

is required to relate warpage to the maximum bake plate temperature drops, and

to relate the wafer temperature profile and the bake plate temperature profile Thethermal model will be derived in next section

The distributed thermal processing system used in this work consisted of twoheating zones, center and edge as shown in Figure 2.3 la1 and la2 represent theaverage air-gap of the center zone and edge zone respectively Embedded withineach of the heating zones were resistive heating elements and temperature sensors.The zones were separated by a small air-gap of approximately 1 mm for thermalinsulation

Spatial distributions of temperature and other quantities in a silicon wafer aremost naturally expressed in a cylindrical coordinate system It is assumed thatthe substrate used for baking is a silicon wafer and the bake plate is cylindrical

in shape with the same diameter as the wafer Energy balances on the wafer and

Table 2.1 Thermophysical Properties

edge zone radius, r2 50 mmAir Thermal conductivity, ka 0.03 W/mK

Convective heat transfer coefficient, h 8 W/m2K

Table 2.2 Thermal Capacitances and Resistances

Thermal Capacitance Value

center zone

Fig 2.3 Baking of Wafer

A control software system was developed using the National Instruments View programming environment (http://www.ni.com, 2007) Two proportional-integral controllers of the following form were used to control the two zones of thebake plate

TI1 = 150 and Kc2 = 16.79, TI2 = 500 respectively

The relationship between the steady-state wafer temperatures Tw1(∞), Tw2(∞)and bake plate setpoints, Tp1(∞), Tp2(∞) for the two-zone system can be obtained

from Equations (2.1) and (2.2) as

Tp1(∞) = Ra1

1

of 3 points Except for the real-time on-line adjustment of the post-exposurebake temperature, all other inputs to the photolithography processes such as spinspeed, baking time, exposure dose, develop time etc were kept constant Noanti-reflection coating was used The post-exposure bake time was fixed at 90s.The experimental setup for the post-exposure bake of a warped wafer is shown

in Figure 2.3 A fixed warpage was ensured during the baking experiment by

mechanically pressing the edges of the wafer against the proximity pins of 70µm.The center-to-edge warpage was given by the difference between the height ofproximity pin and thermal tape thickness.

Twelve Experiment (Wafer) Runs were performed On each wafer CD were tored at 2 points, 1.5 inches apart, one near the center, the other near the edge ofthe wafer At each point, three samples of linewidths were measured by scanningelectron microscope to give the average CD in Figure 2.4 The results for Runs 1,

moni-4, 7, 10 are tabulated in Table 2.3 for further discussion The other runs were peat experiments Wafers 1–3 and 7–9 were flat while 4–6 and 10–12 were warped140µm center-to-edge

re-Because photoresist was coated on the patterned wafer, it was not convenient toattach temperature sensors on the wafer to measure wafer temperature To do so,another set of experiments with the same wafer warpage and bake plate setpointswere conducted There were no pattern nor photoresist on these wafers and theirsole purpose was for us to obtain the wafer temperatures Resistance TemperatureDetectors (RTD) were attached to the wafers (El-Awady et al., 2004; Tay et al.,2004a) for temperature measurements Thermal grease was applied to the RTDsensors for better heat transfer The measured wafer temperatures are included

in the last row of Table 2.3 and in the column that corresponded to the warpageand bake plate setpoints Figure 2.5 shows the measured wafer temperature for a

1 2 3 4 5 6 7 8 9 10 11 12 350

warped wafer The wafer was baked for 90s starting from t = 10s

The bake plate temperature curve for Flat Wafer 1 is shown in Figure 2.1.Notice in Table 2.3 that for Flat Wafer 1 even though the wafer temperature atcenter (128.1◦C) and edge (128.0◦C) were approximately equal, CD nonuniformitywas 23nm This can be expected as properties at center and edge may not be thesame e.g the thickness of the coat of photoresist across the wafer is known to benonuniform (Lee et al., 2002; Decre and Vromans, 2000) Nonuniform photoresistthickness can cause nonuniform CD through a swing curve effect (Singh et al.,2006; Yu et al., 2005a; Yu et al., 2005b) In Tay et al (2007a) the bake plate

Table 2.3 Experimental Results

Experiment (Wafer) No 1 4 7 10

Warpage Flat Warp Flat WarpBake plate Setpoint (◦C) Center 130 130 130.3 130.3 to 133.6

Tp(∞) + T∗

a Edge 130 130 128.5 128.5 to 129.6Bake plate Maximum Center 2.13 1.54 2.12 1.54Temperature Drop (◦C) Edge 1.98 1.73 1.98 1.70

Center 399 362 399 399

CD (nm) Edge 422 408 400 400

Nonuniformity† 23 46 1 1Wafer Temperature (◦C) Center 128.1 125.4 128.2 128.2

Tw(∞) + T∗

a Edge 128.0 126.9 126.6 126.6

∗Ambient temperature Ta = 24.5◦C

†Difference between center and edge CD

temperatures were controlled to give uniform temperatures on the wafer It isdemonstrated here that this is not good enough to give uniform CD Nonuniformtemperature distribution across the wafer may be required to obtain uniform CD

at center and edge

The bake plate temperature curve for Warped Wafer 4 is shown in Figure 2.2.Table 2.3 shows that the wafer center temperature (125.4◦C) was lower than edge(126.9◦C) and the CD nonuniformity doubled to 46 nm

The manufacturing process should be fairly repeatable In practice a certaindegree of repeatability of the CD profile is expected and hence the two-zone bakeplate should start baking at different temperatures for different zones The de-sired CD profile is 400nm for the center and edge respectively The desired wafertemperature profile to achieve uniform CD can be obtained from wafer 1-3 results

and the CD temperature sensitivity Desired bake plate temperature profile forflat wafer can be obtained from Equations (2.7) and (2.8) Once a new set of bakeplate setpoints (130.3◦C and 128.5◦C) was implemented as shown in Figure 2.6,the CD non-uniformity on the Flat Wafer 7 was reduced to 1 nm as shown inTable 2.3 Notice that for CD uniformity, wafer temperature at center (128.2◦C)was higher than edge (126.6◦C).

Solid-2.3.3 Real-Time Control

For the given bake plate, all parameters in Table 2.2 are known except for Ra1

and Ra2 which depended on wafer warpage or average air-gaps at center-zone(la1) and edge-zone (la2) The center and edge zones were pre-programmed tostart baking at setpoints of 130.3◦C and 128.5◦C respectively to give desired wafertemperatures of Tw1(∞) + Ta = 128.2◦C and Tw2(∞) + Ta = 126.6◦C and CDuniformity for flat wafers Equations (2.1) to (2.6) were solved to determine themaximum temperature drops in Tp1 and Tp2 for 20µm ≤ la1 ≤ 300µm and 20µm

≤ la2 ≤ 300µm and the results are plotted in Figures 2.7 and 2.8 for la1 and la2

respectively They can also be tabulated to facilitate on-line search for la1 and la2

from the maximum temperature drops

To obtain CD uniformity for a warped wafer, setpoint adjustments were made

in real-time once warpage was detected Warpage differed from wafer to wafer andhence not expected to be repeatable If warpage was repeatable then fixed butdifferent bake plate setpoints could have been used for center and edge

For processing of Warp Wafer 10, the maximum temperature drop of 1.54◦Cand 1.70◦C center and edge respectively were first measured A search throughFigures 2.7 and 2.8 gave la1 = 184µm and la2 = 110µm Substitute into Ra1,

Ra2 and with the desired wafer temperatures of Tw1(∞) + Ta = 128.2◦C and

Tw2(∞)+Ta= 126.6◦C, Equations (2.7) to (2.8) gave the new setpoints of Tp1(∞)+

Ta = 133.6◦C and Tp2(∞) + Ta = 129.6◦C Notice in Figure 2.9 the bake platesetpoints were changed from 130◦C to 133.6◦C and 128.5◦C to 129.6◦C at t = 24s,

center zone maximum drop (Deg C)

edge zone maximum drop (Deg C)

Fig 2.7 Center-zone average air-gap versus bake plate maximum temperaturedrops

center zone maximum drop (Deg C)

edge zone maximum drop (Deg C)

Fig 2.8 Edge-zone average air-gap versus bake plate maximum temperature drops