Advanced gate stack for CMOS nanotechnology

Abstract Aggressive complementary metal-oxide-semiconductor CMOS scaling requires metal gate/high-k dielectric gate stacks for enhanced device performance in sub-45 nm technology nodes.

METAL GATE TECHNOLOGY FOR ADVANCED CMOS

GATE STACKS

LIM EU-JIN ANDY

NATIONAL UNIVERSITY OF SINGAPORE

2008

METAL GATE TECHNOLOGY FOR ADVANCED CMOS

GATE STACKS

LIM EU-JIN ANDY

(B ENG.) NATIONAL UNIVERSITY OF SINGAPORE

A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

NATIONAL UNIVERSITY OF SINGAPORE

AUG 2008

Acknowledgements

First and foremost, I would like to express my utmost gratitude and appreciation

to my research advisor, Dr Yeo Yee-Chia who has guided me throughout my Ph.D candidature I am thankful to Dr Yeo for sharing his knowledge, and giving me his support and patience during these four years He has always been there to give insights into my research work and I have greatly benefited from his guidance I would also like

to express my sincere appreciation to my co-advisor, Prof Kwong Dim-Lee Prof Kwong has always been encouraging in my research work, and has provided valuable advice throughout my course I am also grateful to Prof Ganesh Samudra for sitting on

my thesis advisory committee and providing valuable feedback and suggestions, especially during our group meetings

I would like to express appreciation to Agency for Science, Technology and Research (A*STAR) for funding my graduate studies through a graduate scholarship award I would also like to acknowledge the efforts of the technical staff in Silicon Nano Device Laboratory (SNDL) specifically Mr Yong Yu Fu, Mr O Yan Wai Linn, Patrick Tang, and Lau Boon Teck in providing efficient technical and administrative support for

my research work Appreciation also goes out to Institute of Microelectronics (IME) and Institure of Materials Research, and Engineering (IMRE) for the use of their equipment for materials characterization work

I am grateful for the friends I have met in SNDL in particular, my buddy Rinus

It has been great fun working with you and I really appreciate your help, especially during the initial phase of my course when I was working on silicide gates I would also like to thank Ren Chi, Xin Peng, Wan Sik, King Jien, Kah Wee, Kian Ming, Jason, Shen

Chen, Whang Sung Jin, Wei-Feng, Hoong Shing, Lina, Alvin, Fangyue, Shao Ming, Hock Chun, and many others for their useful discussions, assistance and friendships throughout my candidature

My deepest gratitude goes out to my parents who have given me their support and encouragement during my studies Most importantly, a special “Thank you!” goes out to

my dearest Fei who has been always there unconditionally with her love and support throughout these years

Table of Contents

Acknowledgements i

Table of Contents iii

Abstract vi

List of Tables viii

List of Figures ix

List of Symbols xix

Chapter 1 Introduction 1.1 Overview for CMOS Scaling 1

1.2 Why Metal Gate Electrodes? 3

1.2.1 Current Status of Metal Gate Technology 5

1.2.2 Work Function Extraction Method 8

1.3 Objective of Research 10

1.4 Thesis Organization 11

1.5 References 13

Chapter 2 Nickel Alloying for Fully-Silicided or Fully-Germanided Metal Gate Work Function Modulation 2.1 Introduction 19

2.2 Experiment 21

2.3 Results and Discussion 22

2.3.1 Nickel-Terbium Alloy for Fully-Silicided Gate 22

2.3.2 Nickel-Aluminum Alloy for Fully-Silicided and Fully-Germanided Gate 31

2.4 Summary 40

2.5 References 42

Chapter 3 Novel Rare-earth Based Interlayers for Wide NMOS

Work Function Tunability in Nickel Fully-Silicided Gate

3.1 Introduction 46

3.2 Experiment 47

3.3 Results and Discussion 49

3.3.1 Electrical and Material Characterization of Rare-earth based Interlayer 49

3.3.2 Proposed Interfacial Dipole Model 60

3.3.3 Integration in HfO2/SiO2 Dielectric Stack 64

3.4 Summary 68

3.5 References 69

Chapter 4 Manipulating Interface Dipoles of Opposing Polarity for Work Function Engineering 4.1 Introduction 74

4.2 Experiment 75

4.3 Results and Discussion 78

4.3.1 Opposing Interface Dipoles in TaN/SiO2 Gate Stack 78

4.3.2 Opposing Interface Dipoles in TaN/High-k Gate Stack 87

4.3.3 Utilization of Aluminum-Incorporated Metal Gates for Reversal of n-type Dipole 91

4.4 Summary 100

4.5 References 101

Chapter 5 Interdiffusion of Thin Metallic Layers for Metal Gate Work Function Control

5.1 Introduction 105

5.2 Experiment 106

5.3 Results and Discussion 109

5.3.1 Gate Work Function Dependence on Metal Thickness 109

5.3.2 Gate Work Function Dependence on Annealing Temperature 113

5.3.3 Work Function Modulation on HfO2 and HfLaOx Dielectric 116

5.4 Summary 119

5.5 References 120

Chapter 6 Conclusions and Future Work 6.1 Conclusion 123

6.1.1 Nickel Alloying for Fully-Silicided or Fully-Germanided Metal Gate Work Function Modulation 124

6.1.2 Novel Rare-earth Based Interlayers for Wide NMOS Work Function Tunability in Nickel Fully-Silicided Gate 124

6.1.3 Manipulating Interface Dipoles of Opposing Polarity for Work Function Engineering 125

6.1.4 Interdiffusion of Thin Metallic Layers for Metal Gate Work Function Control 126

6.2 Suggestions for Future Work 127

6.3 References 129

Appendix A Publication List 130

Abstract

Aggressive complementary metal-oxide-semiconductor (CMOS) scaling requires metal gate/high-k dielectric gate stacks for enhanced device performance in sub-45 nm technology nodes The elimination of polysilicon gate depletion effect and reduction in gate leakage are major advantages of metal gate/high-k gate stacks over conventional polysilicon/SiO(N) gate stacks However, achieving the desired effective metal gate work function (Φm) to meet threshold voltage requirements in future CMOS devices is one of the main hurdles for implementation

Full silicidation of a polysilicon gate electrode with nickel (Ni) is an attractive metal gate option due to its simplicity and compatibility with current CMOS process In this work, novel methods were explored to modulate the mid-gap Φm (~4.65 eV) of Ni fully-silicided (Ni-FUSI) gate Ni-alloying with either terbium (Tb), or aluminum (Al) achieved a FUSI gate Φm lowering of about ~0.2 – 0.3 eV Ni-Al alloy further reduced the Φm of a Ni fully-germanided gate by ~0.6 eV The change in gate crystallinity and the segregation of elemental Al were the mechanisms responsible for the gate Φm shifts using Ni-Tb and Ni-Al alloy, respectively To widen the Ni-FUSI gate Φm tunability range, an alternative technique using ultra-thin rare-earth (RE) silicate interlayers was employed Conduction band-edge gate Φm of ~3.8 – 4.1 eV were obtained through the formation of the interlayers on SiO2 A proposed interface rare-earth–oxygen (RE-O) dipole model exhibited excellent correlation between the modulated Φm values and the calculated RE-O dipole magnitudes Additional factors like interlayer thickness, nickel

silicide phase and RE position (for interlayer formation) in a high-k stack were found to influence the effective gate Φm significantly

Two distinct metal gate Φm tuning methods were also investigated for dual gate integration Firstly, the manipulation of n- and p-type interface dipoles for Φm

metal-engineering within the same metal gate stack was explored Continuous Φm tunability was attained through the modulation of dipole magnitude and polarity by combining Tb (n-type) and Al (p-type) –induced interface dipoles in a single metal gate stack Dipole formation hinges critically on the reaction of Tb or Al with SiO2 (or underlying SiO2 for high-k dielectric stacks) We also show, for the first time, that the net interface dipole polarity in a metal gate stack can be reversed through the incorporation of dipoles with opposite polarity and control of the subsequent annealing conditions Secondly, the interdiffusion of elemental metals or metal alloys not more than 10 nm thick was examined for gate Φm control Φm modulation was successfully achieved using these thin layers, which allowed better spatial uniformity and ease of process integration for dual metal gate technology Metal thickness ratios before interdiffusion and annealing temperatures were also crucial in determining the final Φm value The exploration of novel metal gate materials and Φm tuning techniques provides new avenues for future metal gate/high-k gate stack engineering in scaled CMOS technology nodes

List of Tables

Table 1.1 A summary of different metal gate integration approaches for

CMOS devices 8

Table 3.1 The RE metals used in this work are listed below with their

respective sputtering power and sputtering times A working pressure of 5 mTorr was used during sputtering 49

Table 3.2 Net electronegativity difference (Δχ) of RE and O atoms, the

sum their ionic radii (dRE-O), and Δχ × dRE-O are tabulated [3.22]

The ionic radius of trivalent RE ion (3+) with coordination number of 8 is used The relative magnitude of RE-O dipole

moment μ can be estimated by Δχ × dRE-O χ and ionic radius of

O is 3.44 and 1.4, respectively 63

Table 4.1 Thicknesses of Tb, Al, and AlTb films (TTb, TAl, and TAlTb)

which were deposited by sputtering or co-sputtering at a working pressure of 5 mTorr A sputtering power of 60 and 80 W was used for Tb and Al, respectively A surface profiler was used to estimate the IL metal deposition rates for thickness calculations 77

Table 5.1 Metal layers, thicknesses and thickness ratios used in this work

The Metal 2 layer is formed on the Metal 1 layer The most Metal 1 layer was either a high work function metal layer

bottom-(shaded rows), or a low work function metal alloy layer (unshaded rows) 107

List of Figures

Fig 1.1 (a) The energy band diagram of an NMOSFET showing the

poly-Si gate depletion layer during inversion bias (b) The capacitance-voltage plot depicts how the poly-Si gate depletion effect decreases the gate capacitance in the inversion regime 4

Fig 1.2 Metal gate Φm requirements for both planar bulk transistors and

transistors with advanced structures are shown 5

Fig 1.3 An illustration of (a) metal gate/SiO2 and (b) metal gate/high-k

stacks formed with different SiO2 thicknesses through a SiO2

etchback scheme on the same wafer for metal gate Φm

extraction 9

Fig 2.1 (a) High-frequency C-V curves of NiSi- and Ni(Tb)Si-gated

MOS capacitors silicided from Ni1−xTbx alloy (x = 0, 0.11, 0.2,

and 0.29) (b) VFB vs T ox plot used to eliminate the effect of fixed charges for Φm extraction 23

Fig 2.2 (a) TEM image of Ni(Tb)Si (from Ni0.71Tb0.29 alloy) gate stack

where a dual layer gate structure was observed (b) High resolution TEM image of the silicide/SiO2 interface showing no visible degradation 24

Fig 2.3 (a) The frontside SIMS profile of Ni(Tb)Si/SiO2/Si-sub gate

stack silicided using Ni0.71Tb0.29 alloy Dual layer silicide gate structure corresponds to that seen in TEM (b) The backside SIMS profile of the same gate stack confirmed the absence of

Tb at the gate/dielectric interface 25

Fig 2.4 (a) The XRD spectra of NiSi and Ni(Tb)Si gate stack silicided

from Ni1−xTbx alloy (x = 0, 0.11, and 0.2) at 400°C RTA showed

a decrease in film crystallinity with increasing Tb ratio (b) XRD spectra of Ni(Tb)Si (from Ni0.8Tb0.2 alloy) gate stack showed improved crystallinity for silicidation at 500°C RTA than 400°C RTA 28

Fig 2.5 Raman spectra comparing NiSi and Ni(Tb)Si (from Ni0.8Tb0.2

alloy) gate stack A broader peak width was observed for Ni(Tb)Si, suggesting that the underlying NiSi film was more disordered than the pure NiSi film 29

Fig 2.6 Leakage current of NiSi- and Ni(Tb)Si-gated MOS capacitors

are similar (T ox ~5.8 nm), indicating no degradation of electrical characteristics 30

Fig 2.7 (a) C–V curves of Ni(Al)Si gate showing a more negative VFB

shift for a 550ºC silicidation Inset shows the extracted Φm from

the VFB vs T ox plot (b) SIMS profile indicates more Al present

at the Ni(Al)Si/SiO2 interface after a 550ºC silicidation An rich layer was also observed at the top of the gate 32

Al-Fig 2.8 SIMS depth profile of Ni(Al)Ge gate germanided at 550ºC with

Ni0.78Al0.22 alloy The bilayered Ni(Al)Ge gate profile can be observed and the presence of Al is clearly detected at the gate/dielectric interface 33

Fig 2.9 C–V curves for (a) Ni(Al)Si and (b) Ni(Al)Ge gates formed

using different Ni1-xAlx alloys (x = 0, 0.07, 0.22, or 0.42) A saturation in Ni(Al)Si VFB was observed with varying Al ratio

Ni(Al)Ge gate was also able to achieve approximately the same

VFB through Al incorporation (using Ni0:78Al0:22 alloy) 34

Fig 2.10 VFB vs T ox plots for Φm extraction of (a) FUSI and (b)

Ni-FUGE gates in this work Lower Ni(Al)Si and Ni(Al)Ge gate

Φm are expected from the VFB values in the plots 34

Fig 2.11 Al incorporation was able to reduce the Φm of NiSi and NiGe by

~0.2 and ~0.6 eV, respectively A saturation in Ni(Ai)Si and Ni(Ai)Ge Φm at ~4.4 eV was observed 35

Fig 2.12 TEM image of a (a) Ni(Al)Si and (b) Ni(Al)Ge gate stack

showing a bilayer structure EDX verified that the Al concentration was not uniformly distributed in both gate stacks

Al atomic concentration at various spots in the TEM images is indicated in white boxes 36

Fig 2.13 High resolution TEM images of (a) Ni(Al)Si and (b) Ni(Al)Ge

gates do not show visible degradation of gate dielectric 37

Fig 2.14 NiSi and NiGe XRD phases were detected from blanket

Ni(Al)Si and Ni(Al)Ge films This indicated the absence of ternary silicide or germanide formation 38

Fig 2.15 The T ox and Q f values of Ni-FUSI and Ni-FUGE gates (with and

without Al incorporation) are plotted for comparison The

decrease in T ox observed for both Ni(Al)Si and Ni(Al)Ge gates indicated that Al had reacted with the SiO2 dielectric

Furthermore, the decrease in positive Q f suggests the growth of

an interfacial Al2O3 layer which generated negative fixed charges 39

Fig 3.1 (a) C-V curves show significant VFB shifts of ~0.6 – 0.8 V from

NiSi control were obtained for REIL incorporated gate stacks A wide selection of RE materials was investigated, including Y, Er,

Dy, Tb, Gd, Yb, and La NiSi (60 nm)/REIL(~1 – 1.5 nm)/SiO2

gate stacks were formed using an initial SiO2 layer of 3 nm (b)

Tight VFB distributions for REIL gate stacks confirmed the uniformity of REIL formation by sputtering 50

Fig 3.2 (a) VFB versus T ox plot was used to extract the modulated NiSi

Φm in a NiSi (~60 nm)/REIL(~1 – 1.5 nm)/SiO2 gate stack by eliminating the effect of fixed oxide charge The initial SiO2

thicknesses were ~3 – 7 nm and no high temperature annealing was conducted prior to gate silicidation (b) The band-edge NMOS NiSi Φm (3.77 – 4.01 eV) obtained using different REIL

is shown 51

Fig 3.3 A comparison of NiSi (solid symbols) and TaN (open symbols)

Φm modulated by YIL and TbIL with different anneal conditions

YIL data are plotted in square symbols and TbIL data are plotted

in circle symbols 52

Fig 3.4 XRD spectra confirming that NiSi and Ni31Si12 are the

Ni-silicide phases obtained after gate silicidation at 500ºC using

TNi/TSi of 0.7 and 1.3, respectively 53

Fig 3.5 (a) REIL modulates the Ni31Si12 gate Φm to a lesser extent, as

compared to the NiSi gate Ni31Si12 Φm of 4.25 – 4.48 eV for

YIL, ErIL, DyIL, and LaIL were attained (b) NiSi Φm tunability

could also be achieved between Si midgap and Ec by varying the interlayer thickness 54

Fig 3.6 A saturation in NiSi Φm tunability at 4.05±0.5 eV using either

YIL, or TbIL is observed when the sputtered RE thickness exceeds ~1 nm 55

Fig 3.7 The XPS spectra of Y deposited on 3 nm SiO2 before and after

PDA is shown The increase in Y-O-Si bonding after PDA clearly indicated Y-silicate formation on SiO2 dielectric 56

Fig 3.8 Rare-earth (RE) core level and O 1s spectra for (a) ErIL, (b) LaIL

and (c) YIL formed on 3 nm SiO2 The presence of RE-O-Si (RE-silicate) bonds are clearly observed 57

Fig 3.9 HRTEM images of NiSi gate stack with (a) ErIL, (b) TbIL, and (c)

YIL showing excellent gate/REIL interface and uniform formation throughout the dielectric 58

Fig 3.10 Backside SIMS profile of NiSi/YIL/SiO2 gate stack confirmed

that there was no Y diffusion into the Si substrate which might degrade device characteristics 59

Fig 3.11 (a) Typical gate leakage and (b) breakdown voltage showed

better characteristics for NiSi gate stack incorporating a YIL and

a TbIL A RTA at 950ºC was conducted before FUSI for the gate stacks 60

Fig 3.12 (a) A schematic showing highly polarized RE-O dipoles at the

NiSi/SiO2 interface (b) The effect of an interface dipole layer

on NiSi Φm is illustrated in the energy band diagram NiSi Φm is reduced by ∆Φm due to the presence of the interface dipole 61

Fig 3.13 NiSi gate Φm are found to be inversely proportional to ∆χ × d

RE-O This indicates that a larger magnitude in RE-O dipole moment would result in a lower effective gate Φm The magnitude of La-O dipole moment is the largest among all the

RE metals studied in this work 63

Fig 3.14 The deposition of La (~1 nm) at the NiSi/HfO2 interface for a

NiSi/high-k gate stack resulted in NMOS VFB modulation, whereby thinner HfO2 (2 nm) was observed to give a larger VFB

shift The dielectric stack before PDA is shown schematically as

an inset 64

Fig.3.15 SIMS profiles of NiSi/high-k stacks with La deposited at (a)

HfO2/SiO2 interface or (b) NiSi/HfO2 interface The initial HfO2 and SiO2 thickness was 3 nm, and the deposited La thickness was ~1 nm The difference in the relative positions of

La after gate stack formation can be observed from the SIMS profile 65

Fig 3.16 (a) A significant difference in VFB shift was observed when the

La (~1 nm) was deposited at the HfO2/SiO2 interface instead of the NiSi/HfO2 interface The VFB (~1.25 V) obtained for La deposited at the HfO2/SiO2 interface, was similar to that of a NiSi/LaIL/SiO2 gate stack (b) Band-edge NMOS NiSi Φm

modulation could be obtained for a scaled HfO2/LaIL/SiO2

dielectric stack in a high-temperature gate-first flow by interface dipole engineering 67

Fig 4.1 The interlayer (IL) metal splits for the dielectric stacks (before

PDA was conducted) are schematically shown Different IL metals were sputtered to incorporate Tb-induced (n-type) and Al-induced (p-type) dipoles into the metal gate stacks 77

Fig 4.2 NMOS and PMOS TaN Φm tunability is verified by

independently forming (a) Tb-based and (b) Al-based IL, respectively, on SiO2 dielectric 79

Fig 4.3 VFB shift is clearly observed for TaN gate stack incorporated

with either a Tb-based or Al-based IL from the C-V curves A

TaN/SiO2 gate stack is plotted as a reference 79

Fig 4.4 VFB vs Tox plots of Tb/Al/SiO2 dielectric stacks with varying TTb

(0.5, 1, or 2 nm) and fixed TAl (0.5 nm) after 500ºC or 950ºC

PMA An increase in TTb monotonically decreases the TaN Φm 80

Fig 4.5 HRTEM images of TaN/Tb(2nm)/Al(0.5nm)/SiO2 stack after (a)

500ºC and (b) 950ºC PMA and (c) TaN/Al(0.5nm)/SiO2 stack after 950ºC PMA IL’s of ~1.5 – 2nm was observed at the TaN/SiO2 interface No Al or Tb presence was detected by EDS in the underlying SiO2 81

Fig 4.6 Tb- or Al-induced interface dipole densities can be manipulated

to modulate the effective TaN gate Φm (for both 500ºC and 950ºC PMA) continuously by varying IL metal thicknesses 81

Fig 4.7 TaN Φm for a Tb/Al/SiO2 dielectric stack with (a) a varying TTb

and a fixed TAl, or (b) a varying TAl and a fixed TTb after different PMA conditions The Φm modulation trend suggests that Tb-induced (n-type) dipole formation dominates after 500ºC PMA, and Al-induced (p-type) dipole formation is favored after 950ºC PMA 82

Fig 4.8 TaN Φm for a Al/Tb/SiO2 dielectric stack with (a) a varying TTb

and a fixed TAl, or (b) a varying TAl and a fixed TTb after different PMA conditions Since TaN Φm values and modulation trends for the Al/Tb/SiO2 stack are similar to the Tb/Al/SiO2 stack when TAl/TTb and TTb/TAl are equal, it was concluded that there was no dependence in deposition sequence

of the IL metals on dipole formation 83

Fig 4.9 A comparison in TaN Φm for Al/SiO2, Tb/Al/SiO2 and

AlTb/SiO2 dielectric stacks showed that a 950ºC PDA has the same effect in increasing the effective gate Φm as a 950ºC PMA

The Φm increase is attributed to increased Al-induced (p-type) dipole formation at the 950ºC anneal 84

Fig 4.10 Al-O-(Si) bonding (~75.65 eV) is observed for all samples after

950ºC PDA The large binding energy difference for AlTb/SiO2

and Tb/Al/SiO2 dielectric stacks between 700 and 950 ºC PDA shows that the presence of Tb hinders Al-O-(Si) bond formation

at 700ºC PDA 85

Fig 4.11 (a) Tb-O-Si bonding is observed from the oxidized Si 2p peak

shoulder for 700ºC PDA This accounts for the low gate Φm in Tb/Al/SiO2 and AlTb/SiO2 stacks (b) A decrease in Tb-O-Si bonding is seen after 950ºC PDA This reduction in Tb-O-Si bonding together with the increase in Al-O-(Si) bonding supports the Φm increase for the 950ºC PDA split (Fig 4.9) 86

Fig 4.12 (a) Schematic diagram showing the net dipole direction for

completed TaN gate stacks after different anneal conditions for

a AlTb/SiO2 dielectric stack (b) Energy band diagrams that depict how the net dipole direction results in the observed Φm

change after the different anneal conditions highlighted in (a) 87

Fig 4.13 The incorporation of Tb or Al in a HfO2 (2 nm)/SiO2 dielectric

stack shows similar gate Φm tunability as in a SiO2 stack When

Tb or Al is deposited above a thicker HfO2 layer (5 nm), the Φm

tunability is reduced This was due to the hindrance in dipole formation at the HfO2/SiO2 interface 88

Fig 4.14 Higher Φm values for the AlTb/HfO2/SiO2 stack than

HfO2/AlTb/SiO2 stack indicate a higher p-type dipole density (over n-type dipole) at the HfO2/SiO2 interface High Al diffusivity and increased Al-induced dipole formation at 950ºC PMA, enables reversal of the net dipole polarity for the Al/HfO2/Tb/SiO2 stack over the Tb/HfO2/Al/SiO2 stack 89

Fig 4.15 Backside SIMS shows the diffusion of Al beyond the HfO2 and

Tb layer after 950ºC RTA for a TaN/Al/HfO2/Tb/SiO2 stack

Inset shows schematically how Al diffuses through the layers to reach the SiO2 layer 90

Fig 4.16 The addition of Tb (1 nm) reduces the Vth by ~0.4 V (over

HfO2/SiO2 stack) due to the presence of an n-type dipole The incorporation of Al (0.5 nm) reverses the net dipole polarity and

shifts the Vth by ~0.5 V in the opposite direction Inset shows

tight Vth distribution of the devices 91

Fig 4.17 (a) TaAlN gate was employed to incorporate p-type dipole from

the metal gate to reverse n-type dipole pinning existing in the

initial gate dielectric stack (b) C-V curves of TaAlN-gated

HfO2/Tb/SiO2 gate dielectric stack after 500ºC and 950ºC RTA

showing large VFB shift of ~0.75 V 92

Fig 4.18 N-type Φm tunability obtained on HfLaO dielectric for a wide

variety of metal gates including Mo, TaC, TiN, HfN, and TaN 93

Fig 4.19 VFB versus T ox plot shows that the Mo/Al2O3/SiO2 and the

Mo-Al/SiO2 gate stacks have larger effective Φm than the Mo/SiO2

gate stack All gate stacks underwent RTA at 950ºC 94

Fig 4.20 Mo0.81Al0.19 gate on HfLaO(3 nm)/SiO2(1 nm) dielectric

exhibiting significant VFB increase (over Mo gate) after 950ºC RTA with increasing annealing time The inset summarizes the

VFB for Mo1-xAlx gates (x = 0.14 and 0.19) after 950ºC RTA 96

Fig 4.21 The Vth shift of ~0.5 V obtained for nMOSFETs with

Mo/HfLaO and Mo0.86Al0.14/HfLaO gate stacks confirmed the larger effective Φm for Mo-Al gate 97

Fig 4.22 The backside SIMS profile of a Mo0.81Al0.19/HfLaO(3

nm)/SiO2(1 nm) gate stack showed that Al from Mo-Al gate diffused into the HfLaO dielectric layer The confinement of Al

in the HfLaO layer was clearly observed with no Al diffusion into the Si substrate 97

Fig 4.23 (a) The schematic of a Mo/HfLaO/SiO2 (left) and a

Mo-Al/HfLaO/SiO2 (right) gate stack shows the difference in interface dipole formation due to the presence of Al in the gate after a high temperature anneal (b) Energy band diagram of a Mo/HfLaO/SiO2 (left) and a Mo-Al/HfLaO/SiO2 (right) gate stack depicts how the effective interface dipole magnitude at the high-k/SiO2 interface would be reduced after Al-induced dipole formation 99

Fig 5.1 A simplified integration scheme employing metal interdiffusion

to achieve dual Φm metal gates The completed metal gate

stacks consist of a TaN capping layer and either Metal 1, or an

interdiffused metal layer which controls the gate Φm 109

Fig 5.2 (a) C-V curves of TaN/Hf/Ni stacks after FGA, with TaN/Ni (10

nm) stack plotted as reference VFB decreases monotonically

when Hf/Ni thickness ratio (THf/TNi) is increased (b) The extracted Φm of interdiffused Hf/Ni stacks with varying THf/TNi

are plotted 111

Fig 5.3 C-V curves of TaN/Ni/Ni-Hf stacks after FGA, with TaN/Ni-Hf

(5 nm) stack plotted as reference No significant increase in VFB

was observed for the Ni/Ni-Hf stacks from the Ni-Hf control stack after FGA 112

Fig 5.4 SIMS depth profile of (a) as deposited and (b) annealed profile

for TaN (15 nm)/Hf (7 nm)/Ni (10 nm)/SiO2 stack The interdiffusion of Hf into the Ni layer was clearly observed 112

Fig 5.5 SIMS depth profile of (a) as deposited and (b) annealed profile

for TaN (15 nm)/Ni (10 nm)/Ni-Hf (5 nm)/SiO2 stack Both Ni and Ni-Hf layers can be distinctly observed after annealing, showing the lack of interdiffusion 113

Fig 5.6 C-V curves of (a) Hf/Pt stack with THf/TPt = 1.40 and (b)

Pt/Pt-Hf stack with TPt/TPt-Hf = 2.00, after different annealing conditions Single-layer Pt (10 nm) and Pt-Hf (5 nm) stacks after FGA are plotted as dashed lines for reference A generally

larger VFB shift was observed with higher anneal temperatures 114

Fig 5.7 Φm summary of Hf/Pt and Pt/Pt-Hf stacks with after different

annealing conditions for metal interdiffusion The Φm of layer Pt and Pt-Hf stacks after FGA are plotted for reference 115

single-Fig 5.8 Comparison of XPS depth profile for TaN (15 nm)/Hf (7 nm)/Pt

(5 nm)/SiO2 blanket gate stack after (a) 500°C RTA and (b) 700°C RTA More interdiffusion and higher Hf concentration

at the gate/SiO2 interface was observed for the 700°C RTA 115

Fig 5.9 C-V curves of interdiffused Hf/Pt stacks on (a) HfO2/SiO2 and

(b) HfLaOx/SiO2 after 700°C RTA shows Φm tunability from single layer Pt stack 118

Fig 5.10 Φm values for Pt and Hf/Pt stacks after 500 – 700°C RTA on

both HfO2 and HfLaOx dielectrics Φm modulation over Pt stack was attained through metal interdiffusion of Hf/Pt stack for both dielectrics 118

List of Symbols

dRE-O Rare-earth and oxygen ion dipole charge separation Å

E F, n+ poly Fermi-level energy of n+ poly-Si gate eV

E F, Si-sub Fermi-level energy of Si substrate eV

Q d Depletion layer charge in channel region C/cm2

µ Dipole moment between rare-earth and oxygen ion None

ρ Charge transfer between rare-earth and oxygen ion None

2

SiO

φb Potential difference between Fermi-level and

intrinsic Fermi level in Si V

Chapter 1

Introduction

1.1 Overview for CMOS Scaling

As predicted by Moore’s law, there has been an exponential increase in transistor density on integrated circuit (IC) chips for more than four decades [1.1] This was predominantly achieved through transistor scaling based on the criteria proposed by

Dennard et al [1.2] Since the 1970’s, the minimum feature size of transistors was

reduced by a factor ~0.7 times in successive complementary metal-oxide-semiconductor (CMOS) technology nodes The increase in packing density per unit chip area for state-of-the-art IC’s has enabled better performance in terms of speed and functionality through the years However, as we advance further into sub-32 nm regime in current CMOS technology, the fundamental physical limitations of transistor scaling approaches Aggressively-scaled transistors also lead to high leakage currents that will inhibit performance gains if excessive power consumption by the semiconductor chip is not controlled Hence, it is imperative to review the physical scaling trend and consider other alternative technological solutions for continued development in future generation nodes

The International Technology Roadmap for Semiconductors (ITRS) was developed as a guideline to identify key technical requirements and imminent technological challenges faced by the semiconductor industry in the future [1.3] Multiple material, process and device structure changes are projected over the coming years to ensure that key logic technology requirements are met The scaling of planar

metal-oxide-semiconductor-field-effect transistor (MOSFET) down to 32 nm node and beyond faces tremendous challenges The transistor channel would have to be heavily-doped to reduce short channel effect (SCE) This leads to mobility degradation, increased junction leakage and stochastic doping variations that will affect device performance Devices with novel structures such as ultra-thin body fully depleted silicon-on-insulator and multiple-gate transistors have typically lightly doped channels,

and the threshold voltages (Vth) will be controlled by the metal gate electrode’s work function (Φm) [1.4] Therefore, challenges associated with high channel doping in scaled planar bulk transistors will be avoided Despite the advantages of implementing transistors with these advanced structures, numerous new challenges lie ahead such as the difficulty in controlling Si-body thickness, and the variability for these ultra-thin structures

A direct method to control SCE would be the scaling down of the gate stack to increase gate-to-channel coupling At present, gate dielectric thickness has become so thin that gate leakage densities due to direct tunneling of electrons are reaching unacceptable levels for logic technology, especially for high performance logic High-k dielectrics have been proposed as an alternative to conventional silicon oxy-nitride dielectrics to suppress gate leakage, and the most promising candidate seems to be hafnium-based dielectrics [1.5], [1.6] The replacement of the conventional doped polysilicon gate with a metal gate electrode is also expected for integration with high-k dielectrics There has been a recent breakthrough in the implementation of metal gate/high-k gate stack for CMOS devices in high volume production [1.7] However, research on issues such as optimization of n- and p-type gate Φm, physics in metal-

dielectric interface, and gate stack reliability are still on-going for improvements in future technology nodes

To further boost transistor performance, carrier mobility in transistor channel needs to be enhanced through strain engineering The use of lattice-mismatched source-drain (S/D) stressors [1.8], [1.9], and high-stress liners [1.10], [1.11] are both effective approaches in inducing strain in the transistor channel Still, the strain generated using these techniques tend to decrease with scaling, and solutions to maintain strain in scaled structures are required There is no doubt that the application of dimensional scaling, together with the integration of novel materials, processes, and device architectures will

be crucial in meeting performance targets for the coming CMOS generation nodes

1.2 Why Metal Gate Electrodes?

Polysilicon (poly-Si) gate depletion limits electrical oxide thickness scaling and therefore, reduces gate capacitance in the inversion regime (Fig 1.1) This lowers the inversion layer charge density and restricts device performance enhancement in scaled MOSFETs The doping concentration in poly-Si gates has to be increased to reduce the poly-Si gate depletion effect, but this is limited by the equilibrium dopant solubility in poly-Si and the penetration of dopants through ultrathin gate dielectrics [1.12] As a result, metal-gate electrodes are required for the elimination of poly-Si depletion and dopant penetration problem Metal gates also offer a lower gate sheet resistance compared to doped poly-Si gates Despite the obvious advantages in the implementation

of metal gate technology, initial research on high-k dielectrics were conducted using poly-Si gates electrodes to avoid major changes to the MOSFET gate stack

2 4 6 8 10 12 14 16

Accumulation Regime

No poly-gate depletion

Inversion Regime

Fig 1.1 (a) The energy band diagram of an NMOSFET showing the poly-Si gate depletion layer

during inversion bias (b) The capacitance-voltage plot depicts how the poly-Si gate depletion effect decreases the gate capacitance in the inversion regime

However, it soon became evident that metal gate electrodes were required with high-k dielectrics due to serious Φm pinning effects faced by poly-Si/high-k gate stacks [1.13] This was caused by the reaction of poly-Si gate with the high-k dielectric after post-deposition annealing steps Thereafter, the advent of metal gates became unavoidable and the feasibility of a metal gate/high-k gate stack was further affirmed by the demonstration of CMOS transistors with high drive currents [1.14]

One of the most important parameters for metal gate candidates is the Φm because

it directly affects the Vth of the MOSFET The Vth of a MOSFET is typically given by the following expression [1.15]:

ox

b b Si b

ox

d b

C

qN V

C

Q V

Fermi-level and the intrinsic level in Si, Q d is the total depletion charge in the channel

region, C ox is the gate oxide capacitance, εSi is the permittivity of Si, q is the electronic charge, and N b is the doping concentration of Si substrate (for uniform channel doping).

VFB can be given further by the following equation:

ox SiO

f Si

m ox

f Si

C

Q q V

−

=

ε

ΦΦΦ

Φ

where ΦSi is the Si substrate work function, Q f is the fixed oxide charge density, εSiO2 is the permittivity of SiO2, and T ox is the equivalent oxide thickness Hence, for a given

technology node (fixed N d and T ox), the metal gate Φm would determine the Vth To

obtain low and symmetrical Vth for optimal CMOS device performance, the metal gate

Φm must be close to the silicon conduction and valence bands for n and p-channel bulk CMOS transistors, respectively, or about 0.2 eV above and below the intrinsic Si Fermi level is required for advanced transistor structures (ultra-thin body fully depleted silicon-on-insulator and multiple-gate transistors) [1.16] The metal gate Φm requirements for both planar bulk transistors and transistors with advanced structures are shown in Fig 1.2

Bulk NMOS (< 0.2 eV below E c)

Bulk PMOS (< 0.2 eV above E v)

Transistors with advanced structures (± 0.2 eV from Si midgap)

Fig 1.2 Metal gate Φm requirements for both planar bulk transistors and transistors with advanced structures are shown

However, metal gate Φm values on high-k dielectric differ from their vacuum Φm

due to the presence of metal-induced gap states [1.17] These gap states result in charge transfer across the metal-dielectric interface which shifts the metal Fermi-level, and changes the effective metal gate Φm Additional factors such as the formation of extrinsic states, oxygen (O) vacancies, and internal dipole formation were also found to influence the effective gate Φm after extensive research was conducted for various metal gate systems [1.18]-[1.20] As such, the implementation of metal gate/high-k dielectric gate stack is not a straightforward process, and substantial efforts are required for material selection and integration into the mainstream CMOS process

1.2.1 Current Status in Metal Gate Technology

Metal gates can be realized in two general approaches: gate-first and gate-last The former approach retains the order of standard poly-Si gate process flow There are however, concerns over the contamination of front-end tools during processing, difficulty

in metal etching, and integrity of the gate stack during high-temperature annealing The gate-last approach is also called a replacement gate technique, where a dummy gate is removed after all doping and high-temperature processes are completed Its main challenge is the dummy gate stack removal and replacement

Preliminary research on metal gates involved screening a large number of materials including pure metals and their alloys, as well as metal silicides, nitrides and carbides One of the most widely researched metal gate options is the application of a fully-silicided (FUSI) nickel silicide (NiSi) gate electrode [1.21] The process of fully siliciding a poly-Si gate electrode with Ni is simple, and compatible with conventional

CMOS flow The modulation of midgap NiSi Φm is highly desired and the possibility of

Φm tuning through doping, phase and alloying has been demonstrated [1.22]-[1.24] Despite this, Ni-silicidation process is very sensitive to local supply of metal atoms and process temperature [1.25], [1.26], and issues relating to yield control have not been fully resolved yet

The use of other metal gate candidates like metals (and their alloys), metal nitride

or metal carbide system requires a more elaborate approach because two gate electrodes with different Φm are needed for NMOS and PMOS The formation of dual Φm

electrodes using two different metal gate material will require a double masking and etching process step, regardless of whether a gate-first [1.27] or gate-last [1.7] approach

is chosen Novel CMOS integration schemes have been proposed in which the underlying gate dielectric is protected from being exposed during gate patterning, while ensuring two distinct gate Φm are attained [1.28], [1.29] A single metal gate scheme has also been used to reduce process integration complexity [1.30], but additional process steps may be required for gate Φm modulation to achieve low Vth in CMOS transistors The different metal gate integration approaches for CMOS devices is given in Table 1.1 Recently, the use of lanthanide- and Al-based dielectric capping layers has been

successfully used for Vth tuning, but more work is needed to clarify its mechanism for material selection and process optimization [1.31] There are various materials and integration schemes to implement metal gate/high-k stacks, and it is unlikely that all research groups will be employing the same method Therefore, continuous research is essential to allow a smooth transition from the current conventional poly-Si/SiON gate stack to a metal gate/high-k gate stack for future CMOS technology nodes

Table 1.1 A summary of different metal gate integration approaches for CMOS devices

Metal gate integration

One metal M1 M1 • 1 masking step

• Other methods for Φm tuning to

achieve low Vth may be required Two metals M1 M2 • 2 masking steps

• Gate Φm individually tuned by M1 and M2

Two metals, metal

interdiffusion for either

NMOS or PMOS

M1 M1 + M2 • 2 masking steps

• Metal alloy (M1 + M2) formed after interdiffusion for desired gate Φm [1.28]

Two metals, different

bottom metal (M1)

thickness for NMOS and

PMOS

Thick M1 M2 on Thin M1 • 2 masking steps

• When bottom metal (M1) is sufficiently thin, top metal (M2) contributes to the gate Φm [1.29] FUSI gate M1 silicide M1 silicide • 1 masking step

• Gate Φm can be tuned by various methods [1.22]-[1.24]

M1 = Metal 1, M2 = Metal 2

1.2.2 Work Function Extraction Method

As mentioned before, vacuum Φm of metal gates electrodes can differ appreciably from their effective gate Φm in MOS gate stacks Therefore, metal gate Φm calculated using photoelectric effect or thermionic emission [1.32] is not representative of the expected value when integrated into a MOS gate stack From Eqn 1.2, we see that metal gate Φm can be calculated from VFB of the capacitance-voltage (C-V) curve, if the contribution of Q f can be eliminated This is done by linearly extrapolating the VFB

versus T ox plot to obtain VFB at T ox = 0 In addition, the slope of the VFB versus T ox plot

gives us the Q f Therefore, this method has been traditionally used to extract metal gate

Φm on SiO2 dielectric, whereby Q f is assumed to be constant on different dielectric thicknesses By employing an etchback of thermally grown SiO2 using dilute

hydrofluoric acid, we are able to assume constant Q f in our MOS capacitors formed on different SiO2 thicknesses [Fig 1.3 (a)]

However, when varying high-k dielectric thicknesses, bulk charges in the

dielectric shift the VFB, and the high-k dielectrics react with the Si substrate to form interfacial SiOx, making it difficult to maintain a constant fixed interface charge at the dielectric-Si substrate interface [1.33] Hence, extracting metal gate Φm values from the

VFB versus T ox plot through the varying of high-k dielectric thicknesses will lead to high

inaccuracies It was reported that the contributions of charges in the high-k on VFB can be minimized to ~±50 meV by using a fixed and thinned high-k film of ~2–3 nm on terraced SiO2 [1.34] Therefore, a dielectric stack with a single high-k thickness on varying SiO2

thicknesses will limit the influence of high-k bulk charges and enable a reasonably accurate Φm extraction [Fig 1.3(b)]

Fig 1.3 An illustration of (a) metal gate/SiO2 and (b) metal gate/high-k stacks formed with different SiO 2 thicknesses through a SiO 2 etchback scheme on the same wafer for metal gate Φm

extraction

Another method that could be used in calculating the metal gate Φm is through extraction of the barrier height between the metal gate and gate dielectric interface by

current density-voltage (J-V) measurements The barrier height at the metal/dielectric

interface is taken from the applied voltage when current conduction mechanism transits from direct tunneling to Fowler-Nordheim tunneling Reasonable correlations were obtained between metal gate Φm calculated by C-V and J-V measurements, validating both techniques [1.34], [1.35] The disadvantage in the J-V measurement is that it cannot

be used on thin gate dielectrics where direct tunneling dominates or early breakdown occurs Therefore, in this work, all Φm values were extracted using the C-V method from

MOS stacks shown in Fig 1.3 to ensure consistency

1.3 Objective of Research

From the ITRS, material innovations such as metal gate electrodes and high-k dielectrics are specified as near term changes, and are projected for implementation over the next five years Hence, it is essential that the key challenges for advanced gate stacks are engaged and strategic research be focused on the most pressing issues The objective

of this thesis is to explore novel materials and processes for metal gate technology Areas specific to Φm modulation techniques and possible process integration schemes for metal gates will be investigated A comprehensive evaluation of various aspects of metal gate technology based on experimental results is furnished in this work The new data comprising electrical and material analysis will assist in the assessment of metal gate electrode implementation in future generation transistors

1.4 Thesis Organization

This thesis covers research work pertaining to metal gate technology and the main results are divided in the following four chapters

In Chapter 2, nickel-alloying with terbium (Tb) or aluminum (Al) for Ni-FUSI

gate Φm modulation was investigated The mechanisms for Φm lowering of Ni-FUSI gate using both these alloys were elucidated through detailed material analysis Nickel-aluminum alloying was further used to demonstrate the large Φm tunability obtainable on

Ni fully-germanided gates based on its Φm lowering mechanism The limitations of these

Φm tuning methods will also be discussed

In Chapter 3, a novel and alternative Ni-FUSI gate Φm tuning method using earth (RE) –based interlayers formed on SiO2 dielectric was demonstrated for the first time An extensive range of RE metals was screened for wide NMOS Ni-FUSI gate Φm

rare-tunability, and an interface dipole model was proposed to explain the observed Φm shifts Electrical and material analysis was conducted to ascertain the attractiveness of this Φm

tuning technique Additional insights were given for the application of these novel interlayers in high-k gate dielectric stacks to attain band-edge Ni-FUSI gate Φm tunability

in a gate-first process flow

In Chapter 4, a comprehensive study of manipulating interface dipoles for Φm

tunability was performed The combination of n- and p-type dipoles using Tb and Al –based interlayers, respectively, in a single metal gate stack for Φm engineering was carried out We show that net interface dipole polarity in a metal gate stack can be reversed through the creation of dipoles with opposing polarity The importance of Tb and Al reaction with SiO2 for induced dipole formation was established Factors like

annealing temperature and diffusivity in high-k stacks were also found to critically affect dipole formation based on the type of dipole-inducing elements used

In Chapter 5, we investigate the use of thin metallic layers (less than or equal to

10 nm) for metal gate Φm control through metal interdiffusion Nickel (Ni), platinum (Pt), hafnium (Hf), and their alloys (Ni-Hf and Pt-Hf) were explored as the metallic interdiffusing layers The dependence of metal gate Φm on thickness ratios before interdiffusion, and annealing temperature was studied The compatibility of this Φm

modulation technique on high-k dielectrics was also verified

Finally, the main contributions of this thesis and suggestions for future work are

summarized in Chapter 6

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