Advanced materials and novel devices for CMOS applications

Chapter 3 focuses on strained Si n-FET where tensile strain in the channel is induced by lattice mismatched Si or Si:C S/D stressors and high stress tensile nitride liner.. It is shown a

ADVACED MATERIALS AD OVEL DEVICES FOR

CMOS APPLICATIOS

WAG HUIQI, GRACE

A THESIS SUBMITTED FOR THE DEGREE OF Ph.D (EGIEERIG) GRADUATE SCHOOL FOR ITEGRATIVE SCIECES AD EGIEERIG

ATIOAL UIVERSITY OF SIGAPORE

2009

ABSTRACT

Conventional transistor scaling becomes increasingly challenging beyond the 90nm technology node New approaches for the improvement of integrated circuit performance are needed This thesis documents novel ways to introduce strain in transistor channel New device structure and new materials are needed to boost carrier mobility and enhance drive current

Chapter 2 of this thesis documents techniques of forming high germanium (Ge) content substrates using Ge condensation technique Substrates with high Ge concentration could be employed in stress inducing structures or for high mobility channel transistors Chapter 3 focuses on strained Si n-FET where tensile strain in the channel is induced by lattice mismatched Si or Si:C S/D stressors and high stress tensile nitride liner The Si:C S/D may be potentially adopted in future technology nodes Chapter 4 documents another new approach of having a strain transfer structure beneath the channel to couple high stress from the S/D to the channel After the carrier mobility has been improved significantly, series resistance may become a performance limiter In Chapter 5, we thus explore in situ doped Si0.979C0.021 S/D stressor that mitigates the need for ion implantation, and enables higher activated dopant concentration A higher substitutional carbon concentration in Si:C was also used to increase the channel strain

Chapter 6 and 7 report the formation of SiGeSn and GeSn formed by Sn implantation and anneal The compressive strain in the channel induced by the SiGeSn S/D increases the effective mobility of holes, and boost p-FET performance

In summary, novel devices employing novel strain engineering techniques were studied They show promising potential for augmenting the performance of conventional CMOS transistors

ACKOWLEDGEMETS

I would like to express my sincere gratitude to God and my religion for his guidance, love and compassion showered to me, throughout my years of studies and life and for showing me the direction in times of helplessness This thesis is dedicated to God God facilitated in the completion of this thesis and provided significant guidance to my life I owe more than words can describe to God My steadfast belief in the existence of God leads me towards the correct track in all times I see my God as a boundless salvific nature and who is present to liberate me from ignorance and suffering

I would like to express my sincere gratitude to my advisor, A/Prof Yeo Yee-Chia for his generous help throughout my study at National University of Singapore (NUS) Prof Yeo is an admirable academic professional He taught me not only his precious knowledge, but also his exceptional professionalism and dedication to research He impressed me very much by his spirit, responsibility, passion and attitude in training students His drive is truly admirable I remember he once told me “Your passion in research should escalate with age” This truly reminded me I should not give up, and should persevere no matter how much failure or uncertainties I encounter in future He always provided timely support in difficult times, and gave me opportunities to present

my work at important conferences Despite the hectic research life, he gave me time to appreciate life outside research I learnt many important aspects of life from him, and learnt to work as a team Throughout my life I will benefit from the experience and knowledge I gained working with Prof Yeo

I am also grateful to my thesis advisors, A/Prof Zhu Chun Xiang from the National University of Singapore and Dr Subramanian Balakumar who had been very supportive

of my work I thank them for serving on my thesis committee

Special thanks to Dr Patrick Lo for facilitating my fabrication work at the Institute of Microelectronics (IME) I also thank the research staffs and engineer assistants at IME for their support I thank the staff for always giving me priority when using their equipments, and appreciate it when they stay back just to help me complete my processes

I am also indebted to Dr Foo Yong Lim, Dr Debbie Seng, Dr Sudhinranjan Tripathy,

Mr Lim Poh Chong, Ms Vivian Lin Kaixin from Institute of Materials Research and Engineering (IMRE) for their valuable guidance and insightful suggestions which are indispensable for my research work All of them are well known scientists and are always there to share their experience in materials analysis for my devices’ use I thank them for allowing me to use their X-Ray Diffraction (XRD) tool, Raman tool, TOFSIM tool and Hall measurement tool I also thank them for their patience in teaching me and enjoy their friendly discussions I would like to thank Dr Tripathy for proof-reading my thesis, with his invaluable suggestions, I incorporated them in this thesis and learnt from him in the process I would also like to thank Dr Wang Xincai from Singapore Institute of Manufacturing Technology (SIMTECH) On many occasions, he had sacrificed his personal time to provide timely support and guidance and to ensure timely deliveries of

my work I sincerely appreciate his help and support rendered all these years whenever I need to use his laser equipment

I would also like to take this opportunity to express my heartmost gratitude to Mr Chan Taw Kuei, and Prof Osipowicz from Physics Department (NUS) for giving me unlimited access to their Rutherford Backscattering tool I thank Taw Kuei for providing

me with the data analysis and for always giving me priorities in completing the samples’ analysis

I would also like to take this opportunity to thank my working partner, Dr Toh Eng Huat who introduced me to simulations, process developments and shared his expertise in simulations He impressed me by his enthusiasm towards research, and his intelligence, wit and ambition to accomplish them Special thanks goes to Dr Tan Kian Ming for his encouragements and for livening the tense research atmosphere and I benefited immensely from the discussions we had; my colleagues at the Silicon Nano Device Laboratory (SNDL), for providing a wonderful research atmosphere to work in

It is my pleasure to acknowledge and thank my final year project colleagues, Grace Thng Shiwei, Charanya Kailash, Mabel Soe Wah Wah I appreciate their help in fabricating, measuring and deriving the characterization plots for my transistors as part of their final year projects I enjoyed the discussions with them and it was wonderful sharing

my experiences and knowledge with them I learnt a lot from them, and gained immensely from their creative perspectives and ideas I derived enthusiasm and their burning passion for research from them I hope they, too, had a great time working with

me

I would like to show my appreciation to the Agency of Science Technology and Research for financially supporting my course of my studies in NUS since my undergraduate days I would also like to show my appreciation to Agency of Science Technology and Research for providing me with overseas conference presentation opportunities and they had even given me a chance to present at the A*Star’s first inaugural graduate student conference I thank Prof Barry Halliwell, Prof Justine Burley for showering me with care and concern throughout my years of studies I would also like

to thank Prof Miranda Yap and Dr Chirsitna Chai for their concern Last but not least, I would also like to thank my friends from NGS, Siew Lay, Winston, Swee Jin, Jacelyn

Finally, I owe more than words can describe to my daddy, my mummy and my lovely brother, Henry I thank them for their care and love in my entire life, and thank daddy and mummy for the sacrifices they have made and support throughout my education They have been very supportive of me in all situations and under all circumstances,though they are often not recognized but are undoubtedly essential for my endeavours I thank Henry for his concern for me, and calling me every now and there on skype despite his hectic studies at Cornell University, New York Though he is physically distant from me, I appreciate and feel that he is always by my side, supporting and encouraging me even when things are not in my favor I owe more than words can describe to my family, and friends, Joan, Kaifen, Hanni, Cuilin, Fangying and Peichin

3.2.1 Background 263.2.3 Stress Simulation of strained Si MOSFET devices 293.2.4 Electrical Characterization of strained Si MOSFET devices 303.3 Strained n-FETs with Source/Drain Stressor and Tensile Liner 35

Strained Channel MOSFETs featuring Stress Transfer Layer and

Source/Drain Stressors for Enhanced Performance

5.3 Materials Characterization of SiC:P film 64

5.6 Conclusion 70CHAPTER 6

Strained SiGeSn and GeSn formed by Sn implant

6.2 SiGeSn formation by ion implantation and laser anneal 72

6.2.3 Materials Characterization and Analysis 746.3 GeSn Film Formation by Ion Implantation and Anneal 78

6.3.3 Material Characterization and Analysis of GeSn film 80

8.4 Strained n-FETs and p-FETs with strain transfer layer 1078.5 Strained n-FETs with in-situ P doped Si:C S/D Regions 1088.6 Strained SiGeSn and GeSn formed by Sn implant 1088.7 Strained p-FETs with SiGeSn S/D Regions formed by Sn implantation 108

CHAPTER 9

RECOMMEDATIOS FOR FUTURE WORK

LISTS OF FIGURES

Chapter 1

Figure 1.1 Valence band structure of (a) unstrained Si and (b) tensile strained Si on Si1-xGex

Biaxial tensile strain lowers the energy of the heavy hole and spin-orbit subbands relative to the light hole sub band and modifies the shape of the sub bands 8 Figure 1.2 Schematic representation of the constant energy ellipses for (a) unstrained Si and (b)

tensily strained Si resting on SiGe[28] 8 Figure 1.3 Conduction band splitting and sub-band energies lineups of Si under biaxial tensile

strain [28] 8 Figure 1.4 Si has a smaller lattice constant(5.431Å) than Ge (5.658Å) By Vegard’s law the

lattice constant of Si1-xGex will have a larger lattice constant than Si When Si is epitaxially grown on relaxed Si1-xGex, the Si layer will be stretched biaxially Si having smaller lattice constant will develop a tensile strain 10 Figure 1.5 Ge has a larger lattice constant (5.658Å) than Si (5.431Å) By Vegard’s law the

lattice constant of Si1-xGex will have a smaller lattice constant than Ge When Ge is epitaxially grown on relaxed Si1-xGex, the germanium layer will be squeezed biaxially

Ge having larger lattice constant will develop a compressive strain 10 Figure 1.6 Different types of globally strained Si substrate wafers (a) strained Si / relaxed SiGe

on Si substrate (b) strained Si/ relaxed SiGe – on – insulator (SGOI) (c) strained Si– insulator (sSOI) Each layer is grown at slow strain rate allowing nucleation rate of dislocations to be minimized Prexisting threads can be used to relax the strain in the graded layers, preventing new dislocations from nucleating 11 Figure 1.7 Strain in a device may have components in three directions; parallel to the MOS

device channel length, parallel to the device channel width, and perpendicular to the channel plane The strains parallel to the device channel length and width are called in-plane strains It is shown above that biaxial, in-plane tensile strain field can improve n-FET performance, and compressive strain parallel to channel length direction can improve p-FET device performance 13

Chapter 2

Figure 2.1 Schematic cross section and cross sectional TEM micrograph of Si1-xiGexi layer

pseudomorphically grown on SOI substrate There is minimal variation of the Ge concentration in the SiGe film along the lateral direction 18 Figure 2.2 Process flow illustrating cyclical oxidation and anneal performed at 9000C A cross-

sectional TEM micrograph at the bottom shows the Si1-xiGexi layer after the cyclic process and the FFT revealed excellent crystallinity of the SiGe film 21 Figure 2.3 The distribution of Ge concentration and SiGe film thickness in (a) Wafer B and (b)

Wafer E, illustrating that a more uniform distribution of Ge atoms can be achieved by performing cyclical oxidation and anneal during Ge condensation 22 Figure 2.4 HRTEM micrograph at the bottom shows the Si1-xiGexi layer after the cyclic process

and the revealed excellent crystallinity of the SiGe film and uniformity in the Ge composition 23 Figure 2.5 (a)The thickness variation in the SiGe film across the 200mm wafer illustrating that

there was a more non uniform distribution of Ge atoms (graduation from pink to yellow in coloration) when cyclical oxidation and anneal was absent during Ge condensation (b) The thickness variation in the SiGe film across the 200mm wafer was less significant illustrating that there was a more uniform distribution of Ge atoms when cyclical oxidation and anneal was performed during Ge condensation 23 Figure 2.6 AFM root-mean-square roughness data analysis of the SiGe layer as a function of the

fraction of anneal time over the total oxidation and annealing time The AFM images show the surface morphology of SiGe films Cross-hatch patterns are observed in Wafer B, while Wafer E demonstrates uniform and smooth morphology 25

Chapter 3

Figure 3.1 Schematic cross section showing (a) control SGOI n-FET with SiGe RSD, (b) strained

SGOI n-FET with Si RSD Both control and strained devices are structurally raised by 15nm 27 Figure 3.2 TEM image of strained SGOI n-FET with recess etched and raised Si S/D is featured

The gate electrode has a feature size of 70nm The arrows show how beneficial strain can be effected in the channel region for enhanced electron mobilities High Resolution transmission electron microscopy (HRTEM) image of strained SGOI n-FET with recess etched and raised Si S/D is shown The reciprocal space diffractogram is obtained by Fast Fourier Transform (FFT) of a selected region in the TEM image The diffractogram is then filtered to obtain the (002) reflection and the (220) reflection, which contain information about the lattice spacings in the vertical and lateral directions, respectively 28 Figure 3.3Process simulation showing compressive strained-Si0.75Ge0.25 under the Si stressor and

tensily strained-Si0.75Ge0.25 in the channel region The lateral strain is most compressive in the vicinity of the Si S/D stressor, and decreases with increasing depth Tensile strain is developed throughout the SiGe channel, which is the key for electron mobility enhancement in n-FET transistors 29 Figure 3.4 (a) ID-VD and (b) ID-VG characteristics for n-FET with Si selectively grown on S/D

regions ID enhancement of 20 % is observed at LG = 70 nm Si S/D n-FET shows significantly higher linear and saturation drive current over the control device 30 Figure 3.5 Ioff-IDsat plot comparing Si S/D devices and SiGe control devices showing drive current

improvement at a fixed off-state leakage current Ioff= 100 nA/µm All devices were corrected to obtain comparable series resistance Transistor width is 5 µµm 31

49% at VD = 0.05V, at a gate overdrive of 1.0V, over SGOI control n-FET

predominantly explained by the mobility increase in the carriers, associated with the incorporation of Si S/D stressors, as compared to the control SiGe devices 32 Figure 3.7 VT roll-off characteristics of the strained and control nMOSFETs VT,LI and VT,SAT for

strained SGOI and SGOI control n-FETs show similar VT roll-off characteristics and short channel effects 33

Figure 3.8 Drive current of strained SGOI device shows strong dependence on channel

orientations, consistent with the directional dependence of piezoresistance coefficients Highest IDsat is observed for channel orientation along the [010] as compared to [110] direction This is attributable to the preferential anisotropic electron repopulation at the 4-fold degenerate valley which results in smaller conductivity mass and substantial electron mobility enhancement 34 Figure 3.9 Schematic showing (a) control SGOI n-FET with SiGe RSD, (b) strained SGOI n-FET

with Si:C (or Si) RSD with d = 0, and (c) strained SGOI n-FET with Si:C (or Si) RSD with d > 0 A variant of (b) with tensile SiN liner was also fabricated 34 Figure 3.10 (a) TEM image of SGOI n-FET with raised Si0.99C0.01S/D A tensile nitride liner caps

the gate and S/D regions (b) Good Si0.99C0.01/ Si0.75Ge0.25 interface quality indicates pseudomorphic epiaxial growth with low defect density 36 Figure 3.11 Simulated lateral stress SXX (in Pa) for SiGe devices with selective epitaxial growth of

SiC raised S/D for (a) d = 0, h = 30 nm, and (b) d = 15 nm, h = 30 nm Higher stress is induced with recessed S/D stressor 36 Figure 3.12 (a) ID-VD characteristics for n-FET with Si selectively grown on recessed (d>0) and

unrecessed (d=0) S/D regions ID enhancement of 25% is observed at LG 50 nm for (d>0) devices (b) Higher drive current is achieved for Si:C grown on recessed S/D regions Current enhancements are additive with ESL ID enhancement of 68% is observed for devices with SiN ESL 37 Figure 3.13 (a) The ID-VG characteristic of a sub-50nm gate length SiC S/D n-FET and Si:C S/D

n-FET with ESL shows higher linear and saturation drive current over the control

improvement over the unstrained control device 38 Figure 3.14 Plot of drive current as a function of different orientationsfor control and different

splits of strained SGOI devices with different stressor Highest IDsat is observed for channel orientation along the [010] as compared to [110] direction Raised SiC formed

on recessed S/D regions shows higher IDsat. 39 Figure 3.15 (a) Plot of IDsat enhancement as a function of active area width Generally, reduction

in device width leads to a higher drain current enhancement Thus, a smaller active area is desirable (b) Strain relaxation is verified with the red shifts in the Raman peaks from 506.5 cm-1 for the width of 20 microns to 507.5cm-1 for a width of 5 microns 39

Chapter 4

Figure 4.1 TEM picture of a n-channel MOSFET with embedded Si0.7Ge0.3 STL and Si0.99C0.01

S/D, encapsulated with tensile ESL (Device G) The stress-transfer concept is illustrated on the right Lattice interactions between the Si0.7Ge0.3 STL and Si0.99C0.01

S/D stressors lead to vertical compression and horizontal elongation of the Si0.7Ge0.3

layer, which transfers lateral tensile strain to the overlying Si channel for additional performance enhancement The horizontal tensile strain in the Si channel region of the transistor structure is higher than that in a transistor with Si0.99C0.01 S/D alone or with Si0.7Ge0.3 STL alone 43 Figure 4.2 Schematics showing device structures fabricated in this work: (a) Unstrained control

(Device A), (b) Device B with biaxial strained-Si channel and Si S/D, (c) Device C with biaxial strained-Si and Si0.99C0.01 S/D, (d) Device D with unstrained Si-channel recessed Si0.99C0.01 S/D, (e) Device E with strained-Si channel and recessed Si S/D on SiGe strain-transfer layer (STL), and (f) Device F with strained-Si channel and recessed Si0.99C0.01 S/D on SiGe STL 44 Figure 4.3 Summary of the key process steps for fabricating the various device structures A

variant of Device F with tensile SiN ESL capping was also fabricated, named Device

G 46 Figure 4.4 Simulated stress Sxx (in MPa) contour plot for (a) Device D with recessed Si0.99C0.01

S/D, (b) SiGe STL and Si0.99C0.01 S/D S/D, and (c) SiGe STL and recessed Si0.99C0.01

S/D with mid-channel stress values of 460 MPa, 910 MPa, and 1750 MPa, respectively The non-additive stress effect of (a) and (b) support the effectiveness in integrating SiGe as the stress transfer layer for enhanced performance and drive current gain 47 Figure 4.5 (a) Plot of ID-VD for Devices A, D, and F At a gate overdrive of 1.0 V and VD of 1.0 V,

IDsat enhancement of 15.3% and 59% were achieved for Devices D and F, respectively, over Device A (control) The effectiveness in the STL, and its lattice interaction with the S/D stressors lead to substantial improvement in IDsat (b) ID-VD for Devices A, B and E IDsat enhancement of 24.5% and 48% is achieved for Devices B and E, respectively, over the unstrained control n-FET (Device A) 49 Figure 4.6 An illustration of various device structures which modulates the channel strain through

the integration of Si0.7Ge0.3 strain-transfer layer (STL) and Si or Si0.99C0.01 S/D

stressors The impact of various components of strain on device performance enhancement is clearly highlighted 49 Figure 4.7 (a) Plot of ID-VG for Devices A, D and F (b) Plot of Gm as a function of gate overdrive

(VG–VT) for Devices A, D and F A Gm enhancement of 117% was observed for Device F over the unstrained control Similarly, a Gm enhancement of 25% was observed for Device D over the control device 50 Figure 4.8 Narrower width of Device F results in more relaxation in active area due to removal of

lateral constraint at the edge of the active area This in turn translates to higher drive current enhancement Minimal width dependence was observed in devices on unstrained SOI control device 51 Figure 4.9 A p-FET with SOI STL and Si0.60Ge0.40S/D is shown in (a) (b) The strain-transistor

structure (STL) is beneath the strained-SiGe channel The graded Si0.60Ge0.40

source/drain (S/D) regions pull the Si region vertically, giving rise to a horizontal compression in the Si region which gets transferred to the Si0.75Ge0.25 channel region above it The spatial coordinates are such that the z-axis is in the vertical direction and the x-axis is in the horizontal directionThe horizontal compressive strain in the channel region of this transistor structure is higher than a transistor with SiGe S/D alone or with SOI STL alone Lattice interactions at the heterojunctions are illustrated 52 Figure 4.10 (a) Simulated stress Sxx (in GPa) contour plot for Device (b) recessed S/D, and (b) for

Device(d) featuring channel strain modulation with Si STL Midchannel stresses of 620MPa, and -1070MPa, respectively are observed 53 Figure 4.11 Schematic depicting various strain schemes employed in this work: (a)Unstained Si,

-(b) Recessed Si channel with Si0.75Ge0.25 S/D, (c) Biaxial strained Si0.75Ge0.25 channel, (d) Recessed Si0.75Ge025 S/D coupled with SOI STL, (e) Recessed graded e-Si0.6Ge0.4

S/D coupled with SOI STL 53 Figure 4.12 Process sequence showing key steps employed in strained transistors device

fabrication The integration of devices with SOI STL and graded Si0.6Ge0.4 S/D facilitates studies of strain effects that modulate the strained SiGe channel for IDsat

enhancement 55 Figure 4.13 TEM picture of Device (e) showing the proximity of SOI STL to the graded-

Si0.6Ge0.4 S/D for enhanced interaction EDS along the graded SiGe S/D shows the gradual increase in Ge content in the S/D region from 23% to 35.2% and slowly to 41.7% EDS confirms Ge concentration of 41.2% in the SiGe S/D 55

Figure 4.14 (a) Plot of ID-VD for Devices (a) and (c) IDsat enhancement of 30% is observed Due to

the higher hole mobility supported by the Si0.75Ge0.25 channel, IDsat is enhanced over the Si channel control.(b)ID-VD for Devices (c), (d) and (e) IDsat enhancement of 13%

is observed when Si0.75Ge025 interacts with SOI STL 54% enhancement is achieved with Si0.6Ge0.4 S/D, due to the enhanced lattice mismatch with the SOI STL and the

Si0.75Ge0.25 channel, which increases the strain effects at the vertical heterojunction 57 Figure 4.15 (a) Plot of ID-VG for Devices (c), (d), and (e) Similar DIBL and S.S were obtained for

the devices, justifying fair comparisons between devices (b) A Gm enhancement of 104% was observed in graded e-Si0.6Ge0.4 S/D (Device (f)) over unrecessed Si0.75Ge025

S/D device, indicating significant mobility improvement derived from the strain transfer between the Si0.6Ge0.4 S/D and SOI STL to induce in channel 57 Figure 4.16 At Ioff of 100nA/um, a saturation drive current enhancement of 43% is achieved for

Device (e) over biaxially strained Si0.75Ge025 S/D control device Device (c) Significant drive current improvement is attributed to the increased strain transfer efficiency due

to the enhanced lattice mismatch between the graded e-Si0.6Ge0.4 S/D and the SOI STL 58

Chapter 5

Figure 5.1 Schematic cross-sections showing (a) a control unstrained SOI n-FET with in situ

phosphorus-doped Si (Si:P) raised S/D, (b) a strained n-FET featuring strained Si on SGOI with in situ phosphorus-doped silicon-carbon (SiC:P) raised S/D Both control and strained devices have a S/D elevation h of 20 nm above the channel-gate dielectric interface 61 Figure 5.2 Process sequence showing key steps employed in the fabrication of strained-Si/SGOI

transistors The integration of SGOI substrate and in situ doped Si1-yCy S/D achieves high strain levels in the Si channel for drive current IDsat and mobility enhancement 62 Figure 5.3 SEM images of SiC:P in S/D (a) Presence of residues at sides of gate when

insufficiently dipped in HF prior to epitaxy, resulting in residues deposited (b)Plane view showing residues along gate edges (c) and (d) show tilted view of poor epitaxial quality resulting from excessive Cl2 etch during CDE (e) and (f) show residue free and smooth epitaxy was achieved when Cl2 etch time was reduced to an optimal duration 63 Figure 5.4 Transmission Electron microscopy (TEM) picture of a strained Si nMOSFET with

Si0.979C0.021:P S/D Isotropic recess etching of the S/D was done, resulting in some undercutting underneath the spacer This enables the lateral encroachment of the in situ doped Si0.979C0.021 S/D under the spacer Excellent surface morphology and crystalline quality of Si0.979C0.021 is achieved The inset shows a Scanning Electron Microscopy image of the same transistor 65 Figure 5.5 HRXRD rocking curve of the selective epitaxial grown SiC:P films Well-defined

fringes in the rocking curve indicate high integrity of the SiC:P crystal and smooth surface Our analysis confirmed that Csub = 2.1 atomic percent 65 Figure 5.6 Sheet resistance as a function of total carbon concentration Increasing the total

carbon concentration increases the sheet resistance of Si:C films Activation of phosphorus is degraded in films with higher Csub 66 Figure 5.7 Simulated channel stress in the horizontal direction Sxx (in MPa) for strained Si/SGOI

devices with Si1-yCy S/D The lateral tensile stress in the center of the channel is 1600 MPa for the transistor structure with an embedded Si1-yCy S/D, when Csub = 2.1 atomic percent Higher lateral stress is induced in the channel as Csub is increased 66 Figure 5.8 (a) Plot of ID-VD showing that higher Csub results in IDsat enhancement of up to 65%,

due to larger lattice mismatch between SiC:P S/D and the SGOI STL IDsat

enhancement of 45% is observed when Si0.983C0.017 is incorporated in the S/D A larger enhancement is observed when Csub = 2.1 atomic percent in the S/D, due to the enhanced lattice mismatch with the STL and larger strain gets imparted to the strained

Si channel, which increases the strain effects at the vertical heterojunction (b)Plot of

ID-VG for strained devices with SiC:P S/D and unstrained control devices 68 Figure 5.9 (a)Plot of IDsat-IOff illustrating significant drive current enhancement at constant off-

state condition At a fixed off-state leakage current of (100 nA/µm), 22% improvement in drive current is observed when comparing Si0.983C0.017 and Si0.979C0.021

S/D stressors being integrated in the S/D regions A linear fit was used to compare both devices (b)Significant Gm enhancement of 98% is demonstrated for strained n-FET with Si0.979C0.021:P S/D over unstrained control devices 69 Figure 5.10 At a given DIBL of 0.2V/V, significant IDsat enhancement of 61% is demonstrated for

strained n-FET with Si0.979C0.021:P S/D at comparable short channel effects 41% improvement in drive current is shown in strained n-FET with Si0.983C0.017:P S/D A linear fit was drawn to fit points belonging to the same wafer 69

Chapter 6

Figure 6.1 The lattice constant of Sn is 6.49Å while the lattice constant of Si is 5.43Å The lattice

of Sn is approximately 19.5% more than the lattice of Si, whereas the lattice of Ge is only 4% mismatched with Si 72 Figure 6.2 High resolution transmission electron microscopy pictures of a Si1-x-y-zGexSnyBz layer

on Si substrate after laser annealing (a) The sample was laser annealed using 5 laser pulses each with an energy intensity of 115 mJ cm-2 Defect clusters with a size of ~3

to 5 nm were observed (b) With a laser annealing condition of five 400 mJ cm-2pulses, the defect clusters were dissolved, and defect-free single crystalline SiGeSn was formed 73 Figure 6.3 (a) Rutherford backscattering and channeling spectra for the Sn implanted samples

Spectra plotted using (i) solid and (ii) dotted lines are the random and channeling spectra, respectively, for the as-implanted sample Lines (iii) and (iv) are the channeling spectra after annealing using 5 laser pulses each at an energy fluence of

115 mJ cm-2 and 400 mJ cm-2, respectively The reduction of the Sn peak (inset) after laser annealing at 400 mJ cm-2 for 5 pulses indicates enhanced Sn substitutionality Dependence of backscattering yield and substitutional incorporation of (b) Sn and Ge

on laser power are investigated Sn and Ge substitutionality improved, as the laser power was increased from 100 mJ cm-2 to 400 mJ cm-2 Subsequent increase in laser fluence resulted in significant Sn and Ge drive-in, and a reduction in the average concentration of Sn and Ge 75 Figure 6.4 (a) Raman spectra of Si0.75Ge0.25 implanted with Sn and B, followed by laser annealing

(L.A.) with 5 laser pulses The Raman shift by 5.3 cm-1 to the right was caused by substitutional incorporation of Sn in Si0.75Ge0.25, leading to increased in-plane compressive strain (b)Dependence of Si-Si Raman peak on laser energy density is investigated Increasing the laser energy density increases the compressive stress in the Si1-x-y-zGexSnyBz film due to increased Sn substitutionality 76 Figure 6.5 High resolution transmission electron microscopy pictures of a Ge1-xSnx layer on Ge/Si

substrate after laser annealing The samples were laser annealed using 10 laser pulses with an energy intensity of (a) 200 mJ cm-2 (b) 550 mJ cm-2 Misfit dislocations and stacking faults running parallel to the substrate surface are present in (a) while in (b), the defect clusters were dissolved, and defect-free crystalline GeSn was formed 79

Figure 6.6 Rutherford backscattering and channeling spectra for the Sn implanted sample

Spectra plotted using solid and dotted lines are the random and channeling spectra, respectively, for the as-implanted sample(i) and (ii) Lines (iii) and (iv) are the channeling spectra after annealing using 5 laser pulses each at an energy fluence of

400 mJ cm-2 and 550 mJ cm-2, respectively The reduction of the Sn peak (inset) after laser annealing at 400 mJ cm-2 for 5 pulses indicates enhanced Sn substitutionality

χmin for both the Sn and Ge signals deduced the substitutional incorporation of 68% Sn and 73% Ge 80 Figure 6.7(a) Raman spectra of Ge implanted with Sn, followed by laser annealing (L.A.) with 5

laser pulses It was also observed that the Ge1-xSnx/Ge layer peak position decreases in energy with increasing Sn concentration (b) Raman shift in wavenumber plotted with increasing Sn concentration It was observed that ωGeSn decreases linearly with Sn concentration A linear fit was used to arbitrarily fit the points correlating wavenumber shift to average Sn concentration 82 Figure 6.8 High resolution x-ray diffraction images of Ge1-xSnx /Ge The (004) diffraction peak

shifts are consistent with homogeneous diamond cubic Ge1-xSnx within the virtual crystal approximation The Ge and Ge1-xSnx peak widths widening effect may be attributed to the small film thickness and the misfit in the films resulted from the expected strain relaxation caused by the substrate lattice mismatch, as well as the possible compositional variation of the alloy film in the case of Ge1-xSnx 85 Figure 6.9 X-ray microdiffraction two dimensional reciprocal space map around (004) diffraction

spots of Ge1-xSnx on Ge heterostructure The axis x shows the angular position of the sample in degrees The axis y is marked in dimensionless units of λλλλ/2d where λλλλ is the wavelength of the radiation and d is the inter planar distance in the direction perpendicular to the sample surface 88 Figure 6.10 X-ray microdiffraction two dimensional reciprocal space map around (224)

diffraction spots of Ge1-xSnx on Ge heterostructure The presence of two different peaks indicates the existence of Si and GeSn/Ge crystal domain in the GeSn/Ge/Si buffer layer The stronger peak comes from the highly perfect strain relaxed Si domain, while the weaker and broader peak comes from GeSn on Ge 88 Figure 6.11 SIMs profile of Ge1-xSnx on Ge heterostructure, when implanted with a Sn dose of 8

××××1015

cm-2 and laser annealed at energies between 400mJ cm-2 to 650mJ cm-2 The characteristic flat profile of Sn in GeSn after laser annealing assures us of the uniform distribution of Sn 89

Chapter 7

Figure 7.1 Schematic shows the formation of SiGeSn S/D stressors by Sn implantation A lateral

compressive strain is induced in the channel for enhanced p-FET performance 90 Figure 7.2 SEM image of a device after laser annealing The presence of the hardmask and oxy-

nitride spacer served to shield the transistor gate from the laser irradiation damages Unnecessary exposure to laser irradiation at the gate could result in gate characteristic degradation and result in gate leakage issues, rendering poor gate control 91 Figure 7.3 SIMS profiles with various doses of Sn implant Homogenized laser pulse melted the

amorphous SiGeSn and the thermal energy reached the interface of the crystalline interface to produce a characteristic BOX-like profile 92 Figure 7.4 Device fabrication sequence, showing the insertion of a Sn implantation step and laser

amorphous-annealing step in a standard process flow 94 Figure 7.5 TEM image of a 50nm gate length transistor structure after Sn implantation and laser

irradiation 95 Figure 7.6 Optical micrographs show SiGeSn S/D prior to and after laser annealing Laser

annealing was used to restore the crystallinity in SiGeSn after Sn implantation Good crystallinity of the SiGeSn is recovered after laser annealing as shown in the FFT diffractogram Single crystalline structure is achieved 95 Figure 7.7 SIMS depth profiles of Sn and B after LA at energy densities of 380mJ cm-2 and

450mJ cm-2 Enhanced diffusion of B is suppressed and limited within the Sn profile

In the course of annealing and recrystallization, interstitials concentration reduces 96 Figure 7.8(a)Rutherford backscattering and channeling spectra for the Sn implanted sample Sn

and Ge substitutionality improved, as the laser power was increased from 300mJ cm-2

to 380 mJ cm-2 Subsequent increase in laser fluence resulted in significant Sn and Ge drive-in, and a reduction in the average concentration of Sn and Ge.(b) Sn substitutionality of up to 70% was achieved in Si0.75Ge0.25 97 Figure 7.9(a) Plot of ID-VG for a pair of closely-matched strained and control devices.(b) ID-VD

characteristics of strained p-FET with SiGeSn S/D regions at a gate length of 50 nm, showing significant drive current IDsat enhancement over the control p-FET 98 Figure 7.10 IDsat enhancement as a function of physical gate length LG Current enhancement

increases with smaller LG as stressors are brought into closer proximity to the channel 99

Figure 7.11 Comparison of transconductance Gm at the same gate overdrive illustrates an

improvement of 150% in strained SiGeSn S/D device over control device Higher transconductance improvement illustrates the benefits of introducing Sn in SiGe S/D 100 Figure 7.12 (a) Schematics illustrating selective epitaxial growth of SiGe layers on S/D regions of

p-FET structure (b) Sn implantation into the SiGe layers on the S/D regions for enhanced performance 101 Figure 7.13 (a) TEM image of a 80 nm gate length strained Sn implanted p-FET EDS analysis at

S/D region shows Ge content of approximately 25% across the entire S/D region.(b) High resolution TEM show excellent crystallinity in the S/D after Sn implantation and anneal 101 Figure 7.14 (a) ID-VD characteristics of SiGeSn S/D and control transistors for gate overdrives

|VG- VT| of 0 to 1.2 V in steps of 0.2 V The strained p-FET shows ~ 57% increase in

ID at a gate overdrive of 1.2 V (b)Significant ID enhancement at shorter gate lengths due to stressors brought closer to channel centre which leads to larger compressive strain in the channel 103 Figure 7.15 Plot of off-state leakage current Ioff and saturation drain current IDsat’ for strained

transistors with SiGeSn S/D, support the mobility improvement effects IDsat’ and Ioff

are both extracted at VG – VT’ = -1.2 V and VG – VT’ = 0.3 V, respectively VT’ is defined as the mean VT at a nominal gate length Strained p-FETs with a Sn dose of 8

×1015

cm-2 shows the largest IDsat’ gain of 54% for a given Ioff of 100nA/µm Lines are generated by linearly fitting each set of data points using a method of least squares 103 Figure 7.16 ID-VG show comparable short channel effects, DIBL and subthreshold swing between

SiGeSn S/D and control, allowing fair comparisons to be made regarding their current enhancements, and ensuring current enhancements are primarily contributed by strain effects 104 Figure 7.17 Plot of IDsat’ as a function of DIBL for control and strained SiGeSn S/D devices IDsat’

is extracted at DIBL= 50 mV/V and VG – VT’ = -1.2 V where VT’ is defined as the mean VT at a nominal gate length Very significant IDsat enhancement of 54% over control devices is obtained for strained p-FETs with SiGeSn S/D implanted with a Sn dose of 8 ×1015

cm-2 for a given DIBL 104

LISTS OF TABLES

Chapter 2

Table 2.1 All wafers were oxidized at 10500C for 200 minutes This was followed by various amounts of anneal conditions at 9000C according to the following conditions (below) for Wafers A-F 20

Chapter 7

Table 7.1 Tabulation of implant energy and longitudinal and lateral projections 92

LISTS OF SYMBOLS AD ABBREVIATIOS

Lists of Symbols

Csub Carbon Substitutionality

∈-Si Strained silicon

mh

*

Effective mass for hole

Snsub Tin Substitutionality

Tfinal Final Thickness of SGOI

Tinitial Initial Thickness of SOI

Lists of Abbreviations

However, with the progression of each technology node [2], device scaling alone becomes increasingly difficult to maintain The 2006 roadmap refers to devices with a physical gate length of 13 nm in size by the year 2013

One important metric for assessing the circuit performance is the time delay, which is given by the simple equation

time delay

D

DD d

In addition, other metrics like the dynamic power PActive and standby power PStandby are desired to be kept to a minimum Power consumed by CMOS circuitry is driven by PActive The equations are as given below

Active Power Consumption PActive = C.VDD2.f (1.2)

Standby Power Consumption PStandby = W.Ioff.VDD (1.3)

where W is the width , VDD is the supply voltage and Ioff is the off-state leakage current Nevertheless, CMOS technology still faces several fundamental scaling challenges as performance improvement does not necessarily commensurate with technology scaling In order to maintain the furious pace of innovation, tampering with the very architecture of the silicon crystals from which transistors are made is necessary In this thesis, various ways to improve the circuitry speed, by means of increase in electron mobility and drive current ID, will be explored as the power supply voltage is mainly dictated by power consumption and roadmap requirements

1.2 Background

New technology solutions are being explored in order to boost further circuit performance for the next logic generations The incorporation of new materials from the interconnect level (Cu, low-κ [3]), to gate stack (high-κ dielectrics [4]-[5], metal gate electrodes[6]-[9]), and even the substrate (Silicon-on-insulator (SOI)[11]-[13], Germanium (Ge) [14], Germanium-on-insulator (GOI) [15], Galium Arsenide (GaAs) Wafers[16]), are emerging as an essential way to continue to improve circuit performance

Channel strain engineering (“Virtual substrates”, Source/Drain stressors [17]-[19] and Strain Transfer Layers) further improve MOSFET drive currents by fundamentally altering the band structure of the channel and therefore enhance performance even at aggressively scaled channel lengths

As the gate length and gate dielectric thickness are reduced, the use of polysilicon as the gate material aggravates the problem of poly depletion [20], high gate resistance [21] and dopant penetration from the gate [6],[22]-[23] To alleviate these problems, some have suggested the use of metal as the gate material [6]-[9] This not only solves the problem of gate depletion and dopant penetration and also reduces the gate resistance By eliminating the effects of poly depletion, a higher equivalent oxide capacitance can be achieved This, in turn gives rise to an increase in drive current ID However, there are issues related to implementation of metal as the gate material of CMOS device and these include the choice of metal materials, new physics of metal gate dielectric interface and possible schemes of integrating metal gate material into the CMOS process

In line with the scaling of gate length, the gate dielectric thickness has to be reduced,

to increase gate oxide capacitance However, as the thickness of the gate oxide is reduced, gate leakage and power consumption of the MOS transistors will increase tremendously One solution would be the use of high-k dielectric in place of silicon dioxide as the gate dielectric This allows a physically thicker high-k dielectric to achieve the same or lower electrical thickness at a lower leakage current than silicon dioxide[4],[9].While state of the art gate stacks using Hf based dielectrics with Poly-Si and FUSI gates exhibit low leakage and relatively high channel mobilities, they do not

provide the critical benefit of the equivalent oxide thickness (EOT) scaling and low threshold voltages concomitantly[24] Challenges of using high-k include band misalignment to silicon which may alter the leakage current, film morphology, threshold voltage VT instability, consistent maintenance of high mobility charge carriers, formation and elimination of electrical defects in the film/interface, thermal stability and integration with a CMOS compatible manufacturing processes [25]

So far, the methods described help to improve circuitry speed by increasing the drive current ID As explained earlier, reduction in parasitic capacitance C also can help to achieve the same purpose of increasing circuitry speed One way to reduce C is by using silicon-on-insulator (SOI) substrates [11]-[13] instead of the conventional bulk silicon substrate By all accounts, SOI offers speed improvement of between 0% [36] and 30% [37] and power improvement (for the same speed) between 5% and 50% The advantage

of SOI stems from the reduction of junction capacitance (large interconnect capacitances should be drive by sufficiently wide transistors having significant junction capacitances) and the absence of the classical body bias effect in series connected devices eg In NAND and NOR gates On the minus side, the floating body of an SOI device can result in threshold voltage dependence on terminal voltages and result in VT variations, which cause degradation in speed and leakage tradeoff in circuit performance [38] In addition, the high cost of such SOI substrates can be the major deterring factor in its implementation into present CMOS device manufacturing

In today’s context of moving beyond device scaling, a shift to strained Si channel instead of the conventional bulk Si channel is necessary [26] This change is a good

initiative as it is a direct replacement for bulk Si technology of using Si/SiGe epitaxial layers That is, the strained silicon technology can be integrated directly into current designs without any major design changes or capital investments For many years, channel strain engineering [27]-[35] has also been actively pursued to improve drive current ID Introduction of appropriate strain, in the channel of MOSFET devices, causes an increase

in carrier mobility as a result of smaller carrier effective mass and reduction in scattering

To date, there can be many different ways to introduce strain to the channel of transistors The next section will give a more detailed description of the physics behind strain engineering and different ways to strain Si and SiGe devices for integration with MOSFET devices

1.3 Strain engineering for mobility enhancement

The most important parameter of a semiconductor material is the carrier mobility µ, which denotes the direct relationship between the average carrier velocity υ and an external electric field ξ

qτ

where q is the electronic charge, 1/τ is the sum of all reciprocal scattering times associated with the various scattering mechanisms and m∗ is the conductivity effective mass Thus

Tensile strain induces modification to the conduction and valence energy bands which reduces inter-valley scattering and lowers carrier effective masses, leading to an increase in carrier mobility Strain enhances the mobility by reducing the conductivity effective mass and/or the scattering rate For electrons, both mass and scattering changes are generally accepted as important parameters for mobility enhancement [39] However, for holes, only mass change due to band warping and repopulation [40] plays a significant role at today’s manufacturable (<1 GPa) stress level since strain induced valence band splitting is smaller than that for the conduction band Furthermore, though there has been much focus on reduced in-plane mass to increase mobility, increasing the out-of-plane mass for electrons and holes is now understood to be equally important for maintaining the mobility enhancements at high vertical fields

1.4 Electron transport in Strained Si n-FETs

Figure 1.1 shows the valence band structure of unstrained Si and Si under biaxial tensile strain The valence band of Si is composed of the heavy hole, light hole and spin-orbit sub bands In unstrained Si, the heavy hole and light hole subbands are degenerate at the Г point As a result, holes in unstrained Si experience a higher rate of intervalley scattering, which is the primary limitation on hole mobility in bulk Si However, under biaxial tension, the degeneracy of the valleys is broken [Fig 1.1(b)], and the six-fold degeneracy

at conduction band minima is lifted by lowering the two-fold valleys perpendicular to the growth plane (∆2) with respect to the four-fold in-plane valleys (∆4) by ~67 meV per 10%

Ge in the buffer [41] The lowering of the subband leads to reduced intervalley scattering The conduction band is thus split into two sets of energy ladders, and the rate of

intervalley phonon scattering is reduced Electrons in strained Si (∈-Si) occupy the ∆2 valleys where they experience the transverse effective mass mt = 0.19mo for in-plane transport, as opposed to the mixed conductivity mass expressed above In the out of plane direction, the electrons in the ∆2 have mz = ml = 0.916mo The large value of mz means that the effective width of the electron wave function in ∈-Si inversion layers is smaller than

in bulk Si

As mentioned in the earlier section, for electron transport in bulk Si at room temperature, the conduction band is comprised of six degenerate valleys as shown in Figure 1.2 The six-fold degenerate conduction band at ∆ valley along the [100] direction

of the Brillouin zone has equal electron population in each valley The constant energy surface is ellipsoidal with the longitudinal effective mass, ml=0.916mo, and transverse effective mass being much lower, mt=0.19mo, with free electron mass denoted by mo The effective mass of each ellipsoidal lobe is highly anisotropic

The contributions of the six degenerate valleys can be added to result in a single expression known as the conductivity effective mass of electrons m*

1

213

Figure 1.1 Valence band structure of (a) unstrained Si and (b) tensile strained Si on Si 1-x Ge x Biaxial tensile strain lowers the energy of the heavy hole and spin-orbit subbands relative to the light hole sub band and modifies the shape of the sub bands

Figure 1.2 Schematic representation of the constant energy ellipses for (a) unstrained Si and (b) tensily strained Si resting on SiGe[28]

Figure 1.3 Conduction band splitting and sub-band energies lineups of Si under biaxial tensile strain [28]

Treating the transistor channel as a 2 dimensional electron gas (2DEG) the effective masses are grouped into two groups of sub-bands The group corresponds to the four

ellipsoids in the perpendicular directions or in plane ellipsoids The other group corresponds to the two ellipsoids along the direction or out of plane ellipsoids Hence electron population preferentially occupies the lower energy ∆2 valley where the effective in-plane transport mass is significantly reduced due to the lower transverse mass mt in parallel to the Si/SiO2 interface The strain-induced band splitting between subband energies in the ∆2 and ∆4 valleys (Figure 1.3) has also been reported to suppress inter-valley phonon scattering between ∆2 and ∆4 valleys and lead to the enhanced electron mobility [42] Like in the case of biaxial tensile strain, uniaxial tensile strain, induced along the lateral or source-to-drain direction of the transistor has a similar effect on the conduction band and electrical properties of Si [43] Many types of stress tend to increase the electron mobility via increased population in ∆2 valley

1.5 Global and Local Strain Effects

Various fabrication processes can be exploited to induce strain in the transistor channel The channels of the MOSFET can be strained by various methods to obtain an improvement in mobility and drive current There are two ways of introducing strain and can be categorized into, global strain [27] - [29] and local strain [30] - [35] techniques

The global strain technique [27] - [29] generally makes use of an epitaxially grown strained layer on the substrate This technique begins with a normal bulk Si wafer It involves a different material, with a mismatch lattice constant like silicon germanium (SiGe), directly beneath the thin Si channel The SiGe layer is grown on the Si wafer using an epitaxial deposition technique The growth of the Si1-xGex layer on the Si

the “virtual substrate” The strain induced is biaxial in nature, and is already inherent in the substrate right from the beginning of the CMOS process flow

Figure 1.4 Si has a smaller lattice constant(5.431Å) than Ge (5.658Å) By Vegard’s law the lattice constant

of Si 1-x Ge x will have a larger lattice constant than Si When Si is epitaxially grown on relaxed Si 1-x Ge x , the

Si layer will be stretched biaxially Si having smaller lattice constant will develop a tensile strain

Figure 1.5 Ge has a larger lattice constant (5.658Å) than Si (5.431Å) By Vegard’s law the lattice constant

of Si 1-x Ge x will have a smaller lattice constant than Ge When Ge is epitaxially grown on relaxed Si 1-x Ge x , the germanium layer will be squeezed biaxially Ge having larger lattice constant will develop a compressive strain

Figure 1.4 illustrates how a mismatch material, like SiGe, can induce a biaxial tensile strain in the Si layer above it Figure 1.5 shows how Ge on SiGe can induce a biaxial

compressive strain in the overlying Ge Germanium (Ge) has a larger lattice constant (5.658Å) than Si (5.431Å) By Vegard’s law, the lattice constant of Si1-xGex is a linear interpolation between the lattice constant of Si and Ge

Figure 1.6 Different types of globally strained Si substrate wafers (a) strained Si / relaxed SiGe on Si substrate (b) strained Si/ relaxed SiGe – on – insulator (SGOI) (c) strained Si– insulator (sSOI) Each layer

is grown at slow strain rate allowing nucleation rate of dislocations to be minimized Prexisting threads can

be used to relax the strain in the graded layers, preventing new dislocations from nucleating

Figure 1.6 shows the different types of globally strained Si substrate wafers formed using the global strain technique To avoid defects formation as mentioned earlier, the Si

Strained Si Strained Si

Relaxed Si1-xGex

Graded Si1-xGex

Relaxed Si1-xGex Graded Si1-xGex BOX

Si Substrate

BOX Strained Si

xGex, deposited layer has the Ge content graded from 0% up to the desired Si1-xGex concentration The grading of the Si1-xGex, layer allows for the deposited layer to be relaxed After this the surface of the wafer is planarized using a CMP process Finally a thin layer of Si is regrown epitaxially on the wafer Since the lattice constant of Ge is larger than that of Si the resulting layer is under a tensile strain This however is restricted

to layer thicknesses less than that of a critical thickness of Si, otherwise, Si will relax

Figure 1.6 (a) and (b) make use of a graded Si1-xGex, layer to form a low-defect density relaxed Si1-xGex, layer [39] - [45] and a buffer relaxed Si1-xGex, layer before a biaxial tensile strained Si layer is epitaxially grown The strained SOI substrate in Figure 1.6 (c)

is formed using (a) and SiGe is used in interim sSOI fabrication

Once the requisite strain is established in the Si layer, the strained layer is then transferred onto the BOX by layer splitting and bonding and SiGe is removed by selective etchback [46]

Since the local strain approach turned out to be more promising for industrial applications, the first strain technologies used in high volume production was developed

on the basis of uniaxial process induced stress For source and drain (S/D) stressors, by performing a recess etch in the source and drain regions, and selective epitaxial deposition

of a larger lattice material, compressive strain can be introduced into the channel

This provides a lattice-mismatched structure at the source and drain ends of the device channel forcing the channel into a compressive strain state Starting from the 90nm technology node, companies introduced the selective epitaxial growth technique to transfer uniaxial compressive stress into the Si channel by growing a local epitaxial film