Sơ đồ khối Mainboard G31 MG

route the lines in parallel 10 mils width 7 mils spacing to low speed signals 14mils spacing to high speed signals max.. 1200mils placed near pin D23, within 500 mils 4 mils width, 10 mi

Trang 2

SATA Connector 3

PCI Express x 16

HDA Codec Serial ATA ⒑

Reltek USB2.0 Port 7

Serial & Parallel

VGA Connector

Cedar Mill, Presler , Conroe & Allendale LGA775 Processor

USB2.0 Port 1

Header

USB2.0 Port 2

Controller Link

Trang 3

RSMRST circuit

PWRGD_3V

ACZ_RST#

Translation Circuitry

PCIe LAN

RST#

TPM

Trang 4

PCI Express/DMI 100 MHz Diff Pair

DOT 96 MHz Diff Pair

PCI Express x16 Gfx

USB/SIO 48 MHz PCI Express/DMI 100 MHz Diff Pair PCI Express 100 MHz Diff Pair

ICH 33 MHz MCH 200/266/333 MHz Diff Pair

REF 14 MHz

SATA 100 MHz Diff Pair

GMCH Broadwater CPU 200/266/333 MHz Diff Pair

PCI Express 100 Mhz Diff Pair

PCI Slot 1 PCI 33 MHz

SPI SPI Clock

PCI Slot 2 PCI 33 MHz

Trang 5

Linear 1.25V

to 1.05V V_1P05V_ICH 2A

-12V Icc(Max)=0.1A -12V

3.3VSB Icc(Max)=0.375A(wake) Icc(Max)=0.02A(no wake)

+5V DUAL=5A(S0, S1) +5V DUAL=20mA(S3)

3.3V

LDO 12V

to 5V

HDA Codec

FSB_Vtt 1.2V FSB Vtt Icc(Max)=1.3A

Single Phase Switch 5V to 1.8V Ivdd(Max)=TBD LDO 1.8V to 0.9V Ivterm(Max)=1.2A

3.3V Icc(Max)=50mA

*1.25V (DMI&PCIe) VCCA_EXP 2.5A Broadwater GMCH

3.3SBV Icc(Max)=50mA(S0)

1.5V VCCGLAN1_5 74mA

DDR2 Channel A

5V

CK505

Vccp (CPU Vcore) Voltage=1.15~1.5V Icc(Max)=125A 3-Phases Swithing

5V_STBY to 3.3SB 1.5A

VRD 11 Switching Three Phase

Linear 1.8V

to 1.2V 6A

1.2V FSB

3.3V VccCL3_3 12mA 3.3V VccSUS3_3 141mA 3.3V VccLAN (10/100) 12mA 3.3V VccSUSHDA 4mA 3.3V VCC3_3 310mA

3.3V VccGLAN3_3 1mA 3.3V VccHDA 4mA

RTC=5uA RTC

3.3SBV Icc(Max)=38mA(S3)

FWH 3.3V=107mA(S0, S1)

PCI Per Slot (X2)

12V Icc(Max)=0.5A

5V Icc(Max)=5A

3.3V Icc(Max)=7.6A

PCI Express X16 slot (1)

+12V=5.5A

+3.3V=3A 3.3V VCCA_DAC 70mA

PS2 +5V DUAL=345mA(S0, S1) +5V DUAL=2mA(S3)

PCI Express X1 Per slot (1)

BJT

1.25V VCCDMI 40mA

Linear 1.8V

to 1.5V V_1P5V_ICH 2.2A

Vdd (Core)=1.8V

Ivdd(Max)=TBD(per channel)

12V

Trang 6

VIDPWRGD +3D3V_DUAL

+5V_SYS

PS_ONJ

VTT_VR

Vcc_PWRGD VTT_VR

VIDPWRGD

+5V_SYS

VRM_OUTEN VTT_DDR

VIDPWRGD

S0->S5

+3D3V_SYS +12V_SYS

VRM_OUTEN

PS_ONJ VTT_VR

1ms to 10ms

+1D8V_STR +1D8V_STR

Trang 7

ICS_FSBSEL0

200M_N_CPU96M_P_GMCH

3D3V_CLK_SATA_25M

200M_N_GMCH200M_P_GMCHSATA_100M_N_ICH

PE_100M_N_GMCHICS_FSBSEL2

PE_100M_N_ICH3D3V_CLK_48M

VRMPWRGDDOC0

VRMPWRGD

FSBSEL1_1ICS_FSBSEL1

15CK_96M_N_GMCH

SMB_CLK_MAIN 19,21,28,35SMB_DATA_MAIN 19,21,28,35

CK_SATA_100M_N_ICH 25CK_SATA_100M_P_ICH 25

CK_PE_100M_N_GMCH 15CK_PE_100M_P_GMCH 15CK_14M_ICH24

CK_PE_100M_P_ICH 24

FSBSEL0 13,15FSBSEL1 13FSBSEL2 13,15

CK_PE_100M_P_16PORT22CK_PE_100M_N_16PORT22

CK_PE_100M_P_LAN31CK_PE_100M_N_LAN31

266MHz(1066) 0

0 1

0 1 0 133MHz(533)

FS_AFS_BFS_C

1 1 0 400MHz(1600)

Inset FSB1600 CPU run 1333 FSB

X2

XTAL-14.318MHzX2

+/-5%

Dummy

R9034.7K

+/-5%

*R888.2K

+/-5%

Reserved

*R744.7K

+/-5%

Reserved

CP5 X_COPPERCP5 X_COPPER

Trang 8

PS_ONJ 34

ICH_SYS_RSTJ 7,13,24

PWRG_ATX 12,34

HDD_LEDJ 25

SPKR 24,32 SIO_BEEP 34

GREEN_DET 24

Power/MISC Connectors

SPEAKER HEADER

GND 5 6 Power button

NC 9 10 Key Reset button 7 8 Power HD_LED+ 1 2 Power

Front Panel Switch/LED

HD_LED- 3 4 Power LED(Green) Change to 5% or not

Q39

MMBT3904-7-F Q39

MMBT3904-7-F B

PWR_BU

Header_1X2 PWR_BU

Header_1X2 1

*

C540 0.1uF

16V, Y5V, +80%/-20%

Dummy

*

C540 0.1uF

16V, Y5V, +80%/-20%

Dummy

*

C503 220pF Dummy

*

C503 220pF Dummy

*

C264 0.1uF

16V, Y5V, +80%/-20%

Dummy

*

C264 0.1uF

50V, NPO, +/-5%

Dummy

*

C491 220pF

50V, NPO, +/-5%

Dummy

* R357 301

+/-1%

* R357 301

+/-1%

*

C466 0.1uF

16V, Y5V, +80%/-20%

*

C466 0.1uF

16V, Y5V, +80%/-20%

*

C467 0.1uF

16V, Y5V, +80%/-20%

Dummy

*

C467 0.1uF

16V, Y5V, +80%/-20%

Dummy

*

C541 0.1uF

16V, Y5V, +80%/-20%

Dummy

*

C541 0.1uF

16V, Y5V, +80%/-20%

Dummy

*

C297 0.1uF

16V, Y5V, +80%/-20%

Dummy

D33

SD103AW D33

SD103AW

* R356 301

+/-1%

* R356 301

+/-1%

*

C460 220pF Dummy

*

C460 220pF Dummy

16V, Y5V, +80%/-20% Dummy

*

C187 0.1uF

16V, Y5V, +80%/-20% Dummy

* C463 0.1uF

16V, Y5V, +80%/-20% Dummy

* C463 0.1uF

16V, Y5V, +80%/-20% Dummy

* R360 4.7K

+/-5%

* R360 4.7K

50V, NPO, +/-5%

Dummy

*

C459 220pF

50V, NPO, +/-5%

Dummy

Q22 MMBT3904-7-F Q22 MMBT3904-7-F B

*

C465 0.1uF

16V, Y5V, +80%/-20%

*

C465 0.1uF

* R372 8.2K

+/-5%

* R372 8.2K

16V, Y5V, +80%/-20%

Dummy

*

C469 0.1uF

16V, Y5V, +80%/-20%

Dummy

*

C516 10nF

25V, X7R, +/-10%

*

C516 10nF

25V, X7R, +/-10%

BUZZER BUZ

Buzzer

Dummy BUZZER BUZ

16V, Y5V, +80%/-20%

*

C299 0.1uF

16V, Y5V, +80%/-20%

* R361 4.7K

+/-5%

* R361 4.7K

Header_2X5_K10 X FP1

Header_2X5_K10

3

9 6

BAT54C 2 1 3

PWR1

Header_2x12 PWR1

16V, Y5V, +80%/-20%

Dummy

*

C332 0.1uF

16V, Y5V, +80%/-20%

Dummy

* C430 0.1uF

16V, X7R, +/-10%

* C430 0.1uF

* R367 4.7K

+/-5%

* R367 4.7K

+/-5%

* C468 0.1uF

16V, X7R, +/-10%

* C468 0.1uF

16V, X7R, +/-10%

Trang 9

PHASE1

SSIMON

LG2RGND

HG2

ISEN2PHASE2

ISEN1PHASE1

VCCP5V_SYS

5V_SYS

FSB_VTT

CURRENT SENSE

5V_SYS5V_SYS

PSI function select

0: PSI function CPU saving mode

1: no PSI function CPU saving mode

PSI function circuit

+/-5%

R682.2

R1676.2k Ohm+/-1%

+/-5%

Dummy

R15922K

+/-5%

Dummy1

+/-1%*

R15410K

G

R792.2

+/-5%

R792.2

R1646.2k Ohm+/-1%

G

C1051nF

50V, X7R, +/-10%

C1051nF

G

*R1460

+/-5%

*R1460

G

Q18AOD472Q18AOD472

+/-1%

*

R171100KOhm

+/-1%

PWR2

Header_2X2PWR2

+/-1%

*R1531K

50V, X7R, +/-10%

C1041nF

50V, X7R, +/-10%

C1681nF

+/-5%

R6490

+/-5%

Dummy

U7

ISL6622CBZU7

R1576.2k Ohm+/-1%

+/-5%

R932.2

Trang 10

OUTPUT CAP

Id(N MOS) max= 6.9A Id(P MOS) max= -5A

5V_USB

close the rear usb

close the front usb

2 3 4 5 6 7 8

16V, Y5V, +80%/-20%

Dummy

*

C713 0.1uF

16V, Y5V, +80%/-20%

Dummy

Q35 APM2054N

Dummy

Q35 APM2054N

AOD452 G

* R263 20K

+/-1%

* R263 20K

+/-1%

* R254 1K

+/-5%

* R254 1K

+/-5%

* R320 0

+/-5%

Dummy

* R320 0

2N7002 G

* R253 4.12K

Q29 MMBT3904-7-F Q29 MMBT3904-7-F B

* C295 2.2uF

6.3V, Y5V, +80%/-20%

* C295 2.2uF

6.3V, Y5V, +80%/-20%

Trang 11

Pull FB trace out after Cout R638,R658 must less than 1k

Can change to 0402 or not

Need to Check Change to Dummy

Need to change to RUBYCON 16MBZ470MEFC8X11.5

Dummy

Q27AOD452

DummyG

G

D18LS4148-FD18LS4148-F

+/-5%

*

R9110

+/-5%

Q14MMBT3904-7-F

+/-1%

R2691.2KOhm

+/-1%

CP11

X_COPPERCP11

X_COPPER

R1742.2

+/-5%

R1742.2

+/-5%

R1832.2

+/-5%

*R2711.02KOhm

+/-1%

*R2711.02KOhm

*

C345

0.1uF

16V, Y5V, +80%/-20%Dummy

U18

LM358U18

CA

+80/-20%

*C2824.7uF

R1024.7K+/-5%

G

*R2722.2KOhm

+/-1%

*R2722.2KOhm

1

Q36AOD452Q36AOD452

+/-5%

R862.2

+/-5%

D21LS4148-FD21LS4148-F

CA

*

C424

0.1uF

16V, Y5V, +80%/-20%Dummy

Trang 12

PWRG_ATX

PWOK_1

5V_DUAL12V_SYS

5V_DUAL

12V_SYS

5V_DUAL5V_SB

DDR_VOL_1

34

PWRG_ATX8,34

Pull FB trace out after Cout R638,R658 must less than 1k

Rocset

1.8V Voltage 1.8V Power requires

close to Q61 Drain

Max output current = 3A

Vout=Vref(1+R2/R1)+IadjR2 R1 is Up Resistor.

Iadj=50uA Vref=1.25V

915 series failure issue

+/-5%

R3742.2

+/-5%

Q38AOD472Q38AOD472

G

*R351499

+/-1%

*R351499

BAT54C

*R371100KOhm

+/-1%

*R371100KOhm

+/-1%

Q45MMBT3904-7-FQ45MMBT3904-7-F

+/-5%

R3692.2

+/-5%

*R3621K

+/-1%

*R370100KOhm

+/-1%

Q44MMBT3904-7-FQ44MMBT3904-7-F

+/-5%

*R3684.7K

G

Q412N7002Q412N7002

+/-1%

*R350301

BAT54C

R3451.02KOhm

+/-1%

R3451.02KOhm

+/-1%

Q47AOD452Q47AOD452

Trang 13

HAJ31

HAJ11

HAJ15

HAJ27HAJ21

HAJ22

HAJ10HAJ4

HAJ17

HAJ9

HAJ29

TP_DPJ0TP_DPJ3HGTLREF_0

TP_MCERRJTP_BINITJHIERRJ

TP_APJ0HBR0JTESTHI_8TESTHI_10

HREQJ0

HREQJ4HDJ[63 0]

HCOMP1

HBR0J

TESTHI_8TESTHI_10

HTMS

HBPM5J

FSBSEL2HBPM3JHTCK

HBPM4JHTRSTJ

FSBSEL0HBPM2J

HTDOHTDI

HBPM0J

VTT_OUT_RIGHT

HCOMP3VID4

HCOMP1

PROCHOTJVID3

VID0

HCOMP0

TESTHI_13VID1

TESTHI_2_7

VID6

HCOMP2VCC_PLL

CPU_BOOT

VID1VID3

TESTHI_2_7TESTHI_0

MS_ID0HGTLREF_1

TESTHI_1TESTHI_11TESTHI_0

HDJ43

HDJ16

HDJ51

HDJ61HDJ57

HDJ56HDJ14

HDJ13

HDJ48

HDJ54

HDJ63HDJ19

HDJ35

HDJ24

HDJ49HDJ44

TP_CPU_AA2TP_CPU_V2

PROCHOTJ

H_TEST

FORCEPHJTESTHI_12

HGTLREF_1

HGTLREF_0

TP_CPU_G1HBPM0J

HTDIHTMSHBPM3J

HTDO

HTCKHTRSTJ

VCC_PLL

VID2VID0

VTT_OUT_RIGHT

FSB_VTT

VTT_OUT_RIGHTVTT_OUT_RIGHT

VTT_OUT_LEFT

VTT_OUT_RIGHT1D5V_CORE

VTT_OUT_LEFT

VTT_OUT_RIGHT VTT_OUT_LEFTVTT_OUT_LEFT

HADSJ 15HBNRJ 15HITJ 15

INITJ 25

HBPRIJ 15HDBSYJ 15HDRDYJ 15HITMJ 15HLOCKJ 15HTRDYJ 15HDEFERJ15

HBR0J 15HADSTBJ0

15

HADSTBJ115

HREQJ[4 0]

15

SMIJ25

STPCLKJ25

A20MJ25INTR25NMI25FERRJ25IGNNEJ25

VID09,34VID19,34VID29,34VID39,34VID49,34VID59,34

CK_200M_P_CPU7CK_200M_N_CPU7

HVCCA14HVSSA14HVCCIOPLL14

THERMDA34THERMDC34

THERMTRIPJ25CPU_PWRG 24HDJ[63 0] 15

HDSTBNJ2 15HDSTBPJ2 15HDBIJ2 15

ICH_SYS_RSTJ7,8,24

FSBSEL07,15FSBSEL17FSBSEL27,15

VCC_SENSE9VSS_SENSE9MCH_GTLREF_CPU 15

VID69,34VID79,34

VTT_PWRGD 10ICH_THRM_UP24,34

TP_CPU_G1 14

TESTHI_13 25

PECI34

7 mils spacing to low speed signals

14mils spacing to high speed signals

max 1200mils

Place at CPU end of route

Place BPM termination near CPU

MSID0: NC = 2005 Mainstream / Value, 2006 65W FMB Vss = 2005 Performance FMBMSID1: Vss = 2005 Performance,2005 Mainstream/Value,2006 65W FMB

THERMDA/THERMDC

1 width=10 mils, spacing=10 mils

2 route the lines in parallel

10 mils width

7 mils spacing to low speed signals

14mils spacing to high speed signals

max 1200mils

placed near pin D23, within 500 mils

4 mils width, 10 mils spacing

Stuff to enable Thermal event

reserve for Kentsfield CPU support

In Design Guide is NC

GTLREF voltage should be 0.63*VTT

12 mils width, 15 mils spacingdivider should be within 1.5" of the GTLREF pin0.22nF caps should be placed near CPU pin

51 Ohm

+/-5%

Dummy

*R211

Trang 14

HVCCA 13

HVSSA 13

LGA775-2

PLL Supply Filter

Notes:

1 Cap should be within 1.5" mils of the VCCA and VSSA pins

2 VCCA route should be parallel and next to VSSA route to minimize loop area

3 VCCIOPLL route should be parallel and next to VSSA route

to minimize loop area

3 Min 12 mils trace from the filter to the processor pins

4 The inductors should be close to the cap.

10 mils width

7 mils spacing to low speed signals 14mils spacing to high speed signals max 1200mils

15 mils width

7 mils spacing to low speed signals 14mils spacing to high speed signals max 1200mils

+/-5%

R106 0

Socket-IntelPrescottCPU

5 OF 7 U11E

6 OF 7 U11F

7 OF 7 U11G

Trang 15

HDJ42

HDJ46

HDJ50HDJ53

GMCH_EXP_SLR

VSYNC_P

DDCA_DATADDCA_CLK

EXP_TXP14EXP_TXN12

EXP_TXN15EXP_TXN13EXP_TXP8EXP_TXN4EXP_TXN0

DMI_RXP0EXP_RXN12EXP_RXP10EXP_RXP9EXP_RXP7

EXP_RXP15

EXP_RXN7

EXP_RXP5

EXP_TXP6EXP_TXN3

EXP_RXP14

EXP_RXP3

EXP_TXP7EXP_TXP5EXP_RXP2

EXP_TXP9

EXP_TXP3EXP_TXN1

DMI_RXN2

EXP_RXN5

EXP_TXP0

EXP_RXN8EXP_RXN1

EXP_TXP10EXP_TXN8EXP_TXN5

DMI_RXN0

EXP_TXP11

DMI_RXP1EXP_RXP12

EXP_RXP6EXP_RXN3EXP_RXP0

CK_PE_100M_N_GMCHDMI_RXP2

EXP_RXN11

EXP_TXP12EXP_TXN2

CK_PE_100M_P_GMCHEXP_RXN15

EXP_RXP8

DMI_RXN3DMI_RXN1EXP_RXN9

EXP_RXN2EXP_RXP1

EXP_RXN10

DMI_TXP0DMI_TXN1DMI_TXP3

CK_96M_N_GMCH

ICH_PLTRSTJPWRGD_3V

GMCH_EXP_COMP

GMCH_EXP_EN_HDRTP_ALLZTEST

REFSET

FSBSEL1_1GMCH_EXP_EN_HDR

HSCOMPJ

HAJ33

CL_VREF_MCHCL_RST

TP_MCH_F13

TP_MCH_DET_NPLTRSTJ

1D25V_MCH

3D3V_SYS1D25V_MCH

SDVO_CTRLCLK22

DMI_RXP024

CK_PE_100M_N_GMCH7

DMI_RXP224DMI_RXN024

CK_PE_100M_P_GMCH7SDVO_CTRLDATA22

DMI_RXN224DMI_RXP124

DMI_RXN324

DDCA_DATA 23DDCA_CLK 23EXP_RXN5

22EXP_RXP622

EXP_RXP922

EXP_RXP522

EXP_RXN1122

EXP_RXN222

EXP_RXN622EXP_RXN422

EXP_RXP1422

EXP_RXP722

EXP_RXN122

EXP_RXP822

EXP_RXN322

EXP_RXP122

EXP_RXN722

EXP_RXP022

EXP_RXP1022

EXP_RXP1522

EXP_RXN1022

EXP_RXN1422EXP_RXP1322

EXP_RXN922EXP_RXN822

EXP_RXP1222EXP_RXN1222EXP_RXP1122

EXP_RXN1322

EXP_RXP322

EXP_RXN022

EXP_RXN1522

EXP_RXP422EXP_RXP222

DMI_TXP1 24DMI_TXP2 24DMI_TXN3 24DMI_TXN2 24DMI_TXP0 24DMI_TXN1 24DMI_TXP3 24DMI_TXN0 24

EXP_TXN9 22EXP_TXP9 22

EXP_TXN11 22

EXP_TXP6 22EXP_TXP4 22EXP_TXN5 22

EXP_TXP0 22EXP_TXP1 22

EXP_TXP12 22

EXP_TXN0 22

EXP_TXP10 22EXP_TXN10 22

EXP_TXP5 22

EXP_TXP7 22

EXP_TXP11 22EXP_TXP8 22

EXP_TXP3 22EXP_TXN2 22EXP_TXN3 22EXP_TXP2 22

EXP_TXN6 22EXP_TXN4 22EXP_TXN1 22

EXP_TXN8 22EXP_TXN7 22

EXP_TXP14 22EXP_TXN13 22EXP_TXP15 22EXP_TXN14 22EXP_TXP13 22

EXP_TXN15 22EXP_TXN12 22

CK_96M_N_GMCH 7

PLTRSTJ 24,28,34ICH_SYNCJ 24

GMCH_EXP_EN_HDR22

FSBSEL07,13FSBSEL1_17FSBSEL27,13

300 mils

width 10 mils, spacing 6 mils at breakout

10 mils after that

Placed both Resistors close to GMCHWithin 750 milsW=4 mils, S=10 mils from GMCH to connector

placed close to GMCH within 500 mils

4 mils width

6 mils spacing to static signals

12 mils spacing to toppling signals

ATX: 1

GTLREF voltage should be 0.63*VTT = 0.75V

divider should be within 1.5" of the GTLREF pin

220pF caps should be placed near MCH pin

place series resistor as close to divider

Controller Link Routing

1 width=4 mils, Spacing=7 mils

2 CL_CLK and CL_DATA should be length matched to within 100 mils

R200,R201,R205,R208,R209,R210 USE 0 OHM FOR 946PL

HSWING voltage should be 0.25*FSB_VTT

max 3 inches long

Resistor and Capacitor

next to each other

4 mils width, 6 mils spacing in the breakout

4 mils width, 14 mils spacing after the breakoutmax 750 mils

routed on a single layer and matched within 50mils

10 mils width, 7 mils spacingmax 500 mils

5 on 5 mils in breakout, max 250 mils

COMP SIGNAL TERMINATION

Place close to VREF Pin 0.349V

min 4 mils width

+/ -1%

*R140150

+/-1%

*R189392

+/-1%

*R139150

+/ -1%

*R139150

+/ -1%

*R138150

+/-5%

* R1361K

+/-5%

TP9TP7

+/-1%

R127 49.9

+/-1% *R127 49.9

+/-1%

*R1921K

+/-1%

TP6TP13

+/-5%

*R1181K

+/-1%

R13210

+/-1%

*R16924.9

+/-1%

Trang 16

M_MAA_A12M_MAA_A9

M_MAA_A13M_MAA_A10M_MAA_A3M_MAA_A0

M_MAA_A4M_MAA_A1

M_BS_A1

M_ODT_A0M_SCKE_A1

M_ODT_A1M_SCKE_A0

M_DATA_A60M_DATA_A57

M_DATA_A49M_DATA_A47M_DATA_A44M_DATA_A29

M_DATA_A50

M_DATA_A61

M_DATA_A24

M_DATA_A58

M_DATA_A62

M_DATA_A25

M_DATA_A59

M_DATA_A18

M_DATA_A36

M_DATA_A20

M_DQM_A7

M_DQM_A3

M_DQM_A5

M_DQM_A6M_DQM_A4

M_DATA_A14

M_DATA_A1

M_DATA_A5

M_DATA_A13M_DATA_A0

M_DATA_A15

M_DATA_A7

M_DATA_A11M_DATA_A2

M_DATA_A12M_DATA_A4

M_DATA_A10M_DATA_A6

M_DATA_A9M_DQM_A0

M_DQM_A2M_DQM_A1

M_DQS_A2

M_DQS_A5M_DQS_A0

M_DQS_AJ6M_DQS_AJ5M_DQS_AJ3M_DQS_A1

M_DQS_A6M_DQS_AJ1

M_DQS_A7M_DQS_A4

M_DQS_AJ7

M_DQS_AJ0

M_DQS_AJ4M_DQS_A3M_DQS_AJ2

M_DQM_B6M_DQM_B4

M_DQS_BJ2M_DQS_BJ1M_MAA_B4

M_DQM_B1M_MAA_B7

M_DQS_B3M_BS_B0

M_DQS_BJ5

M_DQS_B1

M_DQS_BJ4M_DQS_B4

M_DQM_B0M_MAA_B3

M_MAA_B11M_MAA_B2

M_DQS_BJ3

M_MAA_B12M_MAA_B6M_MAA_B1

M_DQS_BJ6

M_ODT_B1M_BS_B1M_MAA_B8

M_DQS_B5

M_DQS_B2

M_SCKE_B1

M_DQS_B7DDR_GMCH_VREF

M_SCKE_B0M_BS_B2

M_DQM_B3

M_DQS_BJ7M_DQS_B6

M_MAA_B9

M_DQS_BJ0M_DQS_B0

M_DATA_B45M_DATA_B28M_DATA_B15

M_DATA_B26

M_DATA_B59M_DATA_B54

M_DATA_B24

M_DATA_B36M_DATA_B2

M_DATA_B32

M_DATA_B4

M_DATA_B9

M_DATA_B37M_DATA_B0

M_DATA_B12M_DATA_B1

M_DATA_B31

M_DATA_B60

M_DATA_B11

M_DATA_B19M_DATA_B7

M_DATA_B14

M_DATA_B29

M_DATA_B56M_DATA_B46M_DATA_B23

M_DATA_B49

M_DATA_B63

M_DATA_B53

M_DATA_B25

M_DATA_B47M_DATA_B5

SRCOMP1

SRCOMP2

SRCOMP3SMRCOMPVOH

SMRCOMPVOLTP_MCH_AN21

TP_MCH_AP21

1D8V_STR1D8V_STR

1D8V_STR

M_DQS_BJ[7 0]21CK_M_200M_N_DDR1_B

21

M_SCS_B1J20,21

M_DATA_B[63 0] 21M_DATA_B[63 0] 21

M_CAS_BJ20,21

M_DATA_B[63 0] 21M_DQS_B[7 0] 21

M_RAS_BJ20,21

M_DQS_BJ[7 0]21M_DQM_B[7 0] 21

M_ODT_B[1 0]

20,21

M_DQM_B[7 0] 21

M_SCS_B0J20,21

M_DQS_B[7 0] 21

M_WE_BJ20,21

M_DATA_B[63 0] 21

M_DQS_B[7 0] 21

M_DQM_B[7 0] 21M_DQS_B[7 0] 21

M_CAS_AJ18,19

M_DQS_BJ[7 0]21

CK_M_200M_N_DDR0_B21

M_DQS_B[7 0] 21

CK_M_200M_P_DDR1_B21

M_DQS_BJ[7 0]21M_DQM_B[7 0] 21M_WE_AJ

18,19

M_DQS_B[7 0] 21

M_DATA_B[63 0] 21M_MAA_B[14 0]

20,21

M_DQS_BJ[7 0]21

M_DQM_B[7 0] 21M_DQM_B[7 0] 21

M_DATA_B[63 0] 21

M_RAS_AJ18,19

M_DQM_A[7 0] 19M_DATA_A[63 0] 19

M_DQS_A[7 0] 19M_DATA_A[63 0] 19

M_DATA_A[63 0] 19

M_DQS_AJ[7 0]19M_DQS_A[7 0] 19M_DQM_A[7 0] 19

M_DQS_AJ[7 0]19M_DQM_A[7 0] 19

M_DQM_A[7 0] 19

M_DQS_A[7 0] 19

M_DATA_A[63 0] 19

M_DQM_A[7 0] 19M_DQS_AJ[7 0]19M_DQS_AJ[7 0]19M_DQS_AJ[7 0]19

M_DQS_A[7 0] 19

M_DQS_A[7 0] 19M_DATA_A[63 0] 19M_DQS_AJ[7 0]19

M_DQS_AJ[7 0]19M_DQM_A[7 0] 19

M_DATA_A[63 0] 19

M_DQS_A[7 0] 19M_DQS_AJ[7 0]19

M_DQM_B[7 0] 21M_DATA_B[63 0] 21

width 10 mils, spacing 10 mils

5 mils width/spacing minimum for max of 300 mils

in GMCH break-out area Placed close to GMCH pin

5 mils width, 10 mils spacing, max 500 mils length for breakout regionPlace CAP./RES within 1" of GMCH package

1D8V_STR: 10 mils width/10 mils spacing

SMRCOMPVOH: 0.8 *VCCSM

DDR2 Compensation Group Signals

del TP26del TP20

3.01K

Dummy*R1793.01K

+/-1%

*R1881K

+/-1%

*R1911K

+/-1%

Dummy

Trang 17

VCCA_EXP

1D25V_MCHPCIE

VCCA_DACVCCA_EXPVCCD_CRTVCCDQ_CRT

VCCA_HPLLVCCA_DPLLAVCCA_EXPPLLVCC_CL_PLL

VCCDQ_CRT

VCCA_MPLL1D25V_MCHPCIE

1D8V_STR

3D3V_SYS

5V_SYS1D5V_CORE

Place in the PCI-E power plane(less than 100 mils from the package)Intel DG: 220uF

Don't use 1.8, use 1.5v.

For GMCH heatsink hook This is for ICH7 heatsink hook.

Need to Check Change to Dummy

Modify by Steven 051707

Near the FB20

Near the NBModify by Steven 051707

+/-5%

R1341

+/-5%

R2181

+/-5%

R1951

+/-10%

L26L0805 1uH

Trang 18

M_MAA_A6 M_MAA_A8

M_MAA_A3

M_MAA_A2 M_MAA_A13

M_MAA_A14

M_BS_A1 M_BS_A0 M_MAA_A10 M_MAA_A0

DDR2 Channel A Termination

Channel A VTT_0.9V high-frequency decoupling caps.

Place as close to termination resistors as possible

Channel A VTT_0.9V Mid Range decoupling caps.

Placed in termination Island

Need to Check Change to Dummy Need to Check Change to Dummy

6.3V, X5R, +/-10%

*

C393 4.7uF

6.3V, X5R, +/-10%

* RN41 33

+/-5%

* RN41 33

+/-5%

1 5 8 4

R291 43 Ohm R291 43 Ohm

* RN37 33

+/-5%

* RN37 33

+/-5%

1 5 8 4

*

C444 4.7uF

6.3V, X5R, +/-10%

*

C444 4.7uF

6.3V, X5R, +/-10%

* RN39 33

+/-5%

* RN39 33

+/-5%

1 5 8 4

+/-5%

* RN40 33

+/-5%

1 5 8 4

R296 43 Ohm R296 43 Ohm

* RN38 33

+/-5%

* RN38 33

+/-5%

1 5 8 4

Trang 19

M_DATA_A25

M_DATA_A34

M_DQS_AJ6M_ODT_A1

M_DQM_A1

M_SCKE_A1M_BS_A0

M_DATA_A45M_DATA_A35M_DATA_A15

M_DATA_A63

M_DQM_A6M_DQM_A0

M_DATA_A24

M_MAA_A11

M_DATA_A10M_DQS_A3

M_MAA_A2

M_DATA_A60

M_DATA_A20

M_DATA_A30M_DATA_A1

M_DATA_A44M_DATA_A47SMVREF_A

M_MAA_A7

M_MAA_A12

M_DQS_AJ5M_DQS_AJ1

M_DATA_A50M_MAA_A10

M_DATA_A61M_DATA_A54M_DATA_A51M_MAA_A4

M_DATA_A8

M_DATA_A39M_DATA_A5

M_MAA_A8

M_DATA_A31M_DQS_A7

M_DATA_A48M_MAA_A3

M_MAA_A5

M_DATA_A53

M_DQM_A7M_DQS_A0

M_DATA_A32

M_DQS_AJ2M_DQS_AJ0

M_DQS_A6

M_DATA_A17M_DQS_A2

M_DATA_A52M_DATA_A33M_DATA_A6

M_DQS_A5

M_DATA_A0

M_DATA_A14

M_DQM_A[7 0] 16

M_ODT_A[1 0] 16,18

M_DQS_A[7 0] 16

M_DATA_A[63 0] 16M_DQS_AJ[7 0]16

CK_M_200M_P_DDR2_A

16

M_WE_AJ16,18

M_SCS_A1J16,18

Channel A DIMM 1 1.8V high-frequency decoupling caps

place as close to DIMM power pins as possible

Channel A DIMM II 1.8V high-frequency decoupling caps

place as close to DIMM power pins as possible

Place between Ch A DIMM II

+/-1%

*R3001K

+/-1%

*R2991K

Định dạng
Số trang	38
Dung lượng	1 MB