Digital design width CPLD Application and VHDL - Chapter 11 ppt

Knowing the input and output voltages and currents of these circuits isessential, since gate loading, power dissipation, noise voltages, and interfacing betweenlogic families depend on t

• Name the various logic families most commonly in use today and stateseveral advantages and disadvantages of each.

• Define propagation delay

• Calculate propagation delay of simple circuits, using data sheets

• Define fanout and calculate its value, using data sheets

• Calculate power dissipation of TTL and CMOS circuits

• Calculate noise margin of a logic gate from data sheets

• Draw circuits that will interface various CMOS and TTL gates

• Explain how a bipolar junction transistor can be used as a logic inverter

• Describe the function of a TTL input transistor in all possible input states:

HIGH, LOW, and open-circuit

• Explain the operation of a totem pole output

• Illustrate how a totem pole output generates power line noise and describehow to remedy this problem

• Illustrate why totem pole outputs cannot be tied together

• Explain the difference between open-collector and totem pole outputs of aTTL gate

• Illustrate the operation of TTL open-collector inverter, NAND, and NORgates

• Write the Boolean expression of a wired-AND circuit

• Design a circuit that uses an open-collector gate to drive a high-currentload

• Calculate the value of a pull-up resistor at the output of an open-collectorgate

• Explain the operation of a tristate gate and name several of its advantages

• Design a circuit using a tristate bus driver to direct the flow of data fromone device to another

• Describe the basic structure of a MOSFET and state its bias voltagerequirements

• Draw the circuit of an CMOS inverter and show how it works

• Draw the circuits of CMOS NAND and NOR gates and explain the operation of each.

• Design a circuit using a CMOS transmission gate to enable and inhibit digital and log signals

ana-• Interpret TTL data sheets to distinguish between the various TTL families

• Describe the use of the Schottky barrier diode in TTL gates

• Calculate speed-power products from data sheets

Our study of logic gates and flip-flops in previous chapters has concentrated on digital

logic and has largely ignored digital electronics Digital logic devices are electronic

circuits with their own characteristic voltages and currents No serious study of digital cuitry is complete without some examination of this topic

cir-It is particularly important to understand the inputs and outputs of logic devices aselectronic circuits Knowing the input and output voltages and currents of these circuits isessential, since gate loading, power dissipation, noise voltages, and interfacing betweenlogic families depend on them The switching speed of device outputs is also fundamentaland may be a consideration when choosing the logic family for a circuit design

Input and output voltages of logic devices are specified in manufacturers’ data sheets,which allows us to take a “black box” approach initially

Later in the chapter, we will examine some basic digital circuits at a transistor level,since digital logic is based on transistor switching Two major types of transistors, the bipo-lar junction transistor and the metal-oxide-semiconductor field effect transistor (MOSFET),form the basis of the major logic families in use today Transistor-transistor logic (TTL) isbased on the bipolar transistor Complementary MOS (CMOS) is based on the MOSFET

We will briefly study the operating characteristics of both bipolar transistors andMOSFETs and then see how these devices give rise to the electrical characteristics of sim-ple logic gates

11.1 Electrical Characteristics of Logic Gates

TTL Transistor-transistor logic A logic family based on bipolar transistors

CMOS Complementary metal-oxide semiconductor A logic family based onmetal-oxide-semiconductor field effect transistors (MOSFETs)

ECL Emitter coupled logic A high-speed logic family based on bipolartransistors

When we examine the electrical characteristics of logic circuits, we see them as practical,rather than ideal devices We look at properties such as switching speed, power dissipation,noise immunity, and current-driving capability There are several commonly availablelogic families in use today, each having a unique set of electrical characteristics that differ-entiates it from all the others Each logic family gives superior performance in one or more

of its electrical properties

CMOS consumes very little power, has excellent noise immunity, and can be used

with a wide range of power supply voltages

TTL has a larger current-driving capability than CMOS Its power consumption is

higher than that of CMOS, and its power supply requirements are more rigid

ECL is fast, making it the choice for high-speed applications It is inferior to CMOS

and TTL in terms of noise immunity and power consumption

TTL and CMOS gates come in a wide range of subfamilies Table 11.1 lists some ofthe TTL and CMOS variations of the quadruple 2-input NAND gate All gates listed have

K E Y T E R M S

11.1 • Electrical Characteristics of Logic Gates 499

the same logic function but different electrical characteristics Other gates would be larly designated, with the last two or three digits indicating the gate function (e.g., aquadruple 2-input NOR gate would be designated 74LS02, 74ALS02, 74F02, etc.)

simi-We will examine four electrical characteristics of TTL and CMOS circuits: tion delay, fanout, noise margin, and power dissipation The first of these has to do withspeed of output response to a change of input The last three have to do with input and out-put voltages and currents All four properties can be read directly from specifications given

propaga-in a manufacturer’s data sheet or derived from these specifications

Figures 11.1 and 11.2 show how the input and output voltages and currents are defined

in a 74XX00 NAND gate This designation can be generalized to any logic gate input oroutput

Table 11.1 Part Numbers for a Quad 2-input NAND Gate in Different

Logic Families

Part Number Logic Family

TTL 74LS00 Low-power Schottky TTL

74ALS00 Advanced low-power Schottky TTL

74HCT00 High-speed CMOS (TTL-compatible inputs) 74LVX00 Low-voltage CMOS

H H

IIH

L

IOL

L L

IIL

H

IOH

FIGURE 11.2

Input/Output Current Parameters

The voltages and currents are designated with two subscripts, one that designates an

input or output and another that indicates the logic level For example, VOLis the voltage at

the gate output when the output is in the logic LOW state IILis the input current when theinput is in the LOW state

These voltages and currents are specified in manufacturers’ published data sheets,which are usually available in print form in a data book or in an electronic format, such as

Portable Document Format (pdf) on a CD or internet site.

Figure 11.3 shows a data sheet for a 74LS00 NAND gate, which also shows parametervalues for a 54LS00 device A 54-series device is manufactured to military specifications,which require a high range of environmental operating conditions A 74-series device is suit-able for general or commercial use We will limit ourselves to the 74-series devices.The voltage and current parameters indicated in Figures 11.1 and 11.2 are all shown inthe 74LS00 data sheet Some parameters are shown as typical values, as well as maximum orminimum Typical values should be considered “information only” as device manufacturers

FIGURE 11.3

74LS00 Data (1 of 2) Reprinted with permission of Motorola.

QUAD 2-INPUT NAND GATE

GUARANTEED OPERATING RANGES

74

4.5 4.75

5.0 5.0

5.5 5.25

V

74

– 55 0

25 25

125 70

° C

74

4.0 8.0

mA

SN54/74LS00

QUAD 2-INPUT NAND GATE

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC CASE 632-08

N SUFFIX

PLASTIC CASE 646-06

14 1

14 1

ORDERING INFORMATION

SN54LSXXJ Ceramic SN74LSXXN Plastic SN74LSXXD SOIC

14 1

D SUFFIX

SOIC CASE 751A-02

• ESD > 3500 Volts

11.1 • Electrical Characteristics of Logic Gates 501

do not guarantee these values An exception to this would be the supply voltage, VCC, whosetypical value is simply indicated as the average of maximum and minimum values

Note that IIHand IILare shown in Figure 11.2 as flowing in opposite directions, as are

IOHand IOL On a data sheet, a current entering a gate is indicated as positive and a currentleaving the gate is shown as having a negative value The reason for these current directionswill become apparent when we examine the internal circuits of the gates later in the chapter

❘❙❚ EXAMPLE 11.1 What is the maximum value of VOLfor a 74LS00 NAND gate when the output current is at

its maximum value?

Solution When the output is in the LOW state, the output current is given by IOL,

which has a maximum value of 8 mA The output voltage, VOL, is specified for a value of

4 mA and for 8 mA Since the output condition is specified for maximum IOL(8 mA),

All Inputs VIL Input LOW Voltage

VOH Output HIGH Voltage

VOH Output HIGH Voltage

74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIHper Truth Table

IIH Input HIGH Current

20 µ A VCC = MAX, VIN = 2.7 V IIH Input HIGH Current

0.1 mA VCC = MAX, VIN = 7.0 V

ICC

Power Supply Current

CC

CL = 15 pF

The 74XX00 NAND gate data is sufficient to represent any logic functions having

“normal” output current within its particular logic family This data can be used for mostgate or flip-flop circuits within the family Some specialized devices with higher-currentoutputs (e.g., 74XX244 octal tristate buffers) have a different set of electrical characteris-tics within their family

In the following sections of the chapter, we will use a NAND gate from each ofthree device families (74LS00, 74HC00A, and 74HCT00A) for illustrating the generalprinciples of the various electrical characteristics Devices from other families will also

be used in examples and problems Data sheets for the various devices are included inAppendix C

❘❙❚ SECTION 11.1 REVIEW PROBLEM11.1 What are the maximum values of voltage and current we can expect at the output of

a 74LS00 NAND gate when both inputs are LOW?

11.2 Propagation Delay

t pHL Propagation delay when the device output is changing from HIGH to LOW

t pLH Propagation delay when the device output is changing from LOW to HIGH

Propagation delay occurs because the output of a logic gate or flip-flop cannot respondinstantaneously to changes at its input There is a short delay, on the order of severalnanoseconds, between input change and output response This is largely due to the charg-ing and discharging of capacitances inherent in the switching transistors of the gate or flip-flop

Figure 11.4 shows propagation delay in two gates: a 74XX00 NAND gate and a74XX08 AND gate Each gate has an identical input waveform, a LOW-HIGH-LOW

pulse After each input transition, the output changes after a short delay, t p

K E Y T E R M S

FIGURE 11.4

Propagation Delay in NAND and AND Gates

Two delays are shown for each gate: t pLH and t pHL The LH and HL subscripts show

the direction of change at the gate output; LH indicates that the output goes from LOW to HIGH, and HL shows the output changing from HIGH to LOW.

Propagation delay is the time between input and output voltages passing through astandard reference value The reference voltage for standard TTL is 1.5 V LSTTL andCMOS have different reference voltages, as follows

11.2 • Propagation Delay 503

Propagation Delay for Various Logic Families:

LSTTL: Time from 1.3 V at input to 1.3 V at output

Other TTL: Time from 1.5 V at input to 1.5 V at output

CMOS: Time from 50% of maximum input to 50% of maximum output

❘❙❚ EXAMPLE 11.2 Use the data sheet in Figure 11.3, as well as those in Appendix C, to find the maximum

propagation delays for each of the following gates: 74LS00 (quadruple 2-input NAND),74LS02 (quadruple 2-input NOR), 74LS08 (quadruple 2-input AND), and 74LS32(quadruple 2-input OR)

❘❙❚ EXAMPLE 11.3 Use data sheets to find the maximum propagation delays for each of the following logic

gates: 74F00, 74AS00, 74ALS00, 74HC00, and 74HCT00

❘❙❚All gates in Example 11.3 have the same logic function (2-input NAND), but differ-ent propagation delay times We might ask, “Why not always use the advanced SchottkyTTL gate (74AS00), since it is the fastest?” The main reason is that it has the highestpower dissipation of the gates shown We wouldn’t know this without looking

up other specs on the data sheet (We will learn how to do this later in the chapter.) Thus,

it is important to make design decisions based on complete information, not just oneparameter

Propagation Delay in Logic Circuits

A circuit consisting of two or more gates or flip-flops has a propagation delay that is the

sum of delays in the input-to-output path Delays in gates that do not affect the circuit

output are disregarded Figure 11.5 shows how propagation delay works in a simple logic

circuit consisting of a 74HC08 AND gate and a 74HC32 OR gate Changes at inputs A and

B must propagate through both gates to affect the output The total delay in such a case is the sum of t p1 and t p2 A change at input C must pass only through gate 2 The circuit delay resulting from this change is only t p2

FIGURE 11.5

Propagation Delays in a Logic Gate Circuit

The timing diagram in Figure 11.5 shows the changes at inputs A, B, and C and the

re-sulting transitions at all gate outputs

Assume VCC 4.5 V and temperature range is 55°C to 25°C

1 When A goes LOW, AB, the output of gate 1, also goes LOW after a maximum delay of

t pHL  15 ns This makes Y go LOW after a further delay of up to t pHL 15 ns Total

delay: t p  t pHL1
t pHL2 15 ns
15 ns  30 ns, max

2 The HIGH-to-LOW transition at input B has no effect, since there is no difference

be-tween 0  1 and 0  0 AB is already LOW.

3 The LOW-to-HIGH transition at input C makes Y go HIGH after a maximum delay of

11.3 • Fanout 505

11.3 Fanout

Fanout The number of load gates that a logic gate output is capable of drivingwithout possible logic errors

Driving gate A gate whose output supplies current to the inputs of other gates

Load gate A gate whose input current is supplied by the output of another gate

Sourcing A terminal on a gate or flip-flop is sourcing current when the currentflows out of the terminal

Sinking A terminal on a gate or flip-flop is sinking current when the current flowsinto the terminal

I OL Current measured at a device output when the output is LOW

I OH Current measured at a device output when the output is HIGH

I IL Current measured at a device input when the input is LOW

I IH Current measured at a device input when the input is HIGH

We have assumed that logic gates are able to drive any number of other logic gates Sincegates are electrical devices with finite current-driving capabilities, this is obviously not the

case The number of gates (“loads”) a logic gate can drive is referred to as its fanout.

Fanout is simply an application of Kirchhoff’s current law: The algebraic sum ofcurrents at a node must be zero Thus, the fanout of a logic gate is limited by:

a The maximum current its output can supply safely in a given logic state (IOHor

IOL), and

b The current requirements of the load to which it is connected (IIHor IIL)

Figure 11.6 shows the fanout of an AND gate when its output is in the HIGH and

LOW states The AND gate, or driving gate, supplies current to the inputs of the other four gates, which are called the load gates.

Each load gate requires a fixed amount of input current, depending on which state it is

in The sum of these input currents equals the current supplied by the driving gate The

fanout is determined by the amount of current the driving gate can supply without ing its output circuit.

damag-The input and output currents of a gate are established by its internal circuitry damag-Thesevalues are usually the same for two gates in the same family, since the input and output cir-cuitry of a gate is common to all members of the family Exceptions may occur when the

output of a particular gate, such as the 74XX244 octal three-state buffer, has additional

out-put buffering or an inout-put of a gate such as a 74LS86 Exclusive OR is equivalent to morethan one input load

❘❙❚ EXAMPLE 11.4 The gates in Figure 11.7a and b are 74LS00 NAND gates Determine the output current of

the driving gate in each figure

H H

IOL

L

IIL

L L

IOH

H

IIH

a Low output on driving gate

b High output on driving gate

FIGURE 11.7

Example 11.4

Output Current due to One

Load Gate

Solution From the 74LS00 data sheet, IIL 0.4 mA and IIH 20 ␮A (There are two

values of IIHgiven in the data sheet Choose the one for the condition VIN 2.7 V, which

is the minimum output voltage of a driving gate in the HIGH state (VOH) The other value

is not appropriate since a gate will never have a 7 V output, as specified in the condition, ifits supply voltage is 5 V.)

Since the driving gate is driving one load, its output current is the same as the input

current of the load gate Therefore, the driving gate output currents are given by IOL 0.4

mA (positive, since it is entering the driving gate output) and IOH 20 ␮A (negative,

since it is leaving the driving gate output)

❘❙❚ EXAMPLE 11.5 Determine the output current of the driving gate in each of Figures 11.8a and b if the gates

are all 74LS00 NAND gates

H H

H H

a Low output on driving gate

b High output on driving gate

L L

Output Current to Fanout Calculation

If the load gates each represent the same load, then by Kirchhoff’s current law (KCL):

IOL IIL1
IIL2
… I ILnL  nLIIL

and IOH IIH1
IIH2
…
I IHnH  nHIIH

The fanout of the driving gate in the LOW and HIGH states can be calculated as:

leav-sourcing current When current is entering a gate, we say the gate is sinking current.

Note that the output of a gate does not always source current, nor does an input alwayssink current The current direction changes for the HIGH and LOW states at the same ter-minal The reason for this will become apparent when we study the circuitry of logic gateinputs and outputs

❘❙❚ EXAMPLE 11.6 How many 74LS00 inputs can a 74LS00 NAND gate drive? (that is, what is the fanout of

a 74LS00 NAND gate?)

Solution We must consider the following cases:

a When the output of the driving gate is LOW

b When the output of the driving gate is HIGH

(posi-❘❙❚The fanout in both HIGH and LOW states is the same in this case, but that is not al-ways so If the values of HIGH- and LOW-state fanout are different, the smallest valuemust be used For example, if a gate can drive four loads in the HIGH state or eight in theLOW state, the fanout of the driving gate is four loads If we attempt to drive eight loads,

we can’t guarantee enough driving current to supply all loads in both states

If a gate from one logic family is used to drive gates from another logic family, we

must use the output parameters (IOL, IOH) for the driving gate and the input parameters (IIL,

IIH) for the load gates

❘❙❚ EXAMPLE 11.7 Calculate the maximum number of Schottky TTL loads (74SXX series) that a 74LS86

XOR gate can drive

11.3 • Fanout 509

What happens if we load a gate output beyond its rated fanout? Adding more load

gates will do this by increasing the value of IOLbeyond its maximum rating If enough load

is added, the output of the driving gate might be destroyed by the heat generated by the cess current More likely, the performance of the driving gate will be degraded

ex-Figure 11.10 shows the relationship between output voltage and current for a 74LS00and a 74F00 NAND gate Figure 11.10a shows that the output voltage (LOW state) in-creases with increasing sink current Figure 11.10b indicates a decrease in HIGH state out-put voltage with an increase of source current

www.electronictech.com

a Output low characteristic

0.5

0 1

0

IOL, OUTPUT CURRENT (mA)

b Output high characteristic

LS00

F00

TA = 25 °C VCC = 4.5 V

Output Characteristics of 74LS00 and 74F00 Gate Reprinted with permission of Motorola

In other words, a greater load in either state takes the output voltage further away fromits nominal value This has an effect on other performance factors, such as noise margin,which we will examine in a later section of the chapter

The output voltage of a logic gate is defined in a datasheet for a particular value ofoutput current

We will examine the fanout of CMOS devices in a later section on interfacing betweenCMOS and TTL

N O T E

❘❙❚ SECTION 11.3 REVIEW PROBLEM

11.3 The input and output currents IOH, IOL, IIH, and IILof a TTL device may be classified

as source currents or sink currents List each input or output current as a source orsink current

14.4 Power Dissipation

Power dissipation The electrical energy used by a logic circuit in a specified

pe-riod of time Abbreviation: PD

VCC TTL or high-speed CMOS supply voltage

ICC Total TTL or high-speed CMOS supply current

ICCH TTL supply current with all outputs HIGH

ICCL TTL supply current with all outputs LOW

IT When referring to CMOS supply current, the sum of static and dynamic supplycurrents

CPD Internal capacitance of a high-speed CMOS device used to calculate itspower dissipation

Electronic logic gates require a certain amount of electrical energy to operate The measure

of the energy used over time is called power dissipation Each of the different families of

logic has a characteristic range of values for the power it consumes

For TTL and CMOS, the power dissipation is calculated as follows:

High-Speed CMOS: PD VCCIT (IT quiescent
dynamic supply

current)Figure 11.11 shows the supply voltage and current in a 74XX00 NAND gate

The main difference between the two families is the calculation of supply current.The supply current in a TTL device is different when its outputs are HIGH than when

they are LOW Thus, supply current, ICC, and therefore power dissipation, depends on the

states of the device outputs If the outputs are switching, ICCis proportional to output dutycycle

In a CMOS device, very little power is consumed when the device outputs are static.Much more current is drawn from the supply when the outputs switch from one state to an-other Thus, the power dissipation of a device depends on the switching frequency of itsoutputs

11.4 • Power Dissipation 511

Power Dissipation in TTL Devices

Two values are given for supply current in a TTL data sheet ICCLis the current drawn from

the power supply when all gate outputs are LOW ICCHis the current drawn from the ply when all outputs are HIGH If the gate outputs are not all at the same level, the supplycurrent is the sum of currents given by:

n is the total number of gates in the package

nHis the number of gates whose output is HIGH

nLis the number of gates whose output is LOWThe power dissipation of a TTL chip also depends on the duty cycle of the gate out-puts That is, it depends on the fraction of time that the chip’s outputs are HIGH

If we assume that, on average, the outputs of a chip are switching with a duty cycle of50%, the supply current can be calculated as follows:

ICC (ICCH
ICCL)/2

If the output duty cycle is other than 50%, the supply current is given by:

ICC DC ICCH
(1  DC) ICCL

where DC  duty cycle

❘❙❚ EXAMPLE 11.8 Figure 11.12 shows a circuit constructed from the gates in a 74XX00 quadruple 2-input

NAND gate package Use the data sheet shown in Figure 11.3 to determine the maximum

power dissipation of the circuit if the input is DCBA  1001 and the gates are 74LS00

NANDs Refer to the data sheets in Appendix C and repeat the calculation for 74ALS00and 74AS00 gates

Maximum supply current for each device is:

74LS00: ICC 0.75(1.6 mA)
0.25(4.4 mA)  2.3 mA

74ALS00: ICC 0.75(0.85 mA)
0.25(3 mA)  1.3875 mA

74AS00: ICC 0.75(3.2 mA)
0.25(17.4 mA)  6.75 mA

Maximum power dissipation for each device is:

74LS00: PD VCCICC (5 V)(2.3 mA)  11.5 mW

74ALS00: PD VCCICC (5V)(1.3875 mA)  6.94 mW

74AS00: PD VCCICC (5V)(6.75 mA)  33.75 mW

(1 mW 1 milliwatt  10⫺3W.)

❘❙❚ EXAMPLE 11.9 Find the maximum power dissipation of the circuit in Figure 11.12 if the gates are 74LS00

and the gate outputs are switching with an average duty cycle of 30%

Power Dissipation in High-Speed CMOS Devices

CMOS gates draw the most power when their outputs are switching from one logic state tothe other When the outputs are static (not switching), the large internal impedances of thegate limit the supply current A change of state requires the charging and discharging of in-ternal gate capacitances, resulting in a greater demand on the power supply current Thus,the faster a CMOS gate switches, the more current, and hence more power, it requires.CMOS supply current has two components: a quiescent current that flows when thegate is in a steady state and a dynamic component that depends on frequency For relativelyhigh frequencies (about 1 MHz and up), the quiescent component is small compared to thedynamic component and can be neglected

The quiescent current is usually specified for an entire chip package, regardless of the

number of gates It is given by ICCVCC For a 74HC00A NAND gate, ICC 1 ␮A at room

temperature for a supply voltage of VCC 6.0 V The dynamic component calculation

ac-counts for internal and load capacitance and is given, per gate, by:

(CL
CPD) V2CCf

where CLis the gate load capacitance

CPDis the gate internal capacitance

VCCis the supply voltage

f is the switching frequency of the gate output

❘❙❚ EXAMPLE 11.10 The circuit in Figure 11.12 is constructed from 74HC00A high-speed CMOS NAND gates

Calculate the power dissipation of the circuit:

a When the gate inputs are steady at the state DCBA  1010

b When the outputs are switching at an average frequency of 10 kHz

c When the outputs are switching at an average frequency of 1 MHzSupply voltage is 5 V Temperature range is 25°C to 55°C

11.4 • Power Dissipation 513

Solution Refer to the 74HC00A data sheet in Appendix C

a PD VCCICC (5 V)(1 ␮A)  5 ␮W This is the quiescent power dissipation of the

circuit

b The 74HC00A data sheet indicates that each gate has a maximum input capacitance, Cin

of 10 pF Assume that this value represents the load capacitance of gates 1, 2, and 3 ofthe circuit in Figure 11.12 Further assume that gate 4 has a load capacitance of 0 Thetotal power dissipation of the circuit is given by:

❘❙❚ EXAMPLE 11.11 The circuit in Figure 11.12 is constructed using a 74LS00 quad 2-in NAND gate and again

with a 74HC00 quad 2-in NAND Both circuits have identical waveforms applied to theirinputs that make all gate outputs switch with a duty cycle of 50% Calculate the frequency

at which the power dissipation of the 74HC00 circuit exceeds that of the 74LS00 circuit

Assume VCC 5 V and temperature  25°C for both circuits

Solution The power dissipation of the LSTTL circuit is:

f  

(118

1p

5F

m)(

W25V2)

N O T E

❘❙❚ SECTION 11.4 REVIEW PROBLEM11.4 Why does CMOS power dissipation increase with frequency?

11.5 Noise Margin

Noise Unwanted electrical signal, often resulting from electromagnetic radiation

Noise margin A measure of the ability of a logic circuit to tolerate noise

VIH Voltage level required to make the input of a logic circuit HIGH

VIL Voltage level required to make the input of a logic circuit LOW

VOH Voltage measured at a device output when the output is HIGH

VOL Voltage measured at a device output when the output is LOW

Electrical circuits are susceptible to noise, or unwanted electrical signals Such signals

are often induced by electromagnetic fields of motors, fluorescent lighting, frequency electronic circuits, and cosmic rays They can cause erroneous operation of adigital circuit Since it is impossible to eliminate all noise from a circuit, it is desirable

high-to build a certain amount of high-tolerance, or noise margin, inhigh-to digital devices used in the

circuit

In all circuits studied so far, we have assumed that logic HIGH is
5 volts and logic

LOW is 0 volts in devices with a 5-volt supply In practice, there is a certain amount oftolerance on both the logic HIGH and LOW voltages; for TTL devices, a HIGH at a de-vice input is anything above about
2 volts, and a LOW is any voltage below about
0.8

volts Due to internal voltage drops, the HIGH output of a TTL gate is typically about

3.5 volts

Figure 11.13 shows one inverter driving another In Figure 11.13a, the output of thefirst inverter and the input of the second have the same logic threshold That is, the input

of the second gate recognizes any voltage above 2.7 volts as HIGH (VIH 2.7 V) and

any voltage below 0.5 volts as LOW (VIL 0.5 V) The output of the first inverter

pro-duces at least 2.7 volts when HIGH (VOH 2.7 V) and no more than 0.5 volts as LOW

(VOL 0.5 V)

If there is noise on the line connecting the two gates, it will likely cause the voltage ofthe second gate input to penetrate into the forbidden region between logic HIGH and LOWlevels This is shown on the graph of the waveform in Figure 11.13a When the voltage en-ters the forbidden region, the gate will not operate reliably Its output may switch stateswhen it is not supposed to

Figure 11.13b shows the same circuit with different logic thresholds at input and

out-put The output of the first inverter is guaranteed to be at least 2.7 volts when HIGH (VOH

2.7 V) and no more than 0.5 volts when LOW (VOL 0.5 V) The second gate recognizes

any input voltage greater than 2 volts as a HIGH (VIH 2 V) and any input voltage less

than 0.8 volts (VIL 0.8 V) a LOW

The difference between logic thresholds allows for a small noise voltage, equal to orless than the difference, to be superimposed on the desired signal It will not cause the in-put voltage of the second inverter to penetrate the forbidden region This ensures reliableoperation even in the presence of some noise

For the 74LS04 inverter, the HIGH-state and LOW-state noise margins, VNH and

11.5 • Noise Margin 515

❘❙❚ EXAMPLE 11.12 Use the 74HC00A data sheet in Appendix C to calculate the noise margins for this gate

Assume VCC  4.5 V, ambient temperature (TA) is 25°C, and the driving gate is fully

loaded (IOUT 4 mA)

a Zero noise margin

b Nonzero noise margin

Noise within specs for VIH, VIL

FIGURE 11.13

Noise Margins

❘❙❚ SECTION 11.5 REVIEW PROBLEM11.5 Calculate the noise margins of a 74HCT00A NAND gate from the data sheet in Ap-

pendix C VCC 4.5 V, TA 25°C, IOUT 4 mA

11.6 Interfacing TTL and CMOS Gates

TTL Compatible Able to be driven directly by a TTL output Usually impliesvoltage compatibility with TTL

Interfacing different logic families is just an extension of the fanout and noise margin lems; you have to know what the load gates of a circuit require and what the driving gates cansupply In practice, this means you must know the specified values of input and output volt-ages and currents for the gates in question Table 11.4, which is derived from the manufac-turers’ data sheets included in Appendix C, gives an overview of input and output parametersfor a variety of TTL and CMOS families Ambient temperature is assumed to be 25°C

read-1 Input currents in a CMOS gate are very low, due to its high input impedance As a resultfanout is generally not a problem with CMOS loads Interface problems to CMOS loadshave to do with input voltage, not current

2 CMOS devices, such as 74HCT, that have the same values of VIHand VILas the TTL

families in Table 11.4, are considered to be TTL compatible, since they can be driven

de-Let us examine four interfacing problems: high-speed CMOS driving 74LS, 74LS ving 74HC, 74LS driving 74HCT, and 74LS driving low-voltage CMOS

dri-11.6 • Interfacing TTL and CMOS Gates 517

High-Speed CMOS driving 74LS

To design an interface between any two logic families, we must examine the output ages and currents of the driving gate and the input voltages and currents of the load gates.Assume a 74HC00 NAND gate drives one or more 74LS00 NAND gates From the

volt-74HC00 data sheet, we determine that VOH 3.98 V and VOL 0.26 V for VCC 4.5 V

The 74LS00 requires at least 2.0 V at its input in the HIGH state and no more than 0.8 V inthe LOW state The 74HC00 therefore satisfies the input voltage requirement of the74LS00

For the defined output voltages, the 74HC00 gate can source or sink 4 mA The fanoutfor the circuit is therefore calculated as follows:

nH  I

I

O IH

H

  

2

40

m

␮

AA

  200

nL  I

I

O IL

L

  4

0

m.4A

As mentioned earlier, CMOS has a very small input current and therefore does not present

a fanout problem to a 74LS driving gate However, we must also examine the interface forvoltage compatibility

From data sheets, we see that a 74LS00 gate is guaranteed to provide at least 2.7 V inthe HIGH state and no more than 0.5 V in the LOW state A 74HC00 gate will recognizeanything less than 1.35 V as a logic LOW and anything more than 3.15 V as a logic HIGH.The 74LS00 meets the LOW-state criterion, but it cannot guarantee sufficient output volt-age in the HIGH state

In order to properly drive a 74HC input with a 74LS output, we must provide a pull-upresistor to ensure sufficient HIGH-state voltage at the 74HC input The circuit is illustrated

in Figure 11.14 The pull-up resistor should be between 1 k⍀ and 10 k⍀

in-terface 74HCT input voltages are the same as those for TTL (VIH 2.0 V and VIL 0.8 V)

Therefore, 74HCT inputs can be driven directly by LSTTL outputs

74LS Driving Low-voltage CMOS

CMOS families with supply voltages less than 5 V are rapidly becoming popular in newapplications Two of the reasons for their increasing prominence are reduced power dissi-

pation (inversely proportional to the square of the supply voltage) and smaller feature size

(i.e., size of the internal transistors) that allows more efficient packaging and faster tion Low-voltage logic is particularly popular for battery-powered applications such as

opera-laptop computing or cell phones Low voltage families typically operate at VCC 3.3 V or

2.5 V Newer devices are available for VCC 1.8 V or 1.65 V

Low-voltage CMOS families such as 74LVX or 74LCX can interface directly withTTL outputs if they are operated with a 3.0 V to 3.3 V power supply These families are notreally suitable for driving 5-volt TTL, as their noise margins are too small when they use a3.0 V supply voltage

If we wish to use a 74LS device to drive a 74HC device operating at a power supplyvoltage of less than 4.5 V, we can use a 74HC4049 or 74HC4050 buffer to translate theTTL logic level down to an appropriate value The 74HC4049 is a package of six invertingbuffers The 74HC4050 has six noninverting buffers These buffers can tolerate up to 15 V

on their inputs Their output voltages are determined by the value of their supply voltage.Figure 11.15 shows an LSTTL-to-74HC interface circuit with a 74HC4050 buffer.Note that the interface buffer has the same power supply voltage as the load gate Bothsides of the interface are referenced to the same ground

GND

FIGURE 11.15

74LS-to-74HC Interface Using a 74HC4050 Buffer

❘❙❚ SECTION 11.6 REVIEW PROBLEM11.6 A 74LS00 driving gate is to be interfaced to a 74HC00 load using a 74HC4050 non-inverting buffer The 74HC00 has a power supply voltage of 2.5 V What supply volt-age should the 74HC4050 buffer have? Why?

11.7 Internal Circuitry of TTL Gates

Cutoff mode The operating mode of a bipolar transistor when there is no tor current flowing and the path from collector to emitter is effectively an open cir-cuit In a digital application, a transistor in cutoff mode is considered OFF

collec-Saturation mode The operating mode of a bipolar transistor when an increase inbase current will not cause a further increase in the collector current and the pathfrom collector to emitter is very nearly (but not quite) a short circuit This is the ONstate of a transistor in a digital circuit

TTL has been around for a long time The first transistor-transistor logic ICs were developed

by Texas Instruments around 1965 Since then, there have been many improvements in thespeed and power consumption of these devices, but the basic logic principles remain largelyunchanged Even though they are seldom used in modern designs, it makes sense to examinethe internal circuitry of standard TTL gates such as the 7400 NAND, 7402 NOR, and 7404inverter because the internal logic concepts are similar to the more advanced types of TTL.The most important parts of the circuit, as far as a designer or technician is concerned,are the input and output circuits, because they are the only parts of the chip to which wehave access It is to these points that we interface other circuits and where we make diag-

K E Y T E R M S

11.7 • Internal Circuitry of TTL Gates 519

nostic measurements A basic understanding of the inputs and outputs of logic gate cuitry is helpful when we design or troubleshoot a digital circuit

cir-Bipolar Transistors as Logic Devices

The basic element of a TTL device is the bipolar junction transistor, illustrated in Figure11.16 This is not the place to give a detailed analysis of the operation of a bipolar transis-tor, but a simplified summary of operating modes will be useful

The bipolar transistor is a current amplifier having three terminals called the collector,emitter, and base Current flowing into the base controls the amount of current flowingfrom the collector to the emitter If base current is below a certain threshold, the transis-

tor is in cutoff mode and no current flows in the collector In this state, the base-emitter

voltage is less than 0.6 V and the collector-emitter path acts like an open circuit We cantreat the collector-emitter path as an open switch, as shown in the lefthand diagram inFigure 11.17

FIGURE 11.16

Currents and Voltages in an NPN

Bipolar Transistor

FIGURE 11.17

NPN Bipolar Transistor as a Switch

Table 11.5 Bipolar Transistor Characteristics

Cutoff Active Saturation

col-If the base current increases still further, collector current reaches a maximum value

and will no longer increase with base current This is called the saturation mode of the

transistor The saturated value of collector current, ICS, is determined by (1) the resistance

in the collector-emitter current path, (2) the voltage drop across the collector and emitter,

VCE, and (3) the collector supply voltage, VCC Base-emitter voltage is about 0.7 V and willnot increase significantly with increasing base current The voltage between collector andemitter is in the range from 0.2 V to 0.5 V In this mode, we can treat the transistor as aclosed switch, as shown in the righthand diagram of Figure 11.17

Table 11.5 summarizes the voltages and currents in the cutoff, active, and saturationregions

❘❙❚ EXAMPLE 11.13 Figure 11.18 shows an NPN bipolar transistor connected in a common-emitter

configura-tion With the right choice of input voltages, this circuit acts as a digital inverter

FIGURE 11.18

Example 11.13 Transistor as Inverter

FIGURE 11.19

Example 11.13

Voltage and Current Analysis of Inverter

Analyze the circuit to show that it acts as an inverter if a logic HIGH is defined as

3 V and a logic LOW is defined as 0.5 V Assume that b  100, and assume that

VBE  0.7 V and VCE 0.2 V in saturation

Solution We will analyze the circuit with two input voltages: 3 V (logic HIGH) and 0.5

V (logic LOW) These two conditions are shown in Figure 11.19

High input We must prove that VI 3 V is sufficient to saturate the transistor Let us

as-sume that this is true and find out if calculations confirm our assumption

Figure 11.19a shows the circuit with VI 3 V By Kirchhoff’s voltage law (KVL):

Collector current won’t increase beyond its saturated value, even if base current

in-creases Therefore, if the transistor is saturated, bIBwill be larger than the current actuallyflowing in the collector-emitter path

In saturation, the collector current can be calculated by KVL:

VCC ICRC
VCE, or

IC (VCC VCE)/RC

IC (5 V  0.2 V)/470 ⍀

 10.2 mA

Since bIB C, the transistor is saturated Thus, an input voltage of 3 V will produce

sufficient base current to saturate the transistor The output is given by VO VCE 0.2 V,

which is within the defined range of a logic LOW

LOW input Figure 11.19b shows the circuit with VI 0.5 V By KVL:

Table 11.6 summarizes the operation of the circuit as an inverter

11.7 • Internal Circuitry of TTL Gates 521

Table 11.6 Input and Output of Single-Transistor

TTL Open-Collector Inverter and NAND Gate

Open-collector output A TTL output where the collector of the LOW-state put transistor is brought out directly to the output pin There is no built-in HIGH-state output circuitry, which allows two or more open-collector outputs to be con-nected without possible damage

out-The TTL gates (7405, 7401, 7404, 7400, and 7402) used in the following sections

to illustrate TTL circuit principles are no longer in general use They are from theoriginal (“standard”) TTL family, which has been superceded by faster and moreefficient devices However, the standard TTL devices are easier to understand thandevices from the newer TTL subfamilies, since their circuit structure is simpler Theoperating principles are similar in both the standard and newer families, so we willuse the standard devices to illustrate the general principles of TTL operation

Figure 11.20 shows the circuit of the simplest TTL gate: a 7405 inverter with open-collector outputs This circuit performs the same function as the single-transistor inverter we exam-

ined in Example 11.13 These circuits differ most obviously in their input circuitry Theinverter circuit in Example 11.13 has a resistor as its input; the 7405 inverter has a transistor,

N O T E

K E Y T E R M

Q1, as its input The input transistor allows faster switching of input states This tion is common to all standard TTL gates and will be examined in detail later in this section.

configura-The logic function of the 7405 is performed by transistors Q2and Q3 Output

transis-tor Q3is switched ON and OFF by current flowing in the collector-emitter path of Q2

When Q3is ON, Y is LOW.

However, when Q3is OFF, Y is floating There is a high impedance between Y and ground, so the output is not LOW But there is no connection to VCCto make the output

HIGH In this condition, Y is neither HIGH nor LOW.

To enable the output to produce a HIGH state, we need to add an external pull-up

re-sistor The value of this resistor depends on the current sinking capability of Q3, specified

in the data sheet as IOL We will do such calculations in a later example

TTL Inputs

Transistor Q1and diode D1make up the input circuit of the TTL inverter of Figure 11.20.The diode protects the input against small negative voltages If the input goes more nega-tive than about 0.7 V, the diode will conduct, effectively short-circuiting the input to

ground plus one diode drop This clamps the input to 0.7 V D1has no logic function

Q1can be treated as two back-to-back diodes, as shown in Figure 11.21 Figure 11.22shows how the input responds to logic HIGH and LOW voltages

LOW Input. When a TTL input is made LOW, the base-emitter junction of Q1acts as a

forward-biased diode, creating a current path from V to ground via the input pin This

FIGURE 11.20

Open-Collector Inverter (7405)

11.7 • Internal Circuitry of TTL Gates 523

current makes up the majority of current IIL, which has a maximum value of 1.6 mA instandard TTL (0.4mA in LSTTL)

At the moment the input is made LOW, the transistor action of Q1transports charge

away from the base of Q2, pulling it LOW and keeping it in cutoff mode This current dies

out when the base charge of Q2has been depleted, shortly after the LOW is applied to the

input pin The diode formed by the base-collector junction of Q1does not carry sufficient

current to turn on Q2, since the base-emitter path is of much lower impedance

HIGH Input. A HIGH at a TTL input reverse-biases the base-emitter junction of Q1

Only a small leakage current, IIH, flows The maximum value of IIHis 40 ␮A for standard

TTL (20 ␮A for LSTTL)

Since the low-impedance current path to the input pin has not been established,

cur-rent flows to the base of Q2via the forward-biased base-collector junction of Q1 This

cur-rent is sufficient to saturate Q2

Open (Floating) TTL Input. An open-circuit TTL input acts as a logic HIGH, as trated by Figure 11.23 A TTL input relies on a logic LOW to establish a low-impedance

illus-current path from VCCto the input pin If the input is open, this LOW is not present andcurrent flows in the base-collector junction of the transistor, by default This is the samecurrent that flows under the HIGH-input condition

This HIGH is not stable; it can be converted to logic LOW by induced noise at the put pin To avoid this uncertainty, an unused input should always be wired to a logic HIGH

LOW Input. As was described above, a LOW input establishes a low-impedance path to

ground, which draws current through the base-emitter junction of Q1 This action also

pre-vents base current from flowing in transistor Q2, causing it to be in cutoff mode and

mak-ing IC2 0

Since IB3is derived from IC2, IB3 0 and Q3is cut off, making a high-impedance path

between the collector and emitter of Q3 As was the case with the single-transistor inverter

in Example 11.13, when IC3 0, then VO VCE VCC (Since no current flows through

the pull-up resistor, the voltage must be the same at both ends.) Output Y is HIGH.

HIGH Input. When input A is HIGH, the base-emitter junction of Q1does not have ficient voltage across it to be forward-biased Current flows through the base-collector

suf-junction of Q1, saturating Q2

Since Q2is ON, current flows to the Q2emitter and splits through the 1-k⍀ resistor

and the base of Q3 The output transistor, Q3, turns ON, establishing a low-impedance

cur-rent path from output Y to ground Curcur-rent is limited by the external pull-up resistor, which must be chosen to keep IOLat or under its rated value of 16 mA VCE3is about 0.2 V to 0.4

V Output Y is LOW.

TTL Open-Collector NAND

Figure 11.25 shows one gate of a 7401 quadruple 2-input NAND gate with open-collectoroutputs The circuit is the same as that of the 7405 inverter, except that the input transistorhas a second emitter Multiple-emitter transistors of this type are common in TTL circuitsand can be modeled by the diode equivalent in Figure 11.25b Figure 11.26 shows the re-sponse of the multiple-emitter input transistor to various combinations of logic levels

11.7 • Internal Circuitry of TTL Gates 525

If both inputs are LOW, the NAND acts exactly the same as the 7405 inverter with a LOW input (A low-impedance path is created through a base-emitter junction.) Output Y

is HIGH, provided an external pull-up resistor is connected to output A partial truth table

for this condition is:

If one input is LOW, the input acts the same as the inverter with a LOW input The

low-impedance current path through the one grounded emitter prevents sufficient

base-collector current from flowing to forward-bias that junction Output Y is HIGH if a pull-up

resistor is connected to the output A partial truth table is as follows:

If both inputs are HIGH, the NAND circuit acts like the 7405 when its input is HIGH.

(There is no base-emitter current path A collector-emitter path is established by default.)

Output Y is LOW This condition can be represented by:

Combining all these conditions, we get the standard NAND truth table:

If one or more emitters of a TTL multiple-emitter input transistor is LOW, the input

is a LOW equivalent All emitters must be HIGH to make the transistor input aHIGH equivalent

These statements lead to the familiar NAND-gate descriptive sentences, illustrated bythe gate symbols in Figure 11.27

a At least one input LOW makes the output HIGH

b Both inputs HIGH make the output LOW

N O T E

FIGURE 11.27

DeMorgan Equivalent Forms of a NAND Gate

❘❙❚ SECTION 11.7A REVIEW PROBLEM11.7 What are the two main functions of the pull-up resistor on the output of an open-collector gate?

K E Y T E R M

11.7 • Internal Circuitry of TTL Gates 527

Gates with totem pole outputs cannot be used in all digital circuits For example, collector gates are required when several outputs must be tied together, a connection called

open-wired-AND Totem pole outputs would be damaged by such a connection, since there is

the possibility of conflict between an output HIGH and LOW state

Open-collector outputs can also be used for applications requiring high current driveand for interfacing to circuits having supply voltages other than TTL levels

A special symbol defined by IEEE/ANSI Standard 91-1984, an underlined square amond, is shown in Figure 11.28 This symbol is added to a logic gate symbol to indicatethat it has an open-collector output Other symbols, such as a star (*), a dot (●), or the ini-tials OC are also used

Open-Collector Symbols Shown

for a NAND Gate (e.g., 7401)

configura-possible ON and OFF states The only way output Y can remain HIGH is if all the

tran-sistors are in their OFF states, as in Figure 11.30c This can happen only if the outputs

of the inverters are all HIGH This is the same as saying the outputs are ANDed

to-gether at Y.

The Boolean expression for Y is:

Y  苶A  苶B  苶 C

 A
B
C

By DeMorgan’s theorem, the wired-AND connection of inverter outputs is equivalent

to a NOR function Because of this DeMorgan equivalence, the connection is sometimescalled “wired-OR.”

Figure 11.31 shows three NAND gates in a wired-AND connection Since the output

functions are ANDed, the Boolean expression for Y is:

Y 苶AB  苶CD  苶EF

 AB
CD
EF

The resulting function is called AND-OR-INVERT Normally this requires at leasttwo types of logic gate—AND and NOR The wired-AND configuration can synthesizeany size of AND-OR-INVERT network using only NAND gates.

The wired-AND function is sometimes shown as an AND symbol around a solderedconnection, as shown in Figure 11.31b

FIGURE 11.30

Output Transistors of

Open-Collector Inverters in a

Wired-AND Connection

11.7 • Internal Circuitry of TTL Gates 529

High-Current Driver

Standard TTL outputs have higher current ratings in the LOW state than in the HIGH state.Thus, open-collector outputs are useful for driving loads that need more current than a stan-dard TTL output can provide in the HIGH state There are special TTL gates with higher rat-

ings of IOLto allow even larger loads to be driven Typical loads would be LEDs, cent lamps, and relay coils, all of which require currents in the tens of milliamperes

incandes-❘❙❚ EXAMPLE 11.14 A 74LS07 hex buffer/driver contains six noninverting buffers whose outputs are

open-collector, rated for IOLmax 40 mA and VOHmax 30 V That is, even though there is no

internal circuit to provide a logic HIGH at the output, the output transistor can withstand avoltage of up to 30 V without damage

Figure 11.32 shows a 74LS07 buffer driving an incandescent lamp rated at 24 V, with aresistance of 690 ⍀ Calculate the current that flows when the lamp is illuminated What

logic level at A turns the lamp on? Could the lamp be driven by a 74LS05 inverter? Why or

why not?

Solution From the 74LS07 data sheet in Appendix C, we see that VOL  0.4 V for

IOL 16 mA and VOL 0.7 V for IOL 40 mA Assume the latter value

By KVL: 24 V  (IOL)(690 ⍀)  VOL 0

Thus, IOL (24 V  0.7 V)/690 ⍀  33.8 mA

Since the buffer is noninverting, and current flows when the output of the 74LS07

sinks current to ground (LOW), the lamp is on when A is LOW.

A 74LS05 open-collector inverter would not be a suitable driver for the circuit for tworeasons: its output is only designed to withstand 5.5 V and it can only sink a maximum of

8 mA

❘❙❚

Value of External Pull-up Resistor

The value of the pull-up resistor required by an open-collector circuit is calculated usingmanufacturer’s specifications and the basic principles of circuit theory: Kirchhoff’s voltageand current laws (KVL and KCL) and Ohm’s law

Figure 11.33 shows the circuit model for calculating the value of Rext It accounts forthe current requirements of the loads, the LOW-state output voltage, and current-sinkingcapacity of the open-collector gate

The main rule in resistor selection is to keep the sum of currents into the

open-col-lector output to less than the maximum rated value of IOL

IOL IR
nIIL

I R  (VCC VOL/Rext

❘❙❚ EXAMPLE 11.15 Calculate the minimum value of the pull-up resistor for a 74LS05 inverter if the circuit

dri-ves ten 74LS00 NAND gate inputs

N O T E

FIGURE 11.33

Circuit Model for Pull-up Resistor Calculation

The resulting function is called AND- OR-INVERT Normally this requires at leasttwo types of logic gate? ?AND and NOR The wired -AND configuration can synthesizeany size of AND- OR-INVERT... 521

Table 11. 6 Input and Output of Single-Transistor

TTL Open-Collector Inverter and NAND Gate

Open-collector output A TTL...

V Output Y is LOW.

TTL Open-Collector NAND

Figure 11. 25 shows one gate of a 7401 quadruple 2-input NAND gate with open-collectoroutputs The circuit is the same as