• Interpret the logic diagrams of Universal PAL and GAL devices to mine the number of outputs and product terms and the type of control signals available in a device.. 8.1 Programmable S
Trang 1O U T L I N E
Sum-of-ProductsArrays
8.2 PAL Fuse Matrix and
CombinationalOutputs
8.3 PAL Outputs with
ProgrammablePolarity
8.4 PAL Devices with
ProgrammablePolarity
8.5 Universal PAL and
Generic Array Logic
C H A P T E R O B J E C T I V E SUpon successful completion of this chapter, you will be able to:
• Draw a diagram showing the basic hardware conventions for a products-type programmable logic device
sum-of-• Describe the structure of a programmable array logic (PAL) AND matrix
• Draw fuses on the logic diagram of a PAL to implement simple logicfunctions
• Describe the structures of combinational, programmable polarity, and registered PAL outputs
• Determine the number and type of outputs from a PAL/GAL part number
• Explain the structure of an output logic macrocell (OLMC)
• State differences between Universal PAL and generic array logic (GAL)and standard PAL
• Interpret the logic diagrams of Universal PAL and GAL devices to mine the number of outputs and product terms and the type of control signals available in a device
deter-• Interpret block diagrams to determine the basic structure of an AlteraMAX7000S CPLD, including macrocell configuration, Logic Array Blocks(LABs), control signals, and product term expanders
• State the differences between PLDs based on sum-of-products (SOP) tecture versus look-up table (LUT) architecture
archi-• Interpret block diagrams to determine the basic structure of a logic element
in an Altera FLEX10K CPLD, including look-up tables, cascade chains,carry chains, and control signals
• Interpret block diagrams to determine how a logic element in a FLEX10Kdevice relates to the overall structure of the device
• Interpret block diagrams to determine how logic array blocks and ded array blocks relate to the overall structure of a FLEX10K CPLD
embed-In the past several chapters, we have been using Altera’s MAX⫹PLUS II software to makecircuit designs for downloading into a complex programmable logic device (CPLD) Wehave treated this device as a black box—something whose function we design, but whosestructure we do not really understand In this chapter, we will look inside the box ■
Trang 2Before we examine the structure of an Altera MAX7000S CPLD, we will look at theinternal structure of several simpler devices that are based on similar technologies, such asthe PAL16L8 and PAL16R8 low-density PLDs (largely for an historical overview), thePALCE16V8, and the GAL22V10.
These devices are based on programmable matrices of sum-of-products (SOP) circuits, as is the Altera MAX series of devices The main programming element is theEEPROM (electrically erasable programmable read-only memory) cell EEPROM-baseddevices will retain their programmed data when power is removed from the device
The Altera FLEX series of CPLDs is based on another technology altogether It storeslogic functions in look-up tables (LUTs) that act as truth tables with four input bits Themain logic element of the FLEX series is the SRAM (static random access memory) cell.SRAM-based CPLDs must have their programming data loaded every time they are powered up They have the advantage of being faster than EEPROM devices, with a higher bit capacity
8.1 Programmable Sum-of-Products Arrays
Product line A single line on a logic diagram used to represent all inputs to anAND gate (i.e., one product term) in a PLD sum-of-products array
Input line A line that applies the true or complement form of an input variable tothe AND matrix of a PLD
PAL Programmable array logic Programmable logic with a fixed OR matrix and
a programmable AND matrix
The original programmable logic devices (PLDs) consisted of a number of AND and
OR gates organized in sum-of-products (SOP) arrays in which connections were made orbroken by a matrix of fuse links An intact fuse allowed a connection to be made; a blownfuse would break a connection
Figure 8.1a shows a simple fuse matrix connected to a 4-input AND gate True and
complement forms of two variables, A and B, can be connected to the AND gate in any bination by blowing selected fuses In Figure 8.1a, fuses for A 苶 and B are blown The output
com-of the AND gate represents the product term AB 苶, the logical product of the intact fuse lines.
Figure 8.1b shows a more compact notation for the AND-gate fuse matrix Rather than
showing each AND input individually, a single line, called the product line, goes into the AND gate, crossing the true and complement input lines An intact connection
to an input line is shown by an “X” on the junction between the input line and the product line
A symbol convention similar to Figure 8.1b has been developed for programmablelogic Figure 8.2 shows an example
The circuit shown in Figure 8.2 is a sum-of-products network whose Boolean expression is given by:
F A苶 B苶 C A B苶 C苶The product terms are accumulated by the AND gates as in Figure 8.1b A buffer havingtrue and complement outputs applies each input variable to the AND matrix, thus
producing two input lines Each product line can be joined to any input line by leaving the
corresponding fuse intact at the junction between the input and product lines
If a product line, such as for the third AND gate, has all its fuses intact, we do not showthe fuses on that product line Instead, this condition is indicated by an “X” through the
gate The output of the third AND gate is a logic 0, since (A 苶 A B苶 B C 苶 C) 0 This is
nec-essary to enable the OR gate output:
A
苶 B苶 C A B苶 C 苶 0 A苶 B苶 C A B苶 C苶
K E Y T E R M S
Trang 38.1 • Programmable Sum-of-Products Arrays 331
Unconnected inputs are HIGH (e.g., A 苶 1 B苶 1 1 C A苶 B苶 C for the the first
prod-uct line)
If the unused AND output was HIGH, the function F would be:
A苶 B苶 C + A B苶 C苶 + 1 = 1
The configuration in Figure 8.2, with a programmable AND matrix and a hardwired
OR connection, is called PAL (programmable array logic) architecture.1
Since any combinational logic function can be written in SOP form, any Booleanfunction can be programmed into these PLDs by blowing selected fuses The programming
B A
A B
B A
A B
a Crosspoint fuse matrix ( A and B intact )
b PLD notation for fuse matrix
Trang 4is done by special equipment and its associated software The hardware and software lects each fuse individually and applies a momentary high-current pulse if the fuse is to beblown.
se-The main problem with fuse-programmable PLDs is that they can be programmedone time only; if there is a mistake in the design and/or programming or if the design
is updated, we must program a new PLD More recent technology has produced eral types of erasable PLDs, based not on fuses but on floating-gate metal-oxide-semiconductor transistors These transistors also form the basis of memory technolo-gies such as electrically erasable programmable read-only memory (EEPROM or
sev-E2PROM)
8.2 PAL Fuse Matrix and Combinational Outputs
JEDEC Joint Electron Device Engineering Council
JEDEC file An industry-standard form of text file indicating which fuses areblown and which are intact in a programmable logic device
Text file An ASCII-coded document stored on disk
Checksum An error-checking code derived from the accumulated sum of the databeing checked
Cell A programmable location in a PLD, specified by the intersection of an inputline and a product line
Product line first cell number The lowest cell number on a particular productline in a PAL AND matrix where all cells are consecutively numbered
Input line number A number assigned to a true or complement input line in aPAL AND matrix
Multiplexer A circuit that selects one of several signals to be directed to a single output
Figure 8.3 shows the logic diagram of a PAL16L8 PAL circuit This device can produce up
to eight different sum-of-products expressions, one for each group of AND and OR gates.The device has active-LOW tristate outputs, as indicated by the “L” in the part number.Each is controlled by a product line from the related AND matrix
The pins that can be used only as inputs or outputs are marked “I” or “O,” spectively Six of the pins can be used as inputs or outputs and are marked “I/O.” TheI/O pins can also feed back a derived Boolean expression into the matrix, where itcan be employed as part of another function A detail of an I/O section is shown inFigure 8.4
re-The part number of a PAL device gives the designer information about the number ofinputs and outputs and their configurations, as follows:
Number of inputsOutput type:
Trang 58.2 • PAL Fuse Matrix and Combinational Outputs 333
The numbering system has some potential ambiguities For example, it is not possible
to use 16 inputs and 8 outputs in a PAL16L8 device at the same time; 6 of the inputs are actually input/output pins Some possible configurations are as follows:
16 inputs (10 dedicated 6 I/O) and 2 dedicated outputs
10 dedicated inputs and 8 outputs (2 dedicated 6 I/O)
12 inputs (10 dedicated 2 I/O) and 6 outputs (2 dedicated 4 I/O)
Each of the outputs of the PAL16L8 is buffered by a tristate inverter, whose ENABLE input is controlled by its own product line When the ENABLE line of the tristate inverter is
FIGURE 8.3
Unprogrammed PAL16L8
Trang 6HIGH, the inverter output is the same as it would normally be—a logic HIGH or LOW, termined by the state of the corresponding OR gate output.
de-When the ENABLE line is LOW, the inverter output is in the high-impedance state.
The output acts as an open circuit, neither HIGH nor LOW; it is as though the output wascompletely disconnected from the circuit The inverter is permanently enabled if all fuses
on the ENABLE product line are blown, and permanently disabled if these fuses are
all intact
Published logic diagrams of PAL devices generally do not have fuses drawn on them.This allows us to draw fuses for any application In practice, PLDs have become too complex to manually draw fuse maps for most applications
Historically, PLD programming would begin with fuses drawn on a logic diagram, andeach fuse would be selected and blown individually by someone operating a hardware de-vice constructed for such a purpose
Fuse assignment is now done with special software such as ABEL, CUPL, or PALASM.These programs will take inputs such as Boolean equations, truth tables, or other forms andproduce the simplest SOP solution to the particular problem (MAXPLUS II is not config-ured to generate programming data for low-density PALs, although it can generate data forsimilar devices in the Altera Classic PLD series.)
The end result of such software is a JEDEC file, an industry-standard way of listing
which fuses in the PLD should remain intact and which should be blown The JEDEC file
is stored on disk as an ASCII text file Most PLD programmers will accept the JEDEC file
and use it as a template for blowing fuses in the target device
Fuse locations, called cells, are specified by two numbers: the product line first cell
number, shown along the left side of the diagram, and the input line number, shown
along the top The address of any particular fuse is the sum of its product line first cellnumber and its input line number The fuses on the PAL16L8 device are numbered from
0000 to 2047 ( 2016 31)
Figure 8.5 shows an example of a JEDEC file for a PAL16L8 application The filestarts with an ASCII “Start Text” character (^B) Next is some information required by thePAL programmer about the type of device (PAL16L8), number of fuses (2048), and soforth The fuse information starts with the line L0000, which is the first product line The1s and 0s which follow show the programmed state of each cell in each product line; a 1 is
a blown fuse and a 0 is an intact fuse In other words, each 0 in the JEDEC file represents
an X in the same position on the PAL logic diagram
The product terms for first sum-of-products output are set by the states of fuses
0000 to 0255 (eight product lines) In the file shown, all fuses are blown in the first product
I/O
FIGURE 8.4
PAL16L8 I/O Section
Trang 78.2 • PAL Fuse Matrix and Combinational Outputs 335
line, the second product line shows three intact fuses, and so forth Since all fuses are intact in the last three lines, they need not be shown in the JEDEC file
Whenever some unprogrammed product lines are omitted from the fuse map, the lastfuse line shown ends with an asterisk (*) The next line with programmed fuses is indicated
by a new fuse number For example, the second group of fuses (0256 to 0511) in Figure 8.5begins after the line marked L0256 in the JEDEC file The remaining fuse lines are similarly indicated
The JEDEC file in Figure 8.5 ends with a hexadecimal checksum (C8DCF), an
error-checking code derived from the programming data, and an ASCII “End Text” code (^C)
FIGURE 8.5
Sample JEDEC File
Trang 8In order to examine the general principle of fuse programming, let us develop the
pro-grammed logic diagram for a common combinational circuit: a 4-to-1 multiplexer (After
developing the fuse maps for several examples, we will not refer to this technique again.)
This circuit, shown in Figure 8.6a, directs one of four input logic signals, D0to D3, to
output Y, depending on the state of two select inputs S0and S1 The circuit works on the
enable/inhibit principle; each AND gate is enabled by a different combination of S1S0 Thebinary state of the select inputs is the same as the decimal subscript of the selected data
input For instance, S1S0 10 selects data input D2; the AND gate corresponding to D2isenabled and the other three ANDs are inhibited
The logic equation for output Y is given by:
Y D0苶S1苶S0 D1苶S1S0 D2S1苶S0 D3S1S0
Since the outputs of the PAL16L8 are active LOW, as illustrated in Figure 8.6b,
we should rewrite the equation as follows:
Y
苶 D苶0苶S1苶S0 D苶1苶S1S0 D苶2S1苶S0 D苶3S1S0
The D inputs must be complemented to reverse the effect of the active-LOW output The output is enabled when the EN input is HIGH Figure 8.7 shows the PAL16L8A logic
diagram with fuses for the multiplexer application
8.3 PAL Outputs With Programmable Polarity
The multiplexer application developed in the previous section uses a PAL device whoseoutput is always fixed at the active-LOW polarity This fixed polarity is suitable for mostapplications, but Boolean functions that would normally have active-HIGH outputs must
be implemented in DeMorgan equivalent form, which is not always very straightforward.Some applications require both active-HIGH and active-LOW outputs In such cases,
it is useful to have a device whose output polarity is fuse programmable
Figure 8.8 shows the logic diagram of a PAL20P8 PAL device This device is the same
as a PAL16L8, except that there are four more dedicated inputs, and the polarity of eachoutput is programmable The Exclusive OR gate on each output is programmed to act as ei-ther an inverter or a buffer When its associated fuse is intact, the XOR input is groundedand passes the output of its related SOP network in true form When combined with theoutput inverter, this produces an active-LOW output When the polarity fuse is blown, thefused XOR input floats to the HIGH state, inverting the SOP output; the output pin be-comes active HIGH
FIGURE 8.6
4-to-1 Multiplexer Circuits
Trang 98.3 • PAL Outputs With Programmable Polarity 337
The polarity fuses are given numbers higher than those of the main fuse array In thiscase, the product line fuses are numbered 0000 to 2559 and the output polarity fuses arenumbered 2560 to 2567
Figure 8.9 illustrates the selection of output polarity Two Boolean functions, F1 and F2, are programmed into the fuse array, with outputs at pins (17) and (15), respectively.
The equations are:
F1 A B A苶 B苶 F2 A B A苶 B苶
FIGURE 8.7
Programmed Logic Diagram for a 4-to-1 Multiplexer
Trang 10FIGURE 8.8
PAL20P8 Logic Diagram
We could, if we chose, rewrite F2 to show the output as active LOW:
F 苶苶2苶 A B A苶 B苶
The portion of the PAL20P8 logic diagram shown in Figure 8.9 represents the fuses
required to program F1 and F2 Pins (14) and (16) supply inputs A and B to the matrix The ENABLE lines of the tristate output buffers float HIGH, since all fuses are blown on the
corresponding product lines, thus permanently enabling the output buffers
The fuses numbered 2565 and 2567 select the polarity at pins (15) and (17) Fuse
2565 is blown The fused input to the corresponding XOR gate floats HIGH, thus makingthe gate into an inverter Combined with the tristate buffer, this makes pin (17) activeHIGH
Fuse 2567 is intact This grounds the input to the corresponding XOR gate, making thegate into a noninverting buffer Combined with the tristate output buffer, this makes pin(15) active LOW
Trang 118.3 • PAL Outputs With Programmable Polarity 339
drawing fuses on the device’s logic diagram
NOT: F1 A苶
AND: F2 BC
OR: F3 D E
NAND: F4 F苶G苶NOR: F5 H苶苶苶苶J苶
FIGURE 8.9
PAL Outputs With Programmable Polarity
Trang 12All functions must be in SOP form Outputs for NOT, AND, OR, Exclusive OR, and
Exclusive NOR are active HIGH Therefore, polarity fuses on the outputs for F1, F2, F3, F6, and F7 are blown NAND and NOR outputs are active LOW; the polarity fuses for F4 and F5 remain intact.
Figure 8.10 shows the logic diagram of the programmed PAL If only active-LOW puts were available, we would need to rewrite some of the equations to make the outputscorrespond to their DeMorgan equivalent forms, as follows:
Trang 138.4 • PAL Devices With Registered Outputs 341
8.4 PAL Devices With Registered Outputs
Register A digital circuit such as a flip-flop or array of flip-flops that stores one
or more bits of digital information
Registered output An output of a programmable array logic (PAL) device having
a flip-flop (usually D-type) that stores the output state
Flip-flops are generally found in programmable logic devices as registered outputs.
A register is one or more flip-flops used to store data Registered outputs in programmable
array logic (PAL) devices can be used for the same functions as individual flip-flops.Figure 8.11 shows the logic diagram of a PAL device with eight registered outputs:
a PAL16R8 The fuse matrix is identical to that of a PAL16L8 device; the differences
K E Y T E R M S
FIGURE 8.11
PAL16R8 Logic Diagram
Trang 14FIGURE 8.12
Example 8.2
Rotation to the Right (4-bit Data)
between the two devices are the registered outputs, a dedicated clock input (pin 1), and apin for enabling all registered outputs (pin 11)
With Registered PAL, the number of outputs shown in the part number indicates thenumber of registered outputs For example, a PAL16R4 device has four registered outputsand four combinational I/O pins, a PAL16R6 device has six registered outputs and twocombinational I/O pins, and a PAL16R8 has eight registered outputs
❘❙❚ EXAMPLE 8.2 A common data operation is that of “rotation.” Figure 8.12 illustrates how a 4-bit number
can be rotated to the right by 0, 1, 2, or 3 places by a circuit called a “barrel shifter.”
To rotate the data, move all bits the required number of places to the right As data reachthe rightmost position, move them to the beginning so that they are transferred in a closed loop
This operation is usually performed by serially shifting the data the required number
of places and feeding back the last output to the first input of a serial shift register
Rotation can also be accomplished by a parallel transfer operation We can load the
bits of the input into four D flip-flops in the order determined by two select inputs, S1and
S0 Assume that the binary number S1S0is the same as the rotation number in Figure 8.12.Table 8.1 summarizes the contents of the circuit after one clock pulse is applied
Table 8.1 Rotation to the Right by a Selectable Number of Bits
Write the Boolean expression(s) for the circuit
Show how the circuit can be implemented by a PAL16R4 device by drawing fuses onits logic diagram
SOLUTION Figure 8.13 shows a parallel transfer circuit (barrel shifter) that willperform the specified rotation The circuit works by enabling one AND gate in each group
of four for each combination of S1and S0 For example, when S1S0 00, the rotation is
0 and the leftmost AND gate of each group is enabled, transferring the parallel data into
the flip-flops so that D A A, D B B, D C C, and D D D After one clock pulse, Q A
Trang 158.4 • PAL Devices With Registered Outputs 343
FIGURE 8.13
Example 8.2
Rotation by Parallel Transfer (Barrel Shifter)
Similarly, if S1S0 10, we select a rotation of 2 The third AND gate from the left is
selected in each group of four This makes the data D A C, D B D, D C A, and D D
B appear at the flip-flop inputs After one clock pulse, Q A Q B Q C Q D CDAB.
The same principle governs the circuit operation for the other two select codes TheBoolean equations for the circuit are:
Q A S苶1苶S0A S苶1S0D S1苶S0C S1S0B
Q B S苶1苶S0B S苶1S0A S1苶S0D S1S0C
Q C S苶1苶S0C S苶1S0B S1苶S0A S1S0D
Q S苶 苶S D S苶 S C S 苶S B S S A
Trang 16FIGURE 8.14
Example 8.2
Programmed PLD for Selectable Bit Rotation
These equations imply that each registered output requires us to use four product lines,one for each product term The programmed logic diagram is shown in Figure 8.14 ❘❙❚
Trang 178.5 • Universal PAL and Generic Array Logic (GAL) 345
8.5 Universal PAL and Generic Array Logic (GAL)
One-time programmable (OTP) A property of some PLDs that allows them to
be programmed, but not erased
Generic array logic (GAL) A type of programmable logic device whose outputscan be configured as combinational or registered and whose programming matrix isbased on electrically erasable logic cells
Universal PAL A PLD based on erasable cells and configurable outputs, muchlike GAL, but primarily designed to emulate PAL devices, such as PAL16L8
Output logic macrocell (OLMC) An input/output circuit that can be
pro-grammed for a variety of input or output configurations, such as active HIGH or
active LOW, combinational or registered Often just called a macrocell.
In-system programmability (ISP) The ability of a PLD to be programmed
through a standard four-wire interface while installed in a circuit
JTAG port A four-wire interface specified by the Joint Test Action Group
(JTAG) used for loading test data or programming data into a PLD installed
There are several limitations of standard low-density PALs First, these devices are
one-time programmable (OTP) Since the AND matrix of a PAL is programmable by
blowing metal fuse links, programming is permanent; there is no opportunity tocorrect or update a design In development of a new design, where many modificationsmust be made to the original design, this can be particularly wasteful Second,standard PAL outputs are permanently configured either as combinational or registered
A given PAL has a certain number of each type of output, which may not be optimumfor the design Third, a standard PAL cannot be programmed while it is installed in acircuit
A number of low-density PLDs have been developed to address these concerns
Devices such as the PALCE16V8 Universal PAL (Vantis Corporation), and the GAL16V8 and GAL22V10 Generic Array Logic (Lattice Semiconductor)* are based on
sum-of-products fuse matrices, just as the earlier-version PALs However, these devicesare based on electrically erasable read only memory (EEPROM or E2PROM) cells, ratherthan fuses, which allow them to be erased and reprogrammed about 10,000 times Aprogrammed device will hold its data for about 20 years
Universal PALs and GALs also have programmable input/output configurations
An I/O pin can be configured as a registered output, a combinational output, or adedicated input, as required Additionally, an output can be specified as active-HIGH oractive-LOW
K E Y T E R M S
*Vantis has recently been acquired by Lattice, so these devices are really produced by the same company