analog bicmos design practices and pitfalls phần 10 pdf

Resis-tors R1 and R2 do not match well.surround-9.1.8 Ion Implant Resistor Conductivity Modulation Lightly doped ion implant resistors are affected by metal passing overthem.. Figure 9.10

chapter 9

Design Practices

Component matching and the protection from electrostatic discharge areimportant design practices Accurate component matching reduces costsand improves circuit function Protection from electrostatic discharge is

a necessary precaution for reliability Often chips are required to pass thehuman body model electrostatic discharge test discussed in this chapter

While the absolute values of device parameters are difficult to maintain,two devices can be accurately matched in a given circuit This permitscircuit design techniques to be used that result in accurate functions

In this section, chip layout for accurate matching of components is cussed

dis-Precise matching of components extends performance limits of cuits such as accurate voltage regulators or operational amplifiers withlow input offset voltage Laser trimming or zener zaping can extend per-formance limits but at the expense of test time and increased die area.Careful attention to matching can improve circuit performance, reducecosts and increase design success

cir-9.1.1 Component Size

Edge irregularities become a significant fraction of device geometriesfor small-sized devices Increasing size reduces the percent variabilitybetween matched components

The same unavoidable edge irregularities exist in large geometry vices as in small However, as shown inFigure 9.1for large geometries,the percent variation due to edge irregularities is smaller Therefore,two large devices will match better than two small devices If devicesare very large, the effects of lateral gradients cause the benefits of largedevices to diminish

de-Figure 9.1 Edge irregularities represent a larger fraction of device sions in small-sized devices.

dimen-9.1.2 Orientation

Matching improves when components are located close together and havethe same orientation This minimizes mismatch due to lateral processvariations

Figure 9.2 The resistors shown in A are oriented for the best match Crepresents the worst orientation

The best match components should be identical, the same size andshape, close together and oriented in the same direction Lateral processvariations such as diffusion gradients, temperature gradients, and maskmisalignments will cause component mismatch

Placing components as close as possible and orienting them in thesame direction is the best defense against lateral variations The layout

A inFigure 9.2will provide the best match Variations in the Y tion have no effect and the effects of variations in the X direction areminimized by the close proximity of the two devices In B, variations in

direc-X have no effect on matching, but variations in Y do Since the

separa-tion is greater than in layout A, the mismatch will be greater Layout

C is the worst case Variations in both X and Y effect the match

9.1.3 Temperature

The presence of a power dissipating component on the chip affects ing A large resistor or transistor dissipating power causes temperaturegradients on the chip Junction temperatures in power dissipating com-ponents can be several degrees above the temperature of the case Bipo-

match-lar transistor saturation current I s is strongly temperature dependent

The simulation described in Section 8.3.2 shows I schanging by an order

of magnitude for a 20-degree change in temperature Power dissipationand the resultant temperature gradients can be time varying making thebehavior of the matched components difficult to understand

Figure 9.3 Locating matched components equal distance from power pating components improves matching

Locating matched components equidistance from a component pating large amounts of power, as shown inFigure 9.3, improves match-ing

dissi-9.1.4 Stress

Mismatch is greater in packaged dies than in unpackaged wafers This isdue to crystalline stress introduced by the packaging process For{111}

plane wafers, locating matched pairs about the axis of symmetry in the

<211> direction near the die center improves matching.

Silicon is a piezoelectric crystal Stress affects electrical parameters.Chips are packaged at high temperature using materials having ther-mal coefficients different than silicon When the package cools to roomtemperature, stress gradients upset matching

Wafers used in the bipolar process are cut in the{111} plane The

biCMOS process uses wafers cut in the{100} plane. Figure 9.4shows atypical packaged bipolar die Stress is symmetrically distributed about

Figure 9.4 A packaged die is shown Stress is symmetrically distributed

about an axis of symmetry in the <211> direction.

Figure 9.5 In the{111} plane the <211> direction is parallel to the wafer

flat edge

an axis of symmetry, passing through the die center in the <211>

di-rection Stress gradients are greater near the edges and less near thecenter The absolute stress may be greater near the center, but gradi-ents cause mismatch, therefore components placed near the center willmatch better than components placed near the die edge For best match,components should be placed to maintain the symmetry, near the diecenter and equidistant from the axis of symmetry

In one case, comparisons between measurements taken at wafer probewith measurements taken on packaged circuits show 50% of opamp inputoffset drift nonlinearity due to packaging

9.1.5 Contact Placement for Matching

Layout geometries that result in device mismatch when ohmic contactsshift relative to the device, such as a resistor horseshoe layout, should

be avoided

Figure 9.6 This horseshoe layout for matched resistors is to be avoided

When placing contacts, care has to be taken to minimize the effect ofmask layer shifts on matching Consider the matched pair of resistorsshown inFigure 9.6 If contacts shift horizontally, one resistor increaseswhile the other decreases Vertical shifts have the same effect on bothresistors This horseshoe layout for matched resistors is to be avoideddue to the mismatch produced when the contacts shift relative to theresistor

9.1.6Buried Layer Shift

Alignment marks consisting of depressions bounded by steps 500A ◦ to

100A ◦ high are placed on the substrate before the epitaxial layer isgrown The buried layer is aligned to these marks The buried layer isdiffused into the substrate prior to the growing of the epitaxial layer

As the epi is grown, alignment marks placed on the substrate replicatethemselves in the epi Due to anisotropic growth of the epi, alignmentmarks shift Since the buried layer is aligned to the mark on the sub-strate and the other layers are aligned to the shifted mark on the surface

of the epi, there is an apparent shift of the buried layer as shown inFig

-ure 9.7 This can influence transistor properties causing mismatch

S P Weeks [1] studied pattern shift during CVD Epitaxy on (111)and (100) silicon He found typical relative shifts for (111) silicon of0.6 and a very small shift typically for (100) silicon Relative shift isdefined as the shift divided by the epi thickness A relative shift of 0.6represents a shift of 4.8 microns for an epi thickness of 8 microns.Transistor performance is affected when the edge of the shifted buriedlayer intersects the emitter or the deep N diffusion.[3] This can affectmatching The effect of buried layer shift is similar to the effect ofrelative shift of masks Careful attention to layout with the symmetric

Figure 9.7 A: Drawn - B: Actual The lateral shift to the right of the actualburied layer relative to the base and emitter is due to the shift to the left ofthe base and emitter alignment mark Here the shift causes the edge of theburied layer to intersect the emitter This can seriously change the effectivesaturation current [3].

layout of transistors minimizes buried layer shift effects

Pattern shift is reduced by modifying processing [2] using:

r Higher temperatures to obtain more isotropic growth

r Lower deposition rates

r Lower pressure [ this approach can cause faceting (development of

undesired crystal planes) or distortion on (100) silicon]

r SiH4instead of SiCl4

r (100) silicon, rather than (111) silicon (Pattern shift of (111)

silicon is reduced by cutting the wafer a few degrees off the exact(111) plane)

to assure matching resistors are in identical environments The dummyresistors may be used for other functions InFigure 9.8, R1 and R4 aredummies, added to assure R2 and R3 have identical environments

Figure 9.8 The four resistors shown are identical except for their ings Resistors R2 and R3 have symmetrical environments and match Resis-tors R1 and R2 do not match well.

surround-9.1.8 Ion Implant Resistor Conductivity Modulation

Lightly doped ion implant resistors are affected by metal passing overthem The potential difference between the resistor and the metal in-fluences the carrier concentration in the resistor and therefore the resis-tance

Figure 9.9 Metal passing over p-type ion implant resistors in n-epi is shown

Figure 9.10 Resistor match is upset by metal passing over one resistor

Metal passing over ion implant resistors form the metal oxide silicon(MOS) structure A positive voltage on the metal relative to the resistorrepels holes from the surface of the p-type ion implant resistor Thisincreases the resistivity The structure is like a MOS transistor with themetal acting as the gate The metal voltage changes (modulates) theresistor current Figure 9.9 shows the ion implant resistor with metalpassing over it Figure 9.10shows matched resistors where the match isupset by metal modulation one resistor

9.1.9 Tub Bias Affects Resistor Match

The voltage of a resistor relative to its epi tub influences the resistance.Two resistors in the same tub will mismatch if they are at differentvoltages as, for example, in a voltage divider

Figure 9.11 A Different resistor-tub bias produces different depletion gions, changing resistance and upsetting resistance matching B Separatetubs biased at the resistor high voltage reduce resistor-tub bias differencesimproving matching

re-The pn junction formed by p-type resistors in n-type epi tubs arereversed biased to isolate the resistors It is common practice to biasthe tubs at the highest voltage in the circuit (VCC) to assure the resistortub junction is reversed biased This can contribute to mismatch whendifferent voltages are applied to the resistors as in the voltage dividershown inFigure 9.11A

The reverse resistor-tub voltage produces a depletion region devoid

of charge carriers in the vicinity of the junction The depletion regionextends both sides of the junction The depth of penetration variesinversely with doping Therefore, the depletion region extends furtherinto the lightly doped epi tub than it does into the p-type resistor Thedepletion region in the resistor reduces the resistor cross section Thisincreases resistance The depth of penetration of the depletion regiondepends on the reverse voltage across the resistor-tub pn junction Theeffect is more pronounced for high resistivity ion implant resistors

Figure 9.11Ashows two matched resistors in a single tub The tub isbiased to the highest voltage in the circuit (VCC) The resistors form

a voltage divider where the resistor R2 is at a higher voltage than theresistor R1 This results in different depletion regions and thereforedifferent values of resistance than would be expected

The matched resistors in Figure 9.11B are placed in different tubs.This permits different tub bias voltages InFigure 9.11B the tubs arebiased at the voltage at the high end of the resistor This results in simi-lar resistor-tub voltages for both resistors with a resultant improvement

in matching

9.1.10 Contact Resistance Upsets Matching

Contact resistance can upset resistor matching when resistor values fer Matching of large resistor ratios is improved by composing the largerresistor from segments equal to the smaller resistor

dif-The value of a resistor is the drawn resistance plus the resistance

due to the contacts R = R d + 2R C, where each contact introduces a

resistance R C Contact resistance becomes significant when resistancevalues are small Large resistor ratios, where one of the resistor values

is small, can be upset by contact resistance

Consider a resistor ratio R2/R1

Figure 9.12 A large resistance ratio with one resistor composed of multiplerepetitions of the smaller resistor achieves a match independent of the contactresistance

The ratio depends on the contact resistance R C

A more accurate ratio results when the large resistor is composed of

a number of segments, each equal to the value of the smaller resistor asshown inFigure 9.12

The ratio equals 1/N , independent of the contact resistance.

9.1.11 The Cross Coupled Quad Improves Matching

A cross coupled quad layout reduces mismatch in the presence of lateralvariations Breaking a component into four parts and laying them out

so opposites are linked reduces mismatch Positive variations are celed by negative variations in the presence of linear gradients in processparameters.

can-Figure 9.13 Matched quad coupled resistors are shown in the presence of

a linear variation in sheet resistance R1+ R4 matches R2+ R3

Cross coupled quad resistors are shown inFigure 9.13 A linear

gradi-ent in the sheet resistance causes values to vary R1 plus R4 is matched

to R2 plus R3 The isoclines represent constant values of sheet tance in arbitrary units Resistance values are proportional to the sheet

resis-resistance The sheet resistances at R1 and R4 are 3 and 9 totaling 12

This matches the total of the sheet resistances at R2 and R3(5 and 7).Lateral variations of other parameters such as junction depth, ox-ide thickness, temperature, and stress can be compensated using crosscoupled quads The technique is not limited to resistors Matching oftransistors, diodes, and capacitors also benefits from the cross coupledquad structure

The nonlinear component of parameter gradients is not compensatedfor by the cross coupled quad For linear gradients, where the spacingbetween isoclines is constant, matching is good When isocline spac-ing varies, representing nonlinear gradients in the process parameters,matching is improved but not as much

9.1.12 Matching Calculations

The performance of precision circuits can be predicted if the accuracywith which matched components track is known In this section sim-ple hand calculations of approximate values for amplifier input offset

voltage and gain, and precision quantities that depend on matching areillustrated.

Resistor Matching Calculation

Resistance depends on fabrication tolerances and temperature The

temperature dependence of resistance is to a first order described by α

where the first term is due to temperature variations, the second is due

to variations in the sheet resistance and the third is due to variations in

n, the resistor geometry n, the geometric aspect ratio, is the resistor

length divided by its width n = L/W For the common case where

L  W , variations in n are dominated by variations in W The resistor

value is the geometric aspect ratio multiplied by the sheet resistance

Variations in temperature, variations in process parameters, as reflected

in sheet resistance, and variations in resistor geometry affect resistorvalues and therefore matching If two nominally identical resistors arelaid out to minimize differences in temperature and process variations,random variations in resistor width remain causing resistor mismatch.While the absolute values of the resistors vary widely, matched resis-tors will track to within a fraction of a percent Precise circuit functions

are realized using ratios of matched resistors For two nominally

identi-cal resistors R1and R2, their ratio is

of sheet resistance with distance will become a factor

Example

If the two resistors shown inFigure 9.14 track so that their ratio is

off by 0.1%, by what percent will the output voltage be off?

Figure 9.14 A bandgap regulator output of 1.25 volts is multiplied toachieve a 5 volt regulator output, using an opamp and a precision voltage

divider Resistor mismatch affects output voltage V o

In this example, V bg = 1.25 V , and R1/R2 = 3[1± 001], (for a 0.1%

error in the resistor ratio) Therefore,

V o = 1.25[1 + 3(1 + 001)] = 5[1 ± 00075]

This represents a 0.075% variation in the output voltage