21st Century Manufacturing Part 8 pptx

Thedie yield from basic wafer production, wafer testing, die separation,and retesting is considered in the next main section.5.11.3 Attachment, Wire Bonding, and Packaging The good dice

Cathode shield

Anode

Argoninlet

Cathode(sourcemateriaI)

High voltage ~

Tovacuum pumpfigure 5.28 Sputtering for the interconnect layers (from Introduction to

Microelecrric Fab,kotwnby Jaeger, ©1988 Reprinted by permission of Hall, Inc., Upper Saddle River, NJ)

Prentice-/Wafer

Fipe 5.29 Hotfilament evaporation

(from Semiconductor Device

Fundamentals by Pierret,©1996.Reprinted by permission of Prentice-Hall, Iac., Upper Saddle River, NJ)

ITovacuum pump

The e-beam method can cause wafer damaging x-rays In general practice allthese evaporation techniques are less favored in today's commercial tabs Sput-tering is used for its superior topological coverage and moderate pressurerequirements

After the last layer of metal is patterned, a final passivation layer is deposited

in order to protect the [C from contamination and damage Small openings are then

Wafers

Heater

Evaporating

"material

5.11 BACK·END PROCESSING METHODS

5.11.1 Summary

Wafers are electronically tested for functionality and separated into individual dice.Each die is set into a chosen package, wire-bonded to the outer perimeter of thepackage, and finally tested ready for assembly onto a printed circuit board (PCB)

This segment of semiconductor production is called back-end processing Figure 5.30

provides an overview of these back-end steps for one of the most common packagetypes, the dual-in-line package The single IC is shown on the front right side It is setonto the base with epoxy or a metal alloy The wire bonds (shown darker) run frombonding pads on theIeto the lead frame of the package The lead frame connections

go through to the Jcleads or gull-wings that subsequently are attached to the PCB.The outer cover (labeled molding compound) completes the package.5.11.2Testing and Separation

IC designers include special test dice on the wafer that are subjected to all the sameoxidation, etching, layering, and doping processes as the desired Ie These special testdice are monitored as much as possible after each of the processing steps describedearlier At the very end of wafer production these test dice are put through an addi-tional series of computer-controlled tests in which fine, needlelike probes contact thealuminum bonding pads of the test dice If this first check shows that the processingparameters were within proper limits, then each die is tested for functionality Dicethat need to be rejected are marked with an ink spot

After preliminary testing is completed, each die is separated from the wafer,usually by a diamond saw In this process the wafer is held down on a sticky sheet ofMylar and the diamond saw is used either to saw between the dice completely

Molding compound FigureS.30 Thedual-in-linepackage

(DIP) (from Manufacturing Engineering

and Technology 3/ebyKalpakjian,

through the wafer or to scribe the wafer and provide continuous notches In the latterapproach the wafer can he turned upsidedown on a soft pad A lightly pressurizedroller passes across the back of the wafer, and controlled cracks separate the dice.This method is related to the <100> wafer growing direction In this orientation, nat-ural cleavage planes run normal to the through thickness direction and to the dieare discarded, while the remaining chips are inspected visually, under a microscope,for defects Thedie yield from basic wafer production, wafer testing, die separation,and retesting is considered in the next main section.

5.11.3 Attachment, Wire Bonding, and Packaging

The good dice are then seated into a desired die package The bottom of the die issecured with a metal-filled epoxy, or with a 96% gold-4% silicon eutectic alloy thatmelts and then solidifies in the range 390°Cto 420°Cto secure the die to the surface.Wrre bonding makes the electrical contacts between the top of the die and thesurrounding lead frame of the package Figure 5.31 shows the delicate wires runningfrom the bonding pads (typically 100 to 125 microns in size) to the frame of the pro-pads, thermosonic bonding has emerged as the most efficient method of attachment

In thermosonic wire bonding, delicate,25 micron, gold or aluminum wires are

pressure-welded to the pads with a blunt indenter The bond is made secure by simultaneouslyheating the substrate to 150°Cand ultrasonically vibrating the joint Solid-statewelding thus occurs from a combination of pressure, vibration, and warm-plasticdeformation of the soft gold or aluminum Thermosonic bonding machines are easilyautomated for high-speed production

5.11.4 Dual-in-L1ne Pacbges IDIPs)

The package and packaging material chosen for a chip depend on the Ie's size, number

of extemallcads, power and heat dissipation requirements, and intended operatingenvironment Dual-in-line packages (DIPs) are common packaging styles They are

~Pl'''''~

.':'~ F1pre 5.31 The DIP packaging method (from Manufacturing Enginuring and

Technology 3/e by Kalpakjian, © 1995.Reprinted by permission of Prentice-Hall Inc"

-oeiawires

Lead framer.hin

inexpensive, easy to handle, and made from a variety of materials to suit the applicationprototype circuit design The usual fonn factor is a plastic rectangle with the I/O leadsplaced at approximately 0.1 inch spacings along the perimeter edges (Figure 5.31).5.11.5 Quad Flat Packages (QFPI

Quad flat packages (QFP) in either plastic or ceramic are today the most oftenseen commercial packages for gate arrays, standard logic cells, and microproces-sors Such flat packs are especially favored for computer systems with severalstacked printed circuit boards (PCBs), which demand low-profile chips to reducethe vertical packing space Figure 5.32 shows the standard layout The upper part

of the figure shows that wire bonds will connect the bonding pads to the externalleads at the periphery of the ceramic (or plastic) package The lower figures showthe periphery layouts including thegull wing in the center diagrams or thel-lead

at bottom left Despite the popularity of the QFP, close inspection of these small, an individual lead might get bent during handing, or, in later processing,

dia-solder shorts might form on the PCB between adjacent legs Further developments

to address this issue are reserved for Chapter 6

5.12 COST OF CHIP MAKING'

5.12.1 Overview

Manufacturing involves many processing steps, and each step adds to the cost of thewafer Therefore, although the cost of a raw unprocessed wafer is only $15 for a 200-

mm wafer, the final processed wafer often costs several thousand dollars after about

100 processing steps The wafer costs depend on the number of masks used, the plexity of the circuits, and the clean room requirements of the process The costincreases with the number of layers in a nonlinear fashion, since each additionalalso increases with smaller feature sizes due to stringent requirements on lithog-raphy and process control However, the cost per chip might then be lower due to thelarger number of chips that can be "squeezed onto the real estate."

com-Table 5.4 shows that lithography is the most expensive aspect of processing.Furthermore, to further reduce line width, lithography is the area where the greatestresearch effort is needed Lithography processes and their associated costs will thuscontinue to be a main focus area in the management of technology

5.12.2Cost of a Single IC

The calculation of the cost of a single IC involves the three main costs in Equation

5.1, modified by the final integrated yield-that is, the number of good dice leavingthe final testing area:

Cost of an individual die on a wafer + cost of testing + cost of packaging (5.1)

s Important·Throughout this section the data are ha.ed on mid_l990s costs A~ tim" goes on, the.

costs will change Also, yields will creep toward the ideal 100% level At the same time, newer designs ofchip will experience lower yields-perhaps nearer 50%-while the manufacturing start-up problems areresolved and debugged The yields shown in the later examples are from Patterson and Hennessy (l996b)

By today's standards these are extremely low, but they would still arise in pilot plants Dataquest's annual

of the best sources for current data Therefore a recent example for a 64-Mb DRAM in the year 2000 isincluded in Appendix 2 of this chapter (Sectiou5.l9)

TABL£ 5.4 Relative Costs of Production Processes

Manufucruringprocessstep

Percentage of wiUerprocessing cost per cm2

(clI.cludcs pllckaging test, anddesign costs)Lithography

The following subsections are based on Patterson and Hennessy (1996b) The point

to always keep in mind is that the "good dice" leaving each step of theIefabricationprocess have to bear the processing costs of all the "bad dice" that were discoveredand rejected alung the way Obviously, all efforts are made to detect these bad dice

as soon as possible Nevertheless, some time, effort, and cost will have gone into ating mistakes For example:

ere-• Perhaps a complete wafer has to be rejected Possible causes include a poorlycalibrated stepper, a faulty vacuum system, chemical impurities in a CVDsystem, or an atmosphere control problem Detecting this larger scale problem

is the function of the test dice on the wafer These are tested as soon as that might already be ruined

pos-• Or, in a more isolated manner.perhaps a dust problem has created several baddice on an otherwise satisfactory wafer

• Or, alternatively, during back-end processing, an otherwise good die has beenmisaligned and damaged

At each step some time and cost will have gone into creating these bad dice.And so this cost has to be shouldered by the good dice Thus the final costs of a singlethe final test

For each processing step, anintermediate die yield can be specified It is usuallystated as a percentage or a value between zero and one So, in Equation 5.2, if 90%

of the dice on the wafer are good dice, by multiplying the "dice per wafer" by 0.9 inthe denominator, it can be seen that the cost of each die is higher than if the yieldwere perfect at 100% or 1

5.12.3 The Cost of an Individual Die on a Wafer

The cost of ao individual die on a perfect wafer involves three main items:

• How many dice fit on a single wafer

• What percentage of these actually work correctly-namely, theprocess die yield

• An allowance for a few test dice on the wafer-not included in the followingequations for simplicity

dice per wafer x die yield

Step Lr caicutate the "dice per wafer."

~[:_1W:d~~~~r] _ [.:!!"_Xwafer diamete~]

The second term allows for the dice around the edge of the wafer Rings of dice at theoutside lose the tip of their outside corners due to the "square peg in a round hole"

saving some time, but still some costs will go onto the waferduring processes such asCVD and diffusion.

The preceding equations are very dependent on wafer size, prompting themove to the 300 rom wafers in the new tabs

The equation gives the following dice per wafer:

• 1 square centimeter die on a 150 mm or 6 inch wafer = 138 dice

• 1 square centimeter die on a 200 mm or 8 inch wafer=269 dice

• 1 square centimeter die on a 300 mm or 12 inch wafer =635 dice

Or for a larger Ie:

• 2.25 square centimeter die on a 150 mm or 6 inch wafer =56 dice

• 2.25 square centimeter die on a 200 mm or 8 inch wafer =107 dice

• 2.25 square centimeter die on a 300 mm or 12 inch wafer =269 diceHowever, note that this calculation gives only themaximumnumber of dice producedifthe fab could achieve 100% yield The next question is: How many of these are good?

Step 2: calculate the "die yield."

[ d] [1 defects per unit areaXdiearea]-.

where the wafer yield accounts for wafers that are so bad they need not be tested.Next, the value of a is an empirical factor corresponding to the number of maskinglevels and the complexity of the manufacturing process being used Typically, intoday's multilevel CMOS processes, a=3

Factory measurements indicate that the defects per unit area lie somewherebetween 0.6 and 1.2 depending on the maturity of the individual processes used.Although these data are empirical rather than analytical, the method assumes that(a) the defects are randomly distributed over the wafer and that (b)the yield isinversely proportional to the complexity of the fabrication process as measured bythe factor a obtained by collecting factory-floor data from CMOS manufacturing

So, for example, using Patterson and Hennessy's (1996b) data, if:

• Thewafer yield is 100% or 1 (for the sakeof simplicity)

• Thedefects per unit area are 0.8 per square centimeter

• Thedie area is 1 square centimeter

Die yield = 1 x (1+[0.8 X 1]13)-3=0.49

From these calculations, it can be concluded that the number of good 1 cm2diceon

a 200 mm (8 inch) diameter wafer reduces from the maximum possible of 269 to areduced figure of (269x 0.49) =only132

Again using 1996 data from Patterson and Hennessy (l996b, see p 63),

manu-depending on the complexity and brand of the microprocessor Therefore, using $3,500

as the average wafer cost, the individual die cost for a 1 ern-die, with 0.8 defects persquare centimeter, on an 8-inch wafer=$3,500 I (269 x 0.49)=$26.55.Before the chip is ready to be used in a computer, further costs or testing, pack-aging, retesting, and shipping must be invested And, of course, these are just the vari·

able costs of the manufacturing processes (see Equation 2.1) The fixed costs of

research and development (R&D), capital expenditures, personnel, and marketingadd considerably more

Note that if the die size is increased to 2.25 square centimeters, the painfulresult for the 200 nun wafer is (107 x 0.24)=only 25 good ones This reducednumber makes the individual costs considerably higher at $14Q-nearly five timeshigher Die designers realize that they cannot easily influence the daily costs of run-ning the factory and controlling the yield from individual CMOS operations Butthey can influence the die area and strive to reduce it by considering the functionsthat are included on the die and the number of110pins

5.12.4 Additional Costs of Testing the Die after Processing

and Slicing

Producing the dice is one set of costs However, the dice must be tested after theCMOS processing and subsequent slicing up procedures to ensure customer satis-have to be tested before it is known they are bad, the good dice must bear this cost.Cost to test a die=.c:0stof testing per hour X average test time

die yield after the test (5.5)

In Patterson and Hennessy's 1996 examples, the quoted testing costs vary from

$50 to $500 per hour depending on the type of test needed Testing time also varieswith die complexity, from 5 to 90 seconds Expensive microprocessors with many pinsneed a longer test with more expensive equipment

5.12.5 Cost of Packaging

The next set of costs involves the back-end packaging of the finished die These costsdie size The cost of the packaging material depends in large part on the desired heatexample, in 1996 data:

• A plastic quad flat pack (PQFP) that will dissipate less than 1 watt of heat from

a 1 crn''dle with 208 pins will cost about $2

• Alternatively, a ceramic pin grid array (PGA) might have 300 to 600 pins for alarger 2 cm2die dissipating much more heat, and the costs will rise to as much

Table 5.5 includes examples:

TABLE 5.5 Package and Test Costs (Courtesy of MIPS Technologies)

Package type Pin count Package cost($) Test time (sec) TeSI cost per hour($)

18.7123.53 103.62

282.35

32.45

181.55157.08318.31

So for one example in detail, the MIPS 4600 has a die area of 77 rnm-.

• For a 95% wafer yield and alpha equal to 3, the die yield comes out to be 0.4787

• The number of dice per wafer, assuming a 200 mm wafer, is 357 Thus, thenumber of good chips per wafer is 171

• In Table 5.6, MIPS 4600 wafers cost $3,200 each

• From each wafer, the price for a good chip is thus $18.71

• The physical package for this chip costs $12

• There are also labor costs: the average testing-time cost per good chip is $0.833and the average packaging-time cost is $0.907 These testing and assembly-time costs add up to $1.74

Altogether, the costs are (18.71 + 12.00 + 1.74)=$32.45 The costs for otherprocessors are much higher The Sun SPARC/6U is given as $31K31 Also these are

manufacturing costs not retail costs.

In future years, costs will be lower-much lower! However, the basic idea will stillhold that each failure makes the good dice cost more and the costs escalate with die size.5.12.6 Conclusion: Relation to Integrated CAD/CAM

It is worth summarizing with some key conclusions from these calculations

5.12.6.1 Design

• With0:=3, the cost of the die is a function of the fourth power of the die area.Therefore, the circuit designer's final choice of die area is dramatically impor-tant to die cost

• This die area depends on a variety of issues including the specific technologybeing used, the number of functions and hence transistors on the chip, and thenumber of pins on the border of the die

5.13.1 HistoricalTrends in the Business

The semiconductor industry has gone through tremendous structural and ical change over the past three decades-since, say, the first 1K DRAM 1103 chip

technolog-Texas, and California, semiconductors became an intensely competitive globalindustry by the 198Os,with Japanese producers steadily usurping the market lead.

In the 1980s theu.s.semiconductor industry's competitive slide was caused inlarge part by persistent manufacturing weaknesses The slide was initially blamed onintensely on process improvements that enabled them to boost chip yield and lowerproduction costs,u.s.firms concentrated on improving chip miniaturization andfunctionality and largely neglected the efficiency of the production process Laggingproductivity and product quality sharply undercut the competitiveness of U.S semi-conductors

By 1985, things looked especially grim for much of the U.S industry Excess rication capacity led to huge industry losses, and many semiconductor start-ups wereforced out of the market Routine production then moved out of the United States tobut also because of excellent production methods The loss of market share and cumu-lative production experience appeared to doom theu.s.semiconductor industry \The competitive picture for theu.s.semiconductor industry is very differenttoday Macher and associates (1998) identify the following "corrective" issues:

fab-• The improvements in quality assurance in all aspects of U.S fabrication

• Many innovative fabrication methods in lithography, etching, and doping

• Important changes in the worldwide demand for semiconductors

• The fact that in the mid-1980s, the United States withdrew from some ICproduct lines-certain memory products were examples; these were products

in which design innovations could not compensate against the superior capital

investments that other countries had made in manufacturing excellence in theirfoundries

The change in U.S quality is dearly shown in the period between May andNovember 1993as measured by comparison with Japanese and Korean tabs (Figure 5.33).This graph is the integrated yield for 0.7 to 0.9 micron CMOS memory chips.Leachman and Hodges (1996) show similar trends for all chip designs, both logic and

at <http://euler.berkeley.edulao.>

Tremendous growth in new applications has also boosted demand for ICs.Memories and PC-oriented microcomponents still take up most of the market, indi-cating the computer industry remains the most important consumer of ICs

In addition, ICs are also at the heart of a burgeoning array of new productsincluding high-definition television (HDTV), interactive multimedia, integratedservices digital networks (ISDNs), cellular and wireless communication systems,automotive electronics, and handheld computers There are major new sources ofmass demand for electronics, computers, and communications products in Asia,Latin America, India, Eastern Europe and other regions At the same time, many ICusers are demanding products tailor-made to their specifications, creating an array

Integrated yield in 0.7-0.9 micron CMOS memory process flow5

is true for both the automobile and the semiconductor industries as they continue togrow alit of the doldrums of the mid-1980s

5.13.2 The $2.5 Billion F8b

Staying ahead in the semiconductor market today is extremely expensive Constantproduct innovation forces companies to invest more heavily in product design and plan-twice as much as it did 10 years ago For example, a high-volume fabrication plant forDRAMs has risen from about $400 million in 1990 to approximately $1 billion today.Part of the cost is due to the fact that semiconductor making is a highly toxicprocess, heavily regulated by environmental and worker protection laws (see Sid-dhaye, 1999) Moving to submicron and large wafer process technologies will drivecosts up even further Over the next five years the scenario for a fabrication plant is:

• 0.13 to 0.18 micron features

-Japan-Korea-USA

• 25,000 wafers per month

• Projected cost of $2.5 billion

Moore has noted (see Leyden, 1997) that other observers in the semiconductorequipment manufacturing field have updated his "law" with respect to manufacturing

be even more dramatic than in the past decade Although anecdotal, this "new law"statesthat the cost of a semiconductor fabrication plant will roughly double every two years.5.13.3Trends and "Alliances" in Advanced Lithography

These investments are daunting even for the deep pockets of Intel, Lucent, and IBM.And the future, beyond these 300 mrn fabs, is even more daunting Therefore, con-emerge This is especially the case of advanced lithography, which, as can be seen inTable 5.4, already accounts for the largest fraction of front-end costs

5.13.3.1 UV and Deep-UV Lithography

The 0.35 micron lines of the late 1990s were generated from UV sources with lengths of 365 nanometers Today's 0.25 micron lines are generated with deep-UV(DUV) sources at 248 nanometers Generally, the cited limit of commercial deep UVwith high-purity glass lenses is a wavelength of 193 nanometers that can producelines 0.13 micron wide, although recent trade reports indicate that 0.08 micron lineductor International, 1998)

wave-5.13.3.2 E UV Lithography

One alliance for future miniaturization is between Intel, Motorola, Advanced MicroDevices, three national laboratories, and several semiconductor equipment manufac-turers Their project is utilizing shorter wavelength, extreme ultraviolet (EUY) lithog-raphy rather than ordinary UV lithography The goal is a 0.03 to 0.1 micron feature size

In EUY, laser generated plasmas produce a source at wavelengths of 13nanometers Highly reflective molybdenum/silicon mirrors, rather than glass lenses,

to create the features (Figure 5.34) For the beta version of the manufacturing

equip-40 wafers per hour

5.13.3.3 X-Ray Lithography

X-ray lithography uses 0.01 to 1 nanometer wavelength sources and has been cessfully used to build devices in the0.02to0.1micron range The process requires asynchrotron to accelerate the high-energy electrons for the source The process isbeing developed at IBM and Sanders (see DeJule, 1999) While the technical feasi-bility has been well proved in dedicated locations, other observers argue that com-mercial fabs-accustomed to DUV lithography-will not rush to install and

Figure5.34 EUVlithography

5.13.3.4 Scattering with Angular Limitation Projection

Electron-Beam Lithography: SCALPEL

In this method, an electron beam is used to direct a high-energy, finely focuseddirectly guided by the data in the CAD files Lucent Technologies' Bell Labs haslimitation projection electron-beam lithography)

Table 5.8 summarizes the values discussed earlier, and Figure 5.35 shows theprojected technologies needed to push BUV to greater limits Advances in resist andmask technologies are also needed to achieve such "deep submicron" levels

TABLE5.8 Lithography Summary

Method

Wavelength (nanometers)

Feature sire(nanometers and micmn~)uv

350 (0.35 micron)

250 (0.25micron) 13Q 180 (0.13 0.18 micron) 30-100 (0.03-0.1 micron) 20-100 (0.02-0.1 micron)

"Siliconcsubslr3te Reduction

Condenser opticsLaser

npn 5.35 Critical level exposure technology potential solutions

(eourte5y of Semiconductor Industry A$sociation, 1998)