21st Century Manufacturing Part 7 pdf

The usual way to measure miniaturization isbythelength,L G,of the polysilicon gate bridging the source and drain region of a tran-sistor.TIlls dimension is shown in later figures.. Pure

some companies-such as Intel, Compaq, Dell, and Gateway-have understood andexploited this new landscape,whereas other companies-such as Apple-have hadmore mixed success in recent years.

The key to building faster, cheaper, smaller, and more powerful computers is to

ance characteristics: more components in a small area increase the circuit's energyefficiency and processing speed The usual way to measure miniaturization isbythelength,L G,of the polysilicon gate bridging the source and drain region of a tran-sistor.TIlls dimension is shown in later figures

A key component of an integrated circuit (IC) is the transistor.Transistors arethe largest member of a family of solid-state devices called "semiconductors." Theyare built from a special class of materials with electrical properties somewherebetween those of conductors and those in insulators Pure semiconductor material

ties called "dopants."

When fabricating an integrated circuit, the transistors, resistors, and capacitors,

as well as their interconnections, are fabricated together-integrated-in a uous substrate of semiconductor material Active circuit elements are formed by

contin-semiconductor substrate material because it has overall cost, performance, and cessing advantages

pro-With each new IC generation, device geometries have become smaller and 10;have become more powerful In 1965, Gordon E Moore, then with Fairchild Corpo-ration but later an Intel cofounder, observed an important trend that was later ele-

transistors that could be integrated on a single die would grow exponentially withtime, roughly doubling every 18 to 24 months Moore correctly anticipated today'sICs, which can hold several millions of transistors on a chip, providing far more func-

functionality A log plot of "dollars per function" over time measured in years shows

a linear decrease In simplest form this means that any chip with a given functionalitywill be about half its original cost in 18 to 24 months

Producing miniaturized devices requires precise and sophisticated design andmicrofabrication Computer aided design tools have significantly improved the pre-cision and level of complexity achievable in circuit layout planning Automatedprocess technologies, advanced clean room systems, and testing equipment havehelped bring chip fabrication to submicron levels The explosion in Ie applications

is also producing a boom in advanced manufacturing equipment It includes

F1pre 5.1 Trends in integrated circuit density (from Digitallntegrated Circuits by

Rabaey, © 1996 Reprinted by permission of Prentice-Hall, Inc., Upper SaddleRiver,NJ)

mechanical polishing equipment to achieve ultraflat surfaces, lasers, and vacuum systems

high-The semiconductor industry is currently focused on producing larger wafersand smaller process geometries Larger wafers reduce raw material costs andincrease chip processing outputs Current state-of-the-art semiconductor manufac-turing systems produce 200 millimeter (8 inch) wafers with 0.25 to 0.35 micron line

beginning to use 0.13 to 0.18 micron processes This will further accelerate the trendshown in Figure 5.2

During the time this book goes to press and gets published, some of the first

300 millimeter (12 inch) wafers will be in production By the year 2010, the

Semi-widths on 450 millimeter (18 inch) wafers Quite simply, these larger wafers meanmore chips per batch, which means lower processing costs per chip, Actually, this isnot entirely new news Henry Ford applied analogous principles to automobile man-

born, Michigan, meant more cars per hour and lower processing costs per batch of

the simple economics are about spreading the fixed costs of the factory, the people,and the manufacturing equipment over a greater number of individual products (see

EnhancementMOSFET/

Bipolartransistor

~~~:~[MESFET

Assuming a 10 mm x to mm chip

and the maximum theoretical yield

FigureS.3 Trends in silicon wafer diameter

5.5 TRANSISTORS

5.5.1 Historical Background

The earliest electronic computers used bulky vacuum tubes resembling short neon

computations and logical functions In the 19408,it took thousands of vacuum tubes

to create the famous computers that occupied several rooms Not surprisingly, thiswas a rather costly and tedious way to go about building a calculating machine

In 1947, vacuum tube computing was rendered obsolete, ahnost overnight,bythetransistor. Three Bell Labs scientists-William Shockley, Walter Brattain, andJohn Bardeen-are credited with a series of inventions that introduced, refined,and then commercially launched the transistor.' Their invention was smaller, faster,and cheaper; handled more complex operations; and generated less heat than its

embedded in a solid piece of semiconductor material Transistors were thus called

"solid-state" devices because electric current nows through a solid semiconductorrather than through a vacuum tube

IIbe importance of the vision of M Kelly, Bell Labs' research director at the time, is also usuallystressed He understood that vacuum tubes were holding back the electronics industry and fostered an

phones were made from vacuum tubes, the device would be as big as the Washington Monument in the

Transistor technology started the microelectronics revolution by making performance inexpensive electronics possible Transistors showed up in a burgeoningarray of electronic products-from rockets to portable radios-throughout the1950s Also, with fewer power, heat, and size constraints, computer designers couldbuild faster, more reliable computers that occupied much less space But properlyconnecting hundreds of transistors with thousands of other electric circuit compo-nents was an enormous design, manufacturing, and performance problem.The problems of interconnecting the discrete devices in computers were over-come with the invention of the integrated circuit in 1958 by Jack Kilby at TexasInstruments This enabled the fabrication of circuit components and their intercon-nections on a single chip.

high-Integrated circuits are classified into analog and digital Analog integrated cuits include a large family of circuits used in power electronics, instrumentation,telecommunications, and optics Digital integrated circuits are usually classified intotwo types, memory and logic chips:

cir-• Memory chips consist of memory cells and associated circuits for address

selec-tion and amplificaselec-tion Process technologies are extremely well developed for

16 and 64 megabyte dynamic random access memories (DRAMs) DRAMsare inexpensive commodity products differentiated by speed, power con-sumption, configuration, and package type From an integrated design and fab-rication viewpoint, specialty DRAMs and video RAMs are the more emergingtechnologies of interest

• Logic chips contain the circuits needed to petform arithmetic, logic, and

con-trot functions central to the microprocessor Application specific integratedcircuits (ASles) are tailored to a customer's particular requirement, asopposed to one of the standard "Intel-inside" microprocessors.Rapid advances in Ie design and process technologies meant that chips could

be made at commercially viable scales by the early 19608.Improvements in turization technology permitted ever-increasing numbers of components to fit onsmaller and smaller chips (Table 5.1)

minia-By1971, a single integrated circuit(Ie)was built that combined logic functions,arithmetic functions, memory registers, and the ability to send and receive data This

device was called the microprocessor It was used in many applications and spurred

TABLE5.1 Trends in Ie Integration Levels

Small scele mtegration

Medium scale integration

Large scale integration

Very large scale integration

Ultra large scale integration

55IMSI

LSI VLSI

2105050105,0005,00010100,000100,000 to 1,000,000

>1,000,000

the factory-floor robotics revolution of the late 19708 (see Figure 1.2) For therobotics industry, the microcorurolter was a cheap and reasonably powerful special-ized control system built around the microprocessor Of course, the microprocessor

also made possible the development of the microcomputer-or the personal

com-puter (PC)

5.5.2 Semiconductors:" Type and ~ Type

A semiconductor is a crystalline material (usually silicon) with electrical properties

and glass Silicon crystallizes in a diamond-shaped lattice, with each atom surrounded

by four other atoms in a tetrahedron The atoms share valence electrons, which giveeach atom a complete valence shell In its pure state, a semiconductor material exhibits

impurities(dopanrs) to the crystal structure of the semiconductor lowers its resistivityand allows current to flow through the material The atomic structure of the dopant

determines whether the resulting material will be "a-type" or "p-type."

• n-type silicon is typically created by doping silicon with phosphorus which hasfive electrons in its outer shell In comparison with the four-electron silicon,

response to a voltage Since most of the conduction is carried by negativelycharged electrons, the material is called n-type

•p-type silicon is typically created by doping silicon with boron Boron has only

three electrons in its outer shell Since all the silicon atoms were nicely anced with four electrons in their outer shell, the presence of the boronintruder creates additional vacancies, or "holes," in the material These holes

bal-fill this hole and, in doing so, leave behind another hole The holes thus seem

tion occurs by way of the positively charged holes, the material is called p-type.

Modifying the concentration of dopants controls the resulting change in conductor conductivity The process of doping semiconductor materials to selec-tively increase their conductivity is fundamental to the manufacture of advancedsemiconductor devices because it makes possible the fabrication of basic circuitsubstructures

semi-Silicon is the material of choice for microelectronics devices because of itsnumerous advantages As one of the most abundant elements on the planet, silicon

manium, the next most popular semiconductor resource Silicon also has critical cessing advantages It easily oxidizes to form silicon dioxide, an excellent insulatoramong circuit components Silicon dioxide is also extremely useful during the fabri-cation process because it is an effective barrier layer during multiple doping opera-

Pre-tiona Gallium arsenide rather than silicon is increasingly used in optoelectronic andhigh-frequency communication devices.

5.5.3The Transistor

The region where p-type and a-type semiconductors meet forms a crucial structureknown as apnjunction (Figure 5.4) Apnjunction is basic to the operation of mostelectronic devices For example, a diode is apnjunction that allows the flow of cur-rent in one direction and blocks it in the opposite direction A bipolar junction tran-sistor(BIT) is made by sandwiching three different semiconductor slices into onesolid block, such that the center slice is of one type and the two outer slices are of theopposite type In effect, this creates twopnjunctions Depending on how the junc-

tions are combined, the transistor is either"npn" or "pnp" (see Figure 5.5) In an npn

transistor, electrons can flow from the emitter(n),across the base(P),to the collector

(rl).More significantly, applying a voltage to the base vigorously rips electrons fromthe emitter and sends them rocketing across the base into thecollector-s-in effect,amplifying the input current to the base The stronger the voltage on the base, thestronger the resulting flow of current through the transistor This amplification ismore utilized in analog devices such as an electric guitar For the ICs in computers,the primary function is the ultrafast switching ability for logic

Figure 5.5 shows a simple sandwichlike npn arrangement By contrast, Figure

5.6 shows the horizontal layout of the field effect transistor (FET) The

termi-nology of the npn transistor-emitter, base, and collector-is now changed to

source, gate,anddrain for the FET To activate the transistor, voltage is applied tothe polysilicon control gate (center of Figure 5.6) Electrons flow out of the source

region (marked n+)through the channel (part of the p-type substrate) and into the

drain (also markedn+).The amount of flow is precisely controlled by the voltageapplied to the gate For the n-type device (NMOS) a positive voltage is applied tothe polysilicon gate' The gate and the p-type substrate form the plates of a capac-itor with the gate oxide (Si02) as the dielectric of the capacitor The reader isreferred to a text such as Rabaey's (1996) for the relationship between the appliedgate voltage and the current flow between the source and the drain

JlIpre SA Schematic structure of apnsemiconductor junction in a silicon

This transistor is off

This Iransistor is on

vouage apphed ro base

Elcrtron flow in

flpre S.6 Basic structure of an a-type NMOS Ie (from Dtgital lmegmted

Circuils by Rablley, <0 1996 Reprinted by permissionof Prentice-Hell, Inc., UpperSaddle Rlver.Nj)

5.5.4MOSFETs as the B ••ic Building Block of the Integrated

Circuit

Metal-oxide semiconductors (MOSFETs) are one type offield effect transistor Theyare the essential building blocks of integrated circuits MOSFETs can be made either

p- or n-type The a-type devices (NMOS) are faster than p-type devices (PMOS) In

practice, the most common type is complementary MOS-type (CMOS) circuits In

this case, a single circuit simultaneously controls pairs of n-type and p-type

transis

-Small or no etcctrou nowIf1

riddoxide(SiO:) Dra!n

Gate Gilteo~id"

p'ficldimpl:Jllt

power-consumption efficencies (see review on P: 4 of Rabaey, 1996) The precise.high-speed switching of MOSFET devices allows transistors to carry out the rapidbinary data processing that lies at the foundation of modem computing.5.5.5The NMOS Transistor

Key terminology includes:

• Substrates, which are p-type fur NMOS

•Active transistor areas, which are n+ in NMOS

• Polysilicon layers for the gate electrode

• Select regions, or field implant regions, which are p+in NMOS

• Field oxide regions of silicon dioxide (SiOz)

• Interconnect layers, usually of aluminum

• Contact layers for interconnections between different layers

• Wells, which are a-type within a p-type substrate for CMOS transistors

The basic structure of anIedepends on the specific transistor technology used

In MOS-based chips, source and drain regions are formed by selectively "doping"

por-device is made up of n+source/drain these n+areas arise from the selective doping of

desired regions in ap-type substrate The conductive gate is made with a thin film ofpolycrystalline silicon (usually referred to as polysilicon) Comparatively thick layers of

p+in NMOS) insulate neighboring n+areas Aluminum layers provide the nections among circuits Copper will increasingly be used for this purpose.5.5.6The CMOS Circuit

intercon-The complementary MOS process is preferred over basic NMOS because it leads tothe creation of more circuits on a chip This is shown in Figure 5.7.The process startswith a p-substrate, which will eventually be doped in certain areas for n+typetransistors (on the left) A mask is used early on in the process to define many addi-

tional n-weIJs-shown on the right-which will then contein p" transistors

5.8 DESIGN

The design of integrated circuits-say, for the embedded systems in cell phones, PDAs,and cameras-is outside the scopeof this book However, typical design levels for suchdevices are shown in Figures 5.8 and 5.9 In Figure 5.8,8 hierarchy is shown that breaksdown a simple IC's description into several levels of abstraction These include:

• The defined global function of the device

• Subfunctions, which must coordinate withthe global goal Therefore iterativehigh-level simulations are needed These iterations are indicated by the feed-back loop at the top of the diagram

• The assembly of these subfunctions into cells or functional blocks

• The creation of specific transistor and circuit layouts that deliver the performance

of the desired functional blocks while stillbeing manufacturable in a standard "feb,"Figure 5.9 is similar but for a more complex device such as a wireless net-worked computer or a wireless PDA Such a device needs three main divisions(shown in three columns) of the design abstraction for (a) analog data processing,(b) digital data processing, and (c) protocols and control (seehttp://bwrc.eecs

berkeley.edu) Some common development tools from Figure 5.9 are listed inTable 5.2 For one of these complex devices, with more than a million transistors,today'sIedesigners target the gate level netlist description in the fifth row of the

Figure 5.8 Design flow,typical of theearly 199Os,for a simple device.Define function

Low-level simulation

of new blocks

Device performancefiles

Check for layout

rule violation

The Destgu Euvironment

TABlE5.2 Design Flow, Typical for Today's More Complex Devleas Shown in Figure 5,9 The Table Was Prepared with the Help of Ahatt Davis,

SynopsysSynopsys (VSS); Cadence (Verilog-XL); MentorGraphics (VHDL)

Cadence (Design Planner, Pillar);Avanl! (Apollo)

Test Insertion and automated test pattern generation

Gate level netlist simulation

-Ana4ogd.~

-pr~

l';lptocolsllM_hol

table.Bycontrast, Figure 5.8 is more typical of the early19908design flow for simplerdevices, where the specific transistor layout is created at the bottomof the diagram.

Integrated circuits are produced in a multistep process The active components of a

wafer Figure 5.3 illustrates that hundreds of individual integrated circuits perhapsmeasuring under 1 cm2each, can be produced simultaneously on a single wafermeasuring 200 mm or 300 mm in diameter Chip arrays are usually identical, but it isalso possible to produce several different designs on one wafer

The formation of silicon wafers and the various lithography and etching steps

are known as front-end processing Wafer fabrication techniques vary widely, but the

basic fabrication process involves thc following series of operations:

• Crystal growing and wafer production. Circular ingots of pure silicon aregrown and sliced into 200-mm or 300-mm wafers

• Oxidation Silicon dioxide (SiOz) is produced by heating the wafer to very high

temperatures in the presence of oxygen

• Photolithography Circuit patterns are formed by masking and etching processes.

• Doping After etching is completed, the exposed surfaces may be doped The n +

orp+dopants are added by ion implantation followed by diffusion processes

• Chemical vapor deposition Thin films of various materials are deposited on

the wafer through several processes (e.g., chemical vapor deposition [CVDJ)

• Interconnect creation Sputtering or evaporation is used to create conducting

circuits between individual transistors and devices

• Testing and packaging IndividuallCs are tested for quality and placed in tective packages that can later be connected on a printed circuit board.The fabrication process is always carried out in a clean room environment, aconfined area in which dust, temperature, and humidity are precisely controlled to

pro-particles per cubic foot in the space (Table 5.3) Reducing dust and other variables isessential to avoid contaminating the chip's circuitry and lowering chip yields

TABLE5.3 Trends in Class Ratings for Clean Rooms

NumberofO a rnrcron panicles per cubic foot

Number of 0.5 micron particles per cubic meter Class 10,000

Class 1,000

Class 100

crass tu

10,000 1.000 10010

350,000 35,000 3,500350

"Class" of clean

c~","c5xnL ~

implant,evaporate,

\ <kpositWafer processing

F1gure 5.10 Iemanufacturing process now

Figure 5,10 shows the process flow and general fabrication sequence for themanufacturing Once again, note that the lithography, etching, and layering steps inthe central parts of the diagram are repeated many times to build up the severallayers indicated in the schematics of Figures 5.6 and 5.7

Once all active components and circuits are fully formed, the wafer is tected with a layer of insulating dielectric film Finally, a patterned passivation layer

pro-bonding wires link to theIepackage during the phase known asback-end cessing Eventually, the chips are assembled onto printed circuit boards (seeChapter 6)

pro-5.8 SEMICONOUCTOR MANUFACTURING II, NMOS'

Figure 5.11 shows the multilayer structure of an NMOS circuit It is useful to

sum-as lithography are considered in Section 5.10 For the new student in this area, it isimportant to emphasize that Steps 3 through 6 are not concerned with creating thetransistor itself but with defining the peripheral areas that will contain thep+fieldimplants and field oxide on the very outside of Figure 5.6 Importantly, and by con-trast, the inner channels that will eventually be the{n+pn+source-gate-drain]

3lmpQrtant: By far the most common manufacturing method today is CMos.In CMOS both

NMOS and PMOS transistors are produced in tandem After the fint oxidation and nitriding steps, the

n-wells are formed so that at high magnification, the wafer will have a checkerboard appearance turing then involves "bopping back and forth" between the p-sebstrate and the n-weU shown in Figure 5.7

Manufac-To a new ~tudent in manufacturing, thiS alternation between the n-type and p·type transistors can get

Figure 5.11 NMOS: wafer on the left and corresponding masks on the right (from

lntroduetio" to Micro<:/eclric Fabrication by Jaeger, © 1988 Reprinted by

permission of Prentice-Hall,Inc,Upper Saddle River, NJ)

transistor areas remain covered and protected by the inert, hardened photoresist.Work does not begin on these areas until Step 8

Step 1: A standard wafer ofp-type silicon with specific resistance is scrupulously

Pho~p~orusUf.a~enic

(Si02). This creates a thin layer-sometimes called the pad oxide-c-on top

of the substrate material

Step 2: A layer of silicon nitride is added using chemical vapor deposition (CVD).Step 3: Ultraviolet-light-sensitive photoresist is applied to the wafer A mask pat-tern is shown on the top right of Figure 5.11a for the outerp+fieldimplants and field oxide areas It is shown as a simple rectangle of fourthin lines The lines are transparent, but every other region of the mask,including the center of the rectangle, is opaque The UV light only passesthrough the lines of the mask, and it deliberately damages the photoresistinto this pattern The damaged photoresist is then sloughed away in chem-ical solutions This leaves a rectangular pattern of four connectedtrenches with naked silicon nitride at the bottom In Steps 4 and 5, the sil-icon nitride and silicon dioxide at the bottom of these trenches are etchedaway

Step 4: The wafer is dry etched with a plasma process to create the vertical-walltrenches Speaking colloquially, the NMOS wafer under a microscope willnow look like Manhattan; tall buildings still protected by oxide/nitride,

substrate Following the etching process, these avenues are then doped withboron to formselect p+type regions (Figure 5.11b)

Step 5: Boron, a p-type dopant, is ion-implanted into these naked avenues The

nation of ion-implantation and diffusion creates thep+field implantregions shown on the left and right of Figures 5.6 and 5.11b Why is this nec-essary? It means that the transistor-in the center part of the figure-is

"boxed in." Electrons will be constrained to flow from the source to the

Thep+regions are also called thechannel-stop implants.

Step 6: Thermal field oxidation then covers thesep+regions with the thick Si02

layers shown at the left and right of Figure 5.11c

Step 7: Let's pause for a moment! The p" areas covered in the thick layer ofSi02

are rather like "sidewalls" that establish the boundaries of the transistor.Work can now begin on the central area where the source, gate, and drainwill be built up

Step 8: Recall from Step 3 that the central area was leftprotected by the sist and still has the oxide/nitride sandwich on it from Steps 1 and 2 This

Mask #2

Mask #3

Mask #4

Mask #5

F1pre 5.12 NMOSprocessing stepsthat correspond to the previous figure (from

introduction to Microelectric FabricationbyJaeger, ©1988.Reprintedby

permission of Prentice-Hall, Inc., Upper Saddle River, NJ).

Step 10: Further doping is done with boron, which can penetrate through this thin

oxide layer, to adjust the necessary threshold voltage of the gate region

Step 11: Polysilicon is deposited using CVD to create the contact for the gate itselfFigure 5.11c represents the wafer at this point in the proceedings Also, theprocesshas reached the lower left column of the box diagrams in Figure5.12

Step 12: The second photolithography mask is then used to create the precise and

delicate features in the central transistor region This is shown as the two