Microengineering MEMs and Interfacing - Danny Banks Part 7 ppt

102 Microengineering, MEMS, and Interfacing: A Practical Guide design layer names, mask serial number, etc., it is normally necessary to create it as complex polygons.. The way around th

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100 Microengineering, MEMS, and Interfacing: A Practical Guide box for setting up display (user) units and their relationship to lambda and the internal units (half millimicrons, i.e., one internal unit will be 0.5 nm)

It is usually possible to create a design using either micrometers or lambda units The latter are generally used for circuitry and not for micromachined devices or structures When moving to a new IC fabrication process with a smaller feature size, the value of lambda is scaled appropriately so that the design need not be recreated from scratch The software may offer an option

to indicate which parts of a design can be scaled and which cannot (e.g., bonding pads) In such a case, it may be possible to create scalable designs that combine microstructures with circuitry, but the process is generally difficult to implement

4.3.1.2 Further Caveats

One additional thing to be aware of is the use of hidden or reserved layer names that the software may use for its own purposes This will be software dependent and will restrict the use of names within a design created using that package For instance, “background” may be a reserved name allowing one to vary the back-ground of the drawing area

4.3.2 G RAPHICS

One difference between a layout editor and a normal drawing software is the scale over which the design is drawn A layout will range from features as small

as 1 µm up to a design that covers an entire wafer (100 mm) — a difference of 100,000 times The layout editor software should provide an option that will prevent it from trying to draw very fine detail when a large area of the design is being viewed; this may be automatic in some packages The normal approach is

to prevent the software from attempting to draw anything that takes up less than

a specified number of pixels on the screen, otherwise it will take the machine an unreasonable length of time to draw complex designs

The layout editor will do its best to make everything visible on the screen This can lead to problems when trying to determine size or the distance between two items because one pixel may be much larger than one user unit, depending

on the scale at which the design is being viewed There will normally be a ruler

or cursor system in the software package to allow distances to be measured

Units in Summary

Internal units Used by the software

User units Used to create the design, usually in micrometers,

and usually set to about 1000 internal units

Lambda units Half the minimum feature size

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Mask Design 101

In order to get an accurate measurement, the design should be viewed at an appropriate scale — normally, the highest possible magnification

4.3.3 G RID

A grid is a useful feature of any drawing package and more or less indispensable for mask design Layout editors generally feature grids that can be turned on or off (i.e., displayed or hidden) with variable mesh dimensions Points and drawing elements will be locked to the intersections of the gridlines (i.e., snap to grid), and

it is often useful to set the minimum spacing on the grid to the minimum feature size being employed The usefulness of the grid cannot be overemphasized Polygons can also be edited by specifying the coordinates of their vertices (corners), as illustrated in Figure 4.3 Very complex polygons can be created in this manner, but a lot of preplanning is required Because MEMS normally involve fairly complex polygons, it is worth planning the coordinates that these will require beforehand

4.3.4 T EXT

Most packages allow text to be typed onto one layer of the design This will not normally appear on the mask itself when fabricated Most layout editors do not allow text to be entered in such a manner that it will appear on the mask (sometimes it is supplied as an advanced option) When placing text on a mask

FIGURE 4.3 Setting vertices of a polygon by editing points directly.

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102 Microengineering, MEMS, and Interfacing: A Practical Guide design (layer names, mask serial number, etc.), it is normally necessary to create

it as complex polygons

4.3.5 O THER F EATURES

Other things that may help when creating a design include: turning different layers on or off to make them accessible or inaccessible for modification and options for selecting an item to be modified These will obviously be software specific

4.3.6 M ANHATTAN G EOMETRY

Manhattan geometry refers to a restricted form of layout in which designs may only be composed of horizontal and vertical lines Complex polygons may also

be restricted This is usually a feature of older CAD packages and is somewhat restrictive in MEMS designs The way around this is to put simple rectangles up against one another to create complex shapes: any two polygons on the same layer that touch or overlap will appear as a single contiguous area on the mask Diagonal bars can be approximated by an array of overlapping squares or rect-angles Tools for placing arrays of design features (either simple polygons or more complex structures) are a common component of layout editors Figure 4.4 illustrates this

FIGURE 4.4 Creating complex polygons from simple squares and rectangles.

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Mask Design 103

4.4 DESIGN

If the concept of creating a design by depositing and machining successive layers

is comprehended, the process of designing the required masks should be straight-forward It only requires the necessary mental visualization to see how the two-dimensional mask designs relate to the final structure

In order to explain the basic concepts of mask design, the device outlined in Figure 4.5 will be used as an example It is not intended to be a real device but

is a simple design that could represent a microbiosensor There are a set of exposed

Graphics and Drawing Hints

• Use the grid

• Plan the design in advance, including the coordinates for complex shapes

• Measure distances and sizes, and make sure that the display is zoomed in as much as possible

• Adjacent or overlapping polygons on the same layer will become a single contiguous shape on the mask

• Most packages allow text to be placed on the design but it will not appear on the mask (check the manual or a CIF file to see if this is true for a particular package)

FIGURE 4.5 Electrode layout for the device used in the examples in this chapter These are metal electrodes; the passivation layer is etched to create the electrode pattern illus-trated This is to be sited at the center of a 5 × 5 mm die Each electrode is to be connected

to a 180-µm square bond pad at the edge of the die.

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104 Microengineering, MEMS, and Interfacing: A Practical Guide metal electrodes at the center of a 5 × 5 mm silicon die (chip) The large central electrode represents a reference (ground or 0 V) electrode The two long thin electrodes to either side could be some form of active sensor, possibly function-alized by electroplating with a conductive polymer combined with a bioactive compound The four electrodes at the top could be used for electrical impedance measurements (two to apply a signal and two to sense it) A small drop of the sample could be placed in the center of the chip and bonding pads at the edge

of the chip could connect it with appropriate circuitry

The design consists of a silicon substrate and three layers: an insulating layer (CVD or thermal oxide) deposited on the wafer but not patterned, a metal layer (nominally M1) to form the electrodes’ bonding pads and conducting tracks between them, and a top insulating layer of oxide (e.g., PECVD) that would be patterned to open vias (holes) above the electrodes and bonding pads so that electrical connections could be made to these; this layer would nominally be V1 This is a three-mask process — one (A1) to cut alignment marks into the silicon substrate, M1 to pattern the metal, and V1 to pattern the vias The mask set will be called EX1 and will employ a 4-µm minimum feature size (although such a simple design could be created with a larger minimum feature size).*

A number of different structures or cells will be created and stitched together

to create a wafer-sized design

4.4.1 T HE F RAME AND A LIGNMENT M ARKS

Each individual chip design will be drawn within a frame This is usually supplied

by the foundry or laboratory that will manufacture the devices and will normally include the following:

• Scribe lane

• Alignment marks

• Test structures

• Layer identification marks

• Mask set number

• Other marks required by the fabrication facility

If the design is being created for in-house fabrication, the absolute minimum requirements are alignment marks and a scribe lane, which may be useful, if only

to assist in layout

4.4.1.1 Scribe Lane

The scribe lane is an area around the chip that has to be kept free of circuitry

or components This defines the grid along which the wafer will be cut into

* The example uses Electric and the mocmosold technology file (library) that it is supplied with; an old double-metal CMOS process that was available through MOSIS [1] The design will not be suitable for fabrication through MOSIS, and the library itself is no longer supported by MOSIS It was chosen only because it has a relatively large value of lambda For this example, the technology

is not important.

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Mask Design 105

individual dies Options for dicing up the wafer include the use of a dicing saw,

a diamond-tipped scribe (which scores a groove across the surface of the wafer where it will be broken), and laser cutting (which burns a series of pits along the scribe lane) All these methods of dicing have disadvantages when dealing with wafers that incorporate micromechanical structures The saw and scribe induce mechanical vibration that can damage components, and the laser induces thermal damage and can eject material over the surface of the dies It may be worth considering incorporating a chemical (e.g., KOH) dicing step for some devices

In the example (Figure 4.6), a 200-µm-wide scribe lane is created on all three layers in use This is done by creating four 100-µm-wide rectangles on each layer and placing them as illustrated The outside dimensions of this are 5000 × 5000

µm, so the area available for the design has been reduced to 4800 × 4800 µm This structure has been named, curiously enough, scribelane

4.4.1.2 Alignment Marks

In order to line up one layer with a previously fabricated layer when performing photolithography, it is necessary to incorporate appropriate marks into the mask design The foundry producing the devices will probably have standard marks that should be used Furthermore, these may need to be placed in a specific position on the design Use the standard alignment marks if available It is not unknown for process technicians and engineers to attempt to align parts of the design itself with the alignment marks appearing in the previous layer when dealing with unfamiliar designs

A simple alignment-mark scheme consisting of squares and a cross is shown

FIGURE 4.6 “ scribelane ”

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Mask Design 107

performing the alignment it is clear which mark is being aligned with which (the

frame appears on all layers)

Masks A1 and M1 (A1 defines the alignment marks, etc., that will be

etched into the silicon) are light field (i.e., will be opaque where a closed or

opaque polygon appears in the design) Mask V1 is dark field (i.e., will be

transparent where a closed or opaque polygon appears in the design) M1 will

be aligned to A1, and V1 will then be aligned to M1 The alignment marks

consist of a small M1 square on the left that will be aligned to the larger A1

square and a larger V1 square that will later be aligned to the smaller M1

square on the right The squares are 20 µm and 16 µm on a side (large and

small, respectively) This may imply a ±2-µm alignment error, but it will be

influenced by various factors, such as over- or under-etching and the ability

of the person performing the alignment to accurately place one square inside

another Although this range of error has been taken into account in the rest

of the design (note the V1–M1 overlap elsewhere), it should be possible to

achieve a much smaller error than this

4.4.1.3 Test Structures

The foundry may wish to incorporate a variety of test structures within the design

For CMOS processes, these may include electronic components (transistors, ring

counters, etc.) to verify conformation to process specifications The example only

includes a set of bars as the test structure (Figure 4.9)

FIGURE 4.9 Example test structures.

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108 Microengineering, MEMS, and Interfacing: A Practical Guide

A 4-µm minimum feature size has been chosen The test structure consists

of a set of 4-µm bars, spaced 4 µm and 8 µm apart, on each layer These will

enable monitoring of the process to check for such things as:

• Correct exposure

• Under- or over-etching

• Asymmetry between x and y axes (and, thus, the vertical and horizontal

bars)

4.4.1.4 Layer and Mask Set Identification Marks

A number of different projects are normally in progress at any one time in a

fabrication facility (fabs) For this reason, it is useful to be able to pick up a wafer

and determine how far it has progressed and to which particular project it belongs

Therefore, each layer should have the layer name written on it, as illustrated

in Figure 4.10a, and a name or number to identify the mask set, as shown in

Figure 4.10b Note that these have been drawn onto each layer as polygons

4.4.1.5 Putting It All Together

These structures now need to be combined into a single structure that can be used

as the basis of any chip design To do this, a new structure, or a frame, is created

and maskname are then placed appropriately (Figure 4.11b) The alignment marks

FIGURE 4.10 (a) “layernames ,” (b) “ maskname ”

(a) DK3182_C004.fm Page 108 Friday, January 13, 2006 10:59 AM

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110 Microengineering, MEMS, and Interfacing: A Practical Guide

FIGURE 4.11 (Continued)

(b)

(c)

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Mask Design 111

and test structures have been placed in each corner of the scribe lane structure, and the layer and mask names have been placed at the center in the bottom The software displays these structures as named boxes

It is possible to view the full design by pushing down (or expanding) on the hierarchy (or instances; each box containing a structure being termed an instance, although the terminology is somewhat software dependent) This has been done

of the design

It is clear that a design hierarchy is being built up, as illustrated in Figure 4.12 Note that if the mask name is changed in maskname, then the change will be reflected in all instances of the frame

4.4.1.6 Another Way to Place Alignment Marks

Notice that the more structures that need to be placed in the frame, the less room there is available for the design In the example being pursued in this section, it

is known that the alignment will be performed by a mask aligner that will view alignment structures that exist along the centerline of the mask So it is only necessary to place alignment marks in this area

To do this, a special frame will be created This will have an alignment mark

at the center and a number of arrows to guide the eye to its position It is only necessary to create one arrow structure (Figure 4.13a) This is placed with the correct orientation into alignmentframe and duplicated using the array place-ment command The resulting structure is shown in Figure 4.13b and Figure 4.13c

4.4.2 T HE D EVICE

The sensor design illustrated in Figure 4.5 is shown as a layout in Figure 4.14

(design) The frame structure has not been used, as the alignmentframe structure, discussed in the previous section, will be used instead The area of the device has been defined by the use of scribelane, and a set of bonding pads have been placed near the edges of the design

FIGURE 4.12 Design hierarchy for the example “frame ” structure.

Frame

Test

Align

Layernames

Maskname

Scribelane

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