MEMORY, MICROPROCESSOR, and ASIC phần 4 ppsx

The main features of CHEI and FN tunneling for n-channel Flash memory cell and alsoCHEI and BBHE injection for p-channel Flash memory cell are compared in Tables 5.1 and 5.2.. three diff

Flash Memories

Solving Eqs 5.22 and 5.24 with the assumption that only electrons at the Fermi level contribute to the

current yields the Fowler-Nordheim formula for the tunneling current density J tunnel at high electric field:

(5.25)This equation can also be expressed as

(5.26)where a and ß are Fowler-Nordheim constants The value of a is in the range of 4.7×10-5 to 6.32×10-

7 A/V2 and ß is in the range of 2.2×108 to 3.2×108 V/cm.47

The barrier height and tunneling distance determine the tunneling efficiency Generally, the barrierheight at the Si-SiO2 interface is about 3.1 eV, which is material dependent This parameter is determined

by the electron affinity and work function of the gate material On the other hand, the tunnelingdistance depends on the oxide thickness and the voltage drop across the oxide As indicated in Eq 5.26,the tunneling current is exponentially proportional to the oxide field Thus, a small variation in theoxide thickness or voltage drop would lead to a significant tunneling current change Figure 5.22Shows the Fowler-Nordheim plot which can manifest the Fowler-Nordheim constants a and ß TheSi-SiO2 barrier height can be determined based on this FN plot by quantum-mechanical (QM)modeling.48

5.4.3 Comparisons of Electron Injection Operations

As mentioned in the above section, there are several operation schemes that can be employed forelectron injection, whereas only FN tunneling can be employed for ejecting electrons out of thefloating gate Owing to the specific features of the electron injection mechanism, the utilization of anelectron injection scheme thereby determines the device structure design, process technology, andcircuit design The main features of CHEI and FN tunneling for n-channel Flash memory cell and alsoCHEI and BBHE injection for p-channel Flash memory cell are compared in Tables 5.1 and 5.2

5.4.4 List of Operation Modes

The employment of different electron transport mechanisms to achieve the programming and eraseoperations can lead to different device operation modes Typically, in commercial applications, there are

FIGURE 5.22 Fowler-Nordheim plot of the thin oxide.

three different operation modes for n-channel Flash cells and two different operation modes for channel Flash cells In the n-channel cell, as shown in Fig 5.23, the write/erase operation modesinclude: (1) programming operation with CHEI and erase operation with FN tunneling ejection atsource or drain side,6–8,49–61 as shown in Fig 5.23(a), usually referred as NOR-type operation mode; (2)programming operation with FN tunneling ejection at drain side and erase operation with FN tunnel-ing injection through channel region,62–70 as shown in Fig 5.23(b), usually referred as AND-typeoperation mode; and (3) programming and erase operations with FN tunneling injection/ejectionthrough channel region,71–78 usually referred as NAND-type operation mode As to the p-channel cell,

p-as shown in Fig 5.24, the write/erp-ase operation modes include: (1) programming operation withCHEI at drain side and erase operation with FN tunneling ejection through channel region,9 as shown

in Fig 5.24(a); and (2) programming operation with BBHE at drain side and erase operation with FNtunneling injection through channel region,10,11 as shown in Fig 5.24(b)

These operation modes not only lead to different device structures but also different memory arrayarchitectures The main purpose of utilizing various device structures for different operation modes isbased on the consideration of the operation efficiency, reliability requirements, and fabrication procedures

In addition, the operation modes and device structures determine, and also are determined by, thememory array architectures In the following sections, the general improvements of the Flash devicestructures and the array architectures for specific operation modes are described

5.5 Variations of Device Structure

5.5.1 CHEI Enhancement

As mentioned above, alternative operation modes are proposed to achieve pervasive purposes and variousfeatures, which are approached either by CHEI or FN tunneling injection Furthermore, it is indicatedthat over 90% of Flash memory product ever shipped are the CHEI-based Flash memory devices.79 Withthe major manufacturers’ competition, many innovations and efforts are dedicated to improve the perfor-mance and reliability of CHEI schemes.50,53,56,57,61,80–83 As described in Eq 5.11, an increase in the electricfield can enhance the probability of the electrons gaining enough energy Therefore, the major approach

to improve the channel hot electron injection efficiency is to enhance the electric field near the drain

TABLE 5.1 Comparisons of Fowler-Nordheim Tunneling and Channel Hot Electron

Injection as Programming Scheme for Stacked-Gate Devices

TABLE 5.2 Comparisons of Band-to-Band Tunneling Induced Hot Electron

Injection and Channel Hot Electron Injection as Programming Scheme for

Stacked-Gate Devices

Flash Memories

side One of the structure modifications is utilizing the large-angle implanted p-pocket (LAP) aroundthe drain to improve the programming speed.56,57,60,83 LAP has also been used to enhance the punch-through immunity for scaling down capability.50,53 As demonstrated in Fig 5.13, the device with LAPhas a twofold maximum electric field of that in the device without LAP structure According to ourprevious report,83 additionally, the LAP cell with proper process design can satisfy the cell performancerequirements such as read current and punch-through resistance and also reliable long-term chargeretention Besides, the utilization of the p-pocket implantation can achieve the low-voltage operationand feasible scaling-down capability simultaneously

5.5.2 FN Tunneling Enhancement

From the standpoint of power consumption, the programming/erase operation based on the FN tunnelingmechanism is unavoidable because of the low current during operation As the dimension of Flash memorycontinues scaling down, in order to lower the operation voltage, a thinner tunnel oxide is needed However,

it is difficult to scale down the oxide thickness further due to reliability concerns There are two ways toovercome this issue One method is to raise the tunneling efficiency by employing a layer of electroninjector on top of the tunnel oxide Another method is to improve the gate coupling ratio of the memorycell without changing the properties of the insulator between the floating gate and well

FIGURE 5.23 Different n-channel Flash write/erase operations: (a) programmming operation with CHEI at drain side and erase operation with FN tunneling ejection at source side; (b) programming operation with FN tunneling ejection at drain side and erase operation with tunneling injection through channel region; and (c) programming and erase operations with FN tunneling injection/ejection through channel region.

The electron injectors on the top of the tunnel oxide enhance the electric field locally and thus thetunneling efficiency is improved Therefore, the onset of tunneling behavior takes place at a loweroperation voltage There are two materials used as electron injectors: polyoxide layer84 and silicon-richoxide (SRO) layer.85 The surface roughness of the polyoxide is the main feature for electron injectors.However, owing to the properties of the polyoxide, the electron trapping during write/erase operationlimits the application for Flash memory cells On the other hand, the oxide layer containing excesssilicon exhibits lower charge trapping and larger charge-to-breakdown characteristics These siliconcomponents in the SRO layer form tiny silicon islands The high tunneling efficiency is caused by theelectric field enhancement of these silicon islands Lin et al.47 reported that the Flash cell with SROlayer can achieve the write/erase capability up to 106 cycles However, the charge retentivity of theFlash memory cell with electron injector layers would be poorer than the conventional memory cellbecause the charge loss is also aggravated by the enhancement of the SRO layer Thus, the stacked-gatedevice with SRO layer was also proposed as a volatile memory cell which can feature a longer refreshtime than that in the conventional DRAM cell.86

5.5.3 Improvement of Gate Coupling Ratio

Another way to reduce the operation voltage is to increase the gate coupling ratio of the memory cell.From the description in the Section 5.4, the floating gate potential can be increased with an increasedgate coupling ratio, through an enlarged inter-polysilicon capacitance For the sake of obtaining a largeinterpoly capacitance, it is indispensable to reduce the interpoly dielectric thickness or increase theinterpoly capacitor area However, the reduced interpoly dielectric thickness would lead to charge lossduring long-term operation Therefore, a proper structure modification without increasing the effec-tive cell size is necessary to increase the interpoly capacitance It was proposed to put an extendedfloating gate layer over the bit-line region by employing two steps of polysilicon layer deposition.68,87

Such device structure with memory array modifications would achieve a smaller effective cell size and

a high coupling ratio (up to 0.8) Shirai et al.88 proposed a process modification to increase the effectivearea on the top surface of the floating gate layer This modified process, which forms a hemispherical-grained (HSG) polysilicon layer, can achieve a high capacitive coupling ratio (up to 0.8) However, thecharge retentivity would be a major concern in considering the material as the electric injector

FIGURE 5.24 Different p-channel Flash write/erase operations: (a) programming operation with CHEI at drain side and erase operation with FN tunneling ejection through channel region; and (b) programming operation with BBHE at drain side and erase operation with FN tunneling injection through channel region.

1986.89 By using this contactless bit-line concept, the memory cell has a 34% size reduction.

FIGURE 5.25 (a) Schematic top view and cross-section of the NOR-type Flash memory array; and (b) schematic top view and cross-section of the NAND-type Flash memory array.

5.6.2 AND-Type Families

Another modification of the NOR-type array accompanied by a different operation mode is the type array In the NOR-type array, the CHEI is used as the electron injection scheme However, owing tothe considerations of power consumption and series resistance contributed by the buried bit line/source,both the programming and erase operations utilize FN tunneling to eliminate the above concerns Someimprovements and modifications based on the NOR-type array have been proposed, including DIvided-bitline NOR (DINOR) proposed by Mitsubishi Corp.,65,68 Contactless NOR (AND) proposed by HitachiCorp.,64,66 Asymmetrical Contactless Transistor (ACT) cell by Sharp Corp.,69 and Dual String NOR(DuSNOR) by Samsung Corp.70 and Macronix, Inc.67 The DINOR architecture employs the main bit-lineand sub-bit-line configuration to reduce the disturbance issue during FN programming The AND andDuSNOR structures consist of strings of memory cells with n+ buried source and bit lines String-select andground-select transistors are attached to the bit and source lines, respectively In the DuSNOR structure, asmaller cell size can be realized because every two adjacent cell strings share a source line Although a smallercell size can be obtained utilizing the buried bit line and source line, the resistance of the buried diffusionline would degrade the read performance The read operation consideration will be the dominant factor indetermining the size of a memory string in the AND and DuSNOR structures

AND-5.6.3 NAND-Type Array

In order to realize a smaller Flash memory cell, the NAND structure was proposed in 1987.90 As shown

in Fig 5.25(b), the memory cells are arranged in series It was reported that the cell size of the NANDstructure is only 44% of that in the NOR-type array under the same design rules The operation mecha-nisms of a single memory cell in the NAND architecture is the same as NOR and AND architectures.However, the programming and read operations are more complex Besides, the read operation speed islower than that in the NOR-type structure because a number of memory cells are connected in series.Originally, the NAND structure was operated with CHEI programming and FN tunneling throughthe channel region.90 Later on, edge FN ejection at drain side was employed.62,63 However, owing toreliability concerns, operations utilizing the bipolarity write/erase scheme were then proposed toreduce the oxide damage.71–78 Owing to the memory cells in the NAND structure being operated by

FN write and erase, in order to improve the FN operation efficiency and reduce the operation voltage,the booster plate technology on the NAND structure was proposed by Samsung Corp.77

5.7 Evolution of Flash Memory Technology

In this section, as in Table 5.3, the development of device structures, process technology, and arrayarchitectures for Flash memory are listed by date The burgeoning development in Flash memorydevices reveals a prospective future

TABLE 5.3 The Development of the Flash Memory

Flash Memories

TABLE 5.3 (continued) The Development of the Flash Memory

5.8 Flash Memory System

5.8.1 Applications and Configurations

Flash memory is a single-transistor memory with floating gate for storing charges Since 1985, the massproduction of Flash memory has shared the market of non-volatile memory The advantages of highdensity and electrical erasable operation make Flash memory an indispensable memory in the applica-tions of programmable systems, such as network hubs, modems, PC BIOS, microprocessor-based sys-tems, etc Recently, image cameras and voice recorders have adopted Flash memory as the storagemedia These applications require battery operation, which cannot afford large power consumption.Flash memory, a true non-volatile memory, is very suitable for these portable applications becausestand-by power is not necessary

In the interest of portable systems, the specification requirements of Flash memory include somespecial features that other memories (e.g., DRAM, SRAM) do not have; for example, multipleinternal voltages with single external power supply, power-down during stand-by, direct execution,simultaneous erase of multiple blocks, simultaneous re-program/erase of different blocks, preciseregulation of internal voltage, and embedded program/erase algorithms to control threshold voltage.Since 1995, an emerging need of Flash memory is to increase the density by doubling the number

of bits per cell The charge stored in the floating gate is controlled precisely to provide multi-levelthreshold voltages The information stored in each cell can be 00, 01, 10, or 11 Using multi-levelstorage can decrease the cost per bit tremendously The multi-level Flash memories have two additionalrequirements: (1) fast sensing of multi-level information, and (2) high-speed multi-level programming.Since the memory cell characteristics would be degraded after cycling, which leads to fluctuation ofprogrammed states, fast sensing and fast programming are challenged by the variation of thresholdvoltage in each level

Another development is analog storage of Flash memory, which is feasible for image storage andvoice record The threshold voltage can be varied continuously between the maximum and minimumvalues to meet the analog requirements Analog storage is suitable for recording the information thatcan tolerate distortion between the storing information and the restored information (e.g., image andspeech data)

Before exploring the system design of Flash memory, the major differences between Flash memoryand other digital memory, such as SRAM and DRAM, should be clarified First, multiple sets ofvoltages are required in Flash memory for programming, erase, and read operations The high-voltagerelated circuit is a unique feature that differs from other memories (e.g., DRAM, SRAM) Second, thecharacteristics of Flash memory cell are degrading because of stress by programming and erasing Thecontrol of an accurate threshold voltage by an internal finite state machine is the special function thatFlash memory must have In addition to the mentioned features, address decoding, sense amplifier, andI/O driver are all required in Flash memory The system of Flash memory, as a result, can be regarded

as a simplified mixed-signal product that employs digital and analog design concepts

Figure 5.26 shows the block diagram of Flash memory The word-line driver, bit-line driver, andsource-line driver control the memory array The word-line driver is high-voltage circuitry, whichincludes a logic X-decoder and level shifter The interface between the bit-line driver and thememory array is the Y-gating Along the bit-line direction, the sense amplifier and data input/outputbuffer are in charge of reading and temporary storage of data The high-voltage parts include charge-pumping and voltage regulation circuitry The generated high voltage is used to proceed withprogramming and erasing operations Behind the X-decoder, the address buffer catches the address.Finally, a finite state machine, which executes the operation code, dictates the operations of thesystem The heart of the finite state machine is the clocking circuit, which also feeds the clock to atwo-phase generator for charge-pumping circuits In the following sections, the functions of eachblock will be discussed in detail

Flash Memories

5.8.2 Finite State Machine

A finite state machine (FSM) is a control unit that processes commands and operation algorithms Figure5.27(a) demonstrates an example of an FSM Figure 5.27(b) shows the details of an FSM The commandlogic unit is an AND-OR-based logic unit that generates next-state codes, while the state register latchesthe current state The current state is related to the previous state and input state State transitions followthe designated state diagram or state table that describe the functionality to translate state codes intocontrolling signals that are required by other circuits in the memory The tendency to develop Flash

FIGURE 5.26 Block diagram of the Flash memory system.

FIGURE 5.27 (a) The hierarchical architecture of a finite state machine; and (b) the block diagram of a finite state machine.

memories goes in the direction of simultaneous program, erase, and read in different blocks The globalFSM takes charge of command distribution, address transition detection (ATD), and data input/out-put The address command and data are queued when the selected FSM is busy The local FSM dealswith operations, including read, program, and erase, within the local block The local FSM is activatedand completes an operation independently when a command is issued The global FSM manages thetasks distributing among local FSMs according to the address The hierarchical local and global FSMscan provide parallel processing; for instance, one block is being programmed while the other block isbeing erased This feature of simultaneous read/write reduces the system overhead and speeds up theFlash memory One example of the algorithm used in the FSM is shown in Fig 5.28 The global FSMloads operating code (OP code) first; then the address transition detection (ATD) enables latch of theaddress when a different but valid address is observed The status of the selected block is checked if thecommand can be executed right away, whereas the command, address, and/or data input are stored inthe queues The queue will be read when the local FSM is ready for excuting the next command Theoperation code and address are decoded Sense amplifiers are activated if a read command is issued.Charge-pumping circuits are back to work if a write command is issued After all preparations aremade, the process routine begins, which will be explained later Following the completion of theprocess routine, the FSM checks its queues If there is any command queued for delayed operation, thelocal FSM reads the queued data and continues the described procedures Since these operations areinvisible to the external systems, the system overhead is reduced.

FIGURE 5.28 The algorithims of a finite state machine for simultaneous read/write feature.

Flash Memories

The process routine is shown in Fig 5.29 The read procedure waits for the completion signal of thesense amplifier, and then the valid data is sent immediately The programming and erasing operationsrequire a verification procedure to ascertain completion of the operation The iteration of program-verification and erase-verification proceeds to fine-tune the threshold voltage However, if the verificationtime exceeds the predetermined value, the block will be identified as a failure block Further operation

to this block is inhibited Since the FSM controls the operations of the whole chip, a good design ofthe FSM can improve the operational speed

5.8.3 Level Shifter

The level shifter is an interface between low-voltage and high-voltage circuits Flash memory requireshigh voltage on the word line and bit line during programming and erasing operations The high voltageappearing in a short time is regarded as a pulse Figure 5.30 shows an example of a level shifter The inputsignal is a pulse in Vcc/ground level, which controls the duration of a high-voltage pulse The supply of thelevel shifter determines the output voltage level of the high-voltage pulse The level shifter is a positivefeedback circuit, which turns stable at the ground level and supply voltage level (high voltage is generatedfrom charge pumping circuits) The operation of the level shifter can be realized as follows The low-voltage input can only turn off the NMOS transistor but cannot turn off the PMOS parts On the otherhand, high voltage can only turn off the PMOS transistor Therefore, generation of two mutually invertedsignals can turn off the individual loading path and provide no leakage current during stand-by Thechallenges of the design are the transition power consumption and the possibility of latch-up The delay

of the feedback loop will result in large leakage current flowing from the high-voltage supply to ground.The leakage current is similar to the transition current of conventional CMOS circuits, but larger due to

FIGURE 5.29 The algorithm of the process routine in Fig 5.28.

the delay of the feedback loop As the large leakage current occurs due to generated substrate current

by hot carriers, the level shifter is susceptible to latch-up The design of the level shifter should focus onspeeding up the feedback loop and employing a latch-up-free apparatus More sophisticated levelshifters should be designed to provide trade-off between the switching power and the switching speed.The level shifter is used in the word-line driver and the bit-line driver if the bit line requires avoltage larger than the external power supply The driver is expected to be small because the word-linepitch is nearly minimum feature size Thus, the major challenges are to simplify the level shifter and toprovide a high-performance switch

5.8.4 Charge-Pumping Circuit

The charge-pumping circuit is a high-voltage generator that supplies high voltage for programming anderasing operations This kind of circuit is well-known in power equipment, such as power supplies, high-voltage switches, etc A conventional voltage generator requires a power transformer, which transformsinput power to output power without loss In other words, low voltage and large current is transformed

to high voltage and low current The transformer uses the inductance and magnetic flux to generate highvoltage very efficiently However, in the VLSI arena, it is difficult to produce inductors and the charge-pumping method is used instead Figure 5.31 shows an example of a charge-pumping circuit that consists

of multiple-stage pumping units Each unit is composed of a way switch and a capacitor The way switch is a high-voltage switch that does not allow charge to flow back to the input The capacitorstores the transferred charge and gradually produces high voltage No two consecutive stages operate atthe same time In other words, when one stage is transferring the charge, the next stage and the previousstage should serve as an isolation switch, which eliminates charge loss Therefore, a two-phase clockingsignal is required to proceed with the charge-pumping operation, producing no voltage drop betweenthe input and output of the switch and large current drivability of the output In addition, the voltage

one-FIGURE 5.30 Level shifter: (a) positive polarity pulse, and (b) negative polarity pulse.

Flash Memories

level must be higher than the previous stage Therefore, the two-phase clocking signal must be shifted to individual high voltages to turn on and off the one-way switch in each pumping unit Asmaller charge-pumping or a more sophisticated level-shift circuit can be employed as self-boostedparts The generated high voltage, in most cases, is higher than the required voltage A regulationcircuit, which can generate stable voltage and is immune to the fluctuation of external supply voltageand the operating temperature, is used to regulate the voltage and will be described later

level-5.8.5 Sense Amplifier

The sense amplifier is an analog circuit that amplifies small voltage differences Many circuits can beemployed—from the simplest two-transistor, cross-coupled latches to the complicated cascaded cur-rent-mirrors sense amplifiers Here, a symbolic diagram is used to represent the sense amplifier in thefollowing discussion The focus of the sensing circuit is on multi-level sensing, which is currently theengineering issue in Flash memory Figures 5.32(a) and (b) show the schemes of parallel sensing andconsecutive sensing, respectively These two schemes are based on analog-to-digital conversion (ADC).Information stored in the Flash memory can be read simultaneously with multiple comparators work-ing at the same time The outputs of the comparators are encoded into N digits for 2N levels Figure5.32(b) shows the consecutive sensing scheme The sensing time will be N times longer than theparallel sensing for 2N levels The sensing algorithm is a conventional binary search that compares themiddle values in the consecutive range of interest Only one sense amplifier is required for a cell In theexample, the additional sense amplifier is used for speeding up the sensing process The second-stagesense amplifier can be pre-charged and prepared while the first-stage sense amplifier is amplifying thesignal uThus, the sensing time overhead is reduced

FIGURE 5.31 (a) Charge-pumping circuit, (b) two-phase clock, and (c) pumping voltage.

When a multi-level scheme is used, the threshold voltage should be as tight as possible for eachlevel The depletion of unselected cells is strictly inhibited because the leakage current from unselectedcells will destroy the true signal, which leads to error during sensing Another challenge in multi-levelsensing is the generation of reference voltages Since the reference voltages are generated from thepower supply, the leakage along the voltage divider path is unavoidable Besides, the generated voltagesare susceptible to the temperature variation and process-related resistance variation If the variation ofreference voltages cannot be minimized to a certain value, the ambiguous decision would be made formulti-level sensing due to unavoidable threshold spread for each level Therefore, to provide high-sensitivity sense amplifier and to generate precise and robust reference voltages are the major developinggoals for more than four-level Flash memory.

5.8.6 Voltage Regulator

A voltage regulator is an accurate voltage generator that is immune to temperature variation, process-relatedvariation, and parasitic component effects The concept of voltage regulation arises from the temperature-compensated device and the negative feedback circuits Semiconductor carrier concentration and mobilityare all dependent on the ambient temperature Some devices have positive temperature coefficients, whileothers have negative coefficients We can use both kinds of devices to produce a composite device forcomplete compensation Figure 5.33 shows two back-to-back connected diodes that can be insensitive tothe temperature over the temperature range of interest, if the doping concentration is properly designed

FIGURE 5.32 (a) Parallel sensing scheme, and (b) consecutive sensing scheme.

Flash Memories

The forward-bias diode is negatively sensitive to temperature: the higher the temperature, the lowerthe cut-in voltage On the other hand, the reverse-bias diode shows a reverse characteristic in thebreakdown voltage When connecting the two diodes and optimizing the diode characteristics, theregulated voltage can be insensitive to temperature Nevertheless, the generated voltage is usually notwhat we want A feedback loop, as shown in Fig 5.34, is needed to generate precise programming anderasing voltage The charge-pumping output voltage and drivability are functions of the two-phaseclocking frequency The pumping voltage can be scaled to be compared with the precise voltagegenerator to provide a feedback signal for the clocking circuit whose frequency can be varied Withthe feedback loop, the generated voltage can be insensitive to temperature Whatever the desiredoutput voltage is, the structure can be applied in general to produce temperature-insensitive voltage

5.8.7 Y-Gating

Y-gating is the decoding path of bit lines The bit-line pitch is as small as the minimum feature size Oneregister and one sense amplifier per bit line is difficult to achieve Y-gating serves as a switch that makesmultiple bit lines share one latch and one sense amplifier Two approaches—indirect decoding and directdecoding—used as the Y-gating are shown in Figs 5.35(a) and (b), respectively Regarding the indirectdecoding, if 2N bit lines are decoded using one-to-two decoding unit, cascaded stages are required with

N decoding control lines However, when the direct decoding schemes is used, 2N bit lines require 2N

decoding lines to establish a one-to-2N decoding network, and the pre-decoder is required to generatethe decoding signal The area penalty of indirect decoding is reduced but the voltage drop along thedecoding path is of concern To avoid the voltage drop, a boosted decoding line should be used to

FIGURE 5.34 Voltage regulation block diagram.

FIGURE 5.33 (a) Back-to-back connected temperature-compensated dual diodes; and (b) the characteristics of

a diode as a function of temperature.

overcome the threshold voltage of the passing transistor Another approach to eliminate voltage drop isthe employment of a CMOS transfer gate However, the area penalty arises again due to well-to-wellisolation Since Flash memory is very sensitive to the drain voltage, boosted decoding control lines,together with the indirect decoding scheme, are suggested.

5.8.8 Page Buffer

A page buffer is static memory (SRAM-like memory) that serves as temporary storage of input data.The page buffer also serves as temporary storage of read data With the page buffer, Flash memory canincrease its throughput or bandwidth during programming and read, because external devices can talk

to the page buffer in a very short time without waiting for the slow programming of Flash memory.After the input data is transferred to the page buffer, the Flash memory begins programming andexternal devices can do other tasks The page size should be carefully designed according to theapplications The larger the page size, the more data can be transferred into Flash memory withouthaving to wait for the completion of programming However, the area penalty limits the page size.There exists a proper design of page buffer for the application of interest

FIGURE 5.35 (a) Indirect decoding, and (b) direct decoding.

Flash Memories

5.8.9 Block Register

The block register stores the information about the individual block The information includes failure

of the block, write inhibit, read inhibit, executable operation, etc., according to the applications ofinterest Some blocks, especially the boot block, are write-inhibited after first programming Thisprevents virus injection in some applications, such as PC BIOS The block registers are also Flashmemory cells for storing block information, which will not disappear after power-off When the localFSM is working on a certain block, the first thing is to check the status of the block by reading theregister If the block is identified as a failure block, no further operation can be made in this block

5.8.10 Summary

Flash memory is a system with mixed analog and digital systems The analog circuits include generation circuits, analog-to-digital converter circuits, sense amplifier circuits, and level-shifter cir-cuits These circuits require excellent functionality but small area consumption The complicated ana-log designs in the pure-analog circuit do not meet the requirements of Flash memory, which requireslarge array efficiency, large memory density, and large storage volume Therefore, the design of theseanalog circuits tends toward reduced design and qualified function On the other hand, the digital parts

voltage-of Flash memory are not as complicated as those digital circuits used in pure digital signal processcircuits Therefore, the mixed analog and digital Flash memory system can be implemented in a simpli-fied way Furthermore, Flash memory is a memory cell-based system All the functions of the circuitsare designed according to the characteristics of the memory cell Once the cell structure of a memorydiffers, it will result in a completely different system design

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