ATM BASICS - Chapter 2 pot

The cells received from the ATM layer are encoded and pushed intothe medium as a bit or a byte stream.. Whereas the PMD sublayer is different for different carriers and cables, the TC ju

How Does ATM Work

This chapter explains fundamental concepts that lay the basis for ATM

technology The reader is given the in-depth understanding of the terms

such as ATM cells, statistical multiplexing, ATM switching and ATM layer

processing The layers of ATM reference model are discussed and explained

This in-depth view includes the Physical Layer, the ATM and the ATM

Adaptation Layer The basic understanding of these terms is recommended

prior to reading through the following chapters

2.1 ATM Protocol Reference Model

As it was mentioned before, ATM can be viewed as a part of the B-ISDN

con-cept The development of B-ISDN protocols was facilitated by the definition

of the B-ISDN Protocol Reference Model (PRM) The model was developed

using the layered communication architecture based on the distinction

between layer functions developed by the ISO (International Standards

Organization) ATM plays a significant role in the B-ISDN PRM The formal

ATM PRM is a three-dimensional model but the relations between layers

can be better viewed using one-dimensional layer model

It is important to understand that the layers in the ATM PRM (presented inthe Fig.2-1) don’t have one-to-one mapping relationship with the seven lay-ers OSI protocol reference model Some of the layers of ATM PRM providethe functionality of more than one OSI layer For instance, the AAL (ATMAdaptation Layer) represent some of the features of OSI layer 4 (transportcontrol), layer 5 (session control) and layer 7 (application control) Most ofthe ATM PRM layers can be further subdivided into a number of sublayers.

2.2 Physical Layer

The physical layer (PHY) constitutes the lowest level of the ATM PRM Itsmajor task is to transmit ATM cells between ATM devices over the physicalmedium ATM is designed to operate over potentially error free media.Therefore, successful transmission of ATM cells between ATM devices

Fig 2-1, Simplified ATM Protocol Reference Model

requires very low values of BER (BER = 10-12 or better) There exist today a

large variety of standards defining ATM physical interfaces This situation

is mainly caused by a number of underlying technologies that can be used

by ATM

2.2.1 Sub-layers

A physical layer takes complete cells from the mid-layer and transmits them

over the physical medium The physical layer itself is subdivided into two

sub-layers:

•the Transmission Convergence (TC) sub-layer,

•the Physical Medium Dependent (PMD) sub-layer

These two sub-layers work together to ensure that the physical interfaces

receive and transmit cells efficiently, with the appropriate timing structure

in place

Fig 2-2, Sublayers of the Physical Layer

The Physical Medium Dependent is concerned with getting the bits on andoff the wire The PMD bit transmission includes bit transfer and bit align-ment Technically, it covers bit timing, line coding, opto-electric conversion,modulation and demodulation functions necessary to transfer bits over agiven medium The physical connectors and signal characteristics differfrom medium to medium.

The Transmission Convergence sublayer is separated from details and acteristics of the physical medium being used Due to the presence of thePMD sublayer the TC is specified independently of the underlying physicalmedium and operates over different media In general, the purpose of the

char-TC sublayer is to provide a uniform interface to the ATM layer in both tions The cells received from the ATM layer are encoded and pushed intothe medium as a bit or a byte stream The work of the TC sublayer can becharacterized by the following functions:

direc-•Cell rate decoupling This mechanism is used to insert idle cells inthe transmit direction in order to compensate for the variable rate of thegeneration of ATM cells At the receiving side all idle cells are identified andsuppressed

•Header checksum generation and extraction The TC sublayer candetect and if necessary correct errors affecting the contents of the ATM cellheader At the transmitting side the Header Error Check (HEC) field is gen-erated in hardware and inserted into the cell header At the receiving sidethe HEC is recalculated and compared to the value that is extracted fromthe header of the received cell The capabilities of the algorithm used to cal-culate the HEC allow for the detection and correction of single errors as well

as detection of double errors

•Unpacking cells from the enclosing envelope This function is alsoreferred to as cell delineation The receiver must be able to recover the cellboundaries The TC sublayer must delineate the individual cells in thereceived bit stream, either directly from the TDM frame or with the help ofthe HEC field in ATM cells This function can be complemented by thescrambling/descrambling operation

•Frame generation The cell flow must be adapted to the payload of

the transmission system in the transmit direction In the receive direction,

the TC extracts the payload from the transmitted cell

The separation between the TC and the PMD sublayers is the key factor

enabling flexibility in terms of variety of physical interfaces Whereas the

PMD sublayer is different for different carriers and cables, the TC just sends

the cells as a string of bits to the PMD sublayer and converts the bit stream

into a cell stream for the ATM layer

2.2.2 Physical Interfaces

ATM, while being an international transmission technology, has to be able

to work with a variety of formats, speeds, transmission media and distances

that may vary from operator to operator and from country to country

Single-mode fiber, multi-mode fiber, coaxial pairs of different categories,

and shielded and unshielded twisted pairs are all standardized for the use

in the ATM environment ATM can be also run over Radio Frequency

(RF)/satellite links The ITU-T originally defined only two speeds, which

should be supported by ATM: 155.52 Mbps and 622.08 Mbps However, over

time a number of additional speeds and interfaces have been defined, going

as low as DS1/E1 and as high as the 2.5 and 10 Gbps The standardization

process of new physical interfaces is influenced by two factors First of all,

new interfaces are standardized following the development of transmission

technologies (new types of o fibers and copper wires, e.g UTP Cat 6)

However in recent years a few standards have been introduced, while

direct-ly reflecting the market needs Standards describing ATM over Fractional

Links, Inverse Multiplexing for ATM (IMA), Frame-based ATM Transport

over Ethernet (FATE) and Frame Based ATM over SONETS/SDH allow the

operators to maximize the efficiency of their network infrastructure

2.2 ATM Layer

The ATM layer deals with moving cells from a source to a destination, whichdefinitely implies the presence routing algorithms and protocols within theATM switches From the functional point of view, the ATM layer performsthe work expected of the network layer in the OSI model However, sinceATM is quite frequently used to transport IP packets, the ATM layer is bymany people characterized as a data link layer This opinion is not precisedue to the fact that the ATM layer has also some characteristics of a net-work layer: end-to-end virtual circuits, switching and routing In resultATM is sometimes referred to as a layer 2 ½ solution

As it was mentioned earlier, the ATM layer is connection oriented, both interms of the services it can provide and the way it is used by the operators.The basic concept present at the ATM layer is a virtual circuit (in officialATM terminology called a virtual connection) A virtual circuit should beenseen as a connection from one source to one destination, although point-to-multipoint connections are also supported It is important to note that vir-tual circuits are unidirectional but a pair of circuits is normally created atthe same time The same identifiers are used for both directions of the vir-tual circuit but the amount of reserved network resources can differ for bothdirections

The ATM layer is not guaranteed to be 100% reliable The assumption hasbeen made that it’s the task of the underlying physical layer to ensure theerrorless transmission Therefore, the ATM layer is unusual for a connec-tion-oriented protocol in that it operates without any acknowledgements

2.2.1 ATM Cells

The ATM cell is probably the most obvious term for anyone who has ever

heard about ATM technology The ATM cell, a very unique type of a packet,

is comprised of a 5-byte header and 48-byte payload that typically contains

user information In total, ATM cells are 53-byte long (see in the Fig 2-3)

The final agreement on the cell size was influenced by the struggle between

interests representing various interests At the early stage of ATM

stan-dardization process in the ITU-T two different values of the payload size

Fig 2.3, The ATM cell

posed by those who envisaged ATM as the technology satisfying data mission needs in the first place In large cells the relation between the pay-load and the total size is greater - the fixed size overhead represents thesmaller percentage of transmitted data Hence, the overall efficiency fordata transmission is increased The larger size of a cell, the greater amount

trans-of the delay is experienced by other sources generating data in the form trans-ofcells This results in increased delays observed by real time applicationssuch as voice and video transmission Needless to say, 32-octet payloadwould be perfectly suited for the transmission of the E1 signal The actualdecision on the 48-bytes payload size was a compromise trying to minimizethe disadvantages of two competitive proposals It offered a tradeoffbetween the efficiency for data transmission and the delay requirements fordata and video traffic The size of ATM cells allowed operators to transmitvoice over relatively long distances (round trips of 1000 km) whilst avoidingthe need for expensive echo cancellers The concept of fixed size cells is alsopresent in work done in Australia under development of DQDB (DistributedQueue Dual Bus (DQDB), covered in IEEE 802.6 As the matter of fact, thesmallest unit of traffic in DQDB is the slot, which is of 53 bytes length

2.2.2 ATM Cell Header

Fig 2-4 shows the internal structure of an ATM cell header at UNI andNNI In ATM the interface between the user equipment and the ATM switch

is called User-to-Network Interface All other interfaces, including thosebetween ATM switches and between ATM networks as referred to as Node-to-Node Interfaces or Network-to-Node Interfaces The key difference is theGeneric Flow Control (GFC) field, which is not present in cell headers trans-mitted across the NNI

GFC (Generic Fow Control) is the 4-bit field that is present only in cells

transmitted between hosts and the network Switches interfacing between

the user’s equipment and ATM network overwrite GFC, and it is not

deliv-ered to the destination In early days of ATM it was intended to have some

utility for flow and priority control between hosts and the networks, when

multiple ATM devices were to be dropped on a single UNI For any

equip-ment using uncontrolled access, the GFC files shouldn’t be used and the bits

must be always set to 0000 for the transmitted cells

VPI (Virtual Path Identifier) has 8 bits available at the UNI and 12 bits

at the NNI, which gives either 256 or 4096 simultaneous virtual paths at

maximum per a physical connection

Fig 2-4, The ATM cell header format

VCI (Virtual Channel Identifier) is the 16-bit field that selects a

partic-ular virtual channel within a given virtual path It allows for up to 65,536virtual channels per a virtual path A number of combinations of VPI andVCI values are reserved for control functions, such as setting up and clear-ing virtual connections

PTI (Payload Type Identifier) is the 3-bit field, which is as part of cell

control concept The PTI defines the information carried in the cell payload.User data and network management cells are differentiated due to the value

of the MSB bit (sometimes referred to as RM-celler) The second bit can beused to indicate congestion affecting data traffic that can occur in the net-work nodes This bit is often called Explicit Forward Congestion Indicator(EFCI) The LSB bit is used to indicate the final cell in the cell stream,which has been filled with higher layer packet traffic This bit is referred to

as the Service DataUnit (SDU) bit and its application is mostly related tothe presence of a certain adaptation layer type

Table 2-1, PTI field values

CLP (Cell Loss Priority) is the 1-bit field, which value is set by a host to

differentiate between high-priority and low-priority traffic If the CLP is set

(CLP = 1) for a cell and the congestion occurs, the cell can be discarded at

switching devices The cell can be directly marked as a low-priority cell by a

transmitting host or it can be tagged (CLP changes from 0 to 1) by an ATM

switch if the cell represents excessive traffic (breaking the traffic contract)

HEC (Header Error Check) is the 8-bit checksum field The checksum

only covers the first four octets of the cell header It is comprised of the

reminder of the 32 bits out of the header divided by the polynomial x8+ x2+

x + 1 Next it is added to the constant value of 01010101, which provides

robustness in the face of header that contain mostly 0 bits The HEC scheme

can correct all single bit errors and detect multiple errors as well

2.2.3 Cell Transmission

The first step in successful cell transmission is the computation of t the

header checksum The decision to protect only the header was made

delib-erately to reduce the likelihood that some cells are delivered incorrectly due

to a header error This operation does not involve any calculations over the

payload field and it’s up to higher layers to perform error detection and

cor-rection, if they desire so This approach can be easily explained by taking

into account that most real-time applications, such as voice and video

trans-mission, accept occasional loss of information bits However, this is not true

when it comes to data transmission

Next, if the HEC has been generated and inserted into the cell header, it is

now possible to transmit the cell through the physical interface Depending

on the type of transmission media, some additional operations may be

nec-essary If an asynchronous medium is used, a cell can be sent without any

delay (no timing constraints are present) When a synchronous medium is

used, all cells must be sent according to a predefined timing pattern imposed

by the characteristics of a transmission medium This may require the

occa-sional transmission of idle cells, which contain predefined and well-known

bit pattern

The ATM layer does not provide any mechanism that would allow foracknowledgments The actual reason is that the introduction of ATM coin-cided in time with the envisaged rapid inclusion of high speed and very reli-able fiber optic networks It was thought that the task of efficient error con-trol would be left to higher layers And in fact, most transport layer proto-cols handle this task sufficiently by re-sending the entire message if neces-sary ATM networks were intended for the use for real time traffic and for

that type of traffic re-transmitting a single cell corrupted with errors is

more than problematic.

ATM cells belonging to a virtual connection are transmitted and delivered

to the destination in sequence As can be easily noticed from the cell headerstructure, there is no mechanism at the ATM layer that can provide a toolfor checking whether cells are delivered in sequence or not Basically, it isthe matter of the transmission and switching concepts that ensures cell aretransmitted to the destination without reordering Thanks to this assump-tion large savings on cell processing delay are observed However, the task

of checking the integrity of cell stream is given to higher layers of the ATMprotocol reference model

2.2.4 OAM Cells

Within the stream of ATM cells carrying user data one it is possible to tify so called OAM (Operation And Maintenance) cells These non-data ATMcells are used by ATM switches for exchanging low level signaling and con-trol information that are necessary for having the system running The com-mon application of OAM cells is to match the output ATM rate to the rate ofthe underlying transmission technology For instance, an ATM source trans-mitting ATM cells over SONET would normally put out an OAM cell asevery 27 cells In result, the data rate would slow the data rate down to26/27 of 150,336 (OC-3) and thus match SONET completely

iden-2.2.5 Cell Reception

At the receiving end an ATM device has to take incoming bits first, locate

the cell boundaries, check the header, processes the OAM cells (if there are

any) and finally pass the data cell up to the ATM layer The most difficult

task is to delineate cell boundaries from the incoming bit stream The

delin-eation algorithm has two forms that function in the same way In

non-framed environment, the process is bit-aligned, while in a frame-based

sys-tem such as SONET, an octet-aligned process is a better solution The

gen-eral rule is to obtain help from the HEC The method is to initiate the

delin-eation process in a HUNT state (this is shown in Fig 2-5) and to compute

the HEC value for any random sequence of 5 bytes (stored temporarily in a

40-bit shift register) and to consider these 5 bytes as a potentially valid cell

header If this test fails, the next five bytes are taken into account Given

the size of a header and an ATM cell, it can be derived that a header is going

to be located sooner or later However, there may coincidently be a correct

calculation on what is not a header In such a case the delineation procedure

will wait 48 bytes and try again When the first calculation is completed

suc-cessfully, the process moves to PRESYNCH state, where again 48 bytes shift

takes place and repeated calculation is performed If this

wait-and-try-process produces the correct answer δ times (typically 6 times), the

delin-eation process indicates SYNCH state The value of δis chosen to minimize

the probability of getting into SYNCH state by accident

It may also happen that due to poor quality of transmission the

synchro-nization is lost Some of the bits can be inserted or deleted from the

trans-mission Then the cell with the bad header is discarded But if αconsecutive

HECs are bad, then the delineation process takes the decision that the

syn-chronization has been lost and it moves to the HUNT state

The mechanism chosen for cell delineation requires that the TC sublayer isable to understand and use the data included in the header of the ATM layerpresent above it This process in fact violates the basic rules of protocol engi-neering as it requests that one layer makes the use of a higher layer.Therefore, any change applied to the header format of the ATM layer wouldaffect the TC sublayer

2.2.6 Virtual Channels and Virtual Paths

As it was stated earlier, the ATM layer provides connectivity by means ofvirtual circuits Given that within the ATM layer header there are two fieldsthat carry identifiers, it can be easily noticed that a two-level connectionhierarchy can be supported

Figure 2-5, The cell delineation algorithm

The physical link carrying ATM cells can be visualized as a large pipe of the

size that represents the capacity of the physical medium (shown in Fig 2-6)

The link can be further subdivided into smaller pipes called Virtual Paths,

which in turn contain smaller pipes – Virtual Channels Therefore, along

any transmission route from a given source to a given destination a group of

virtual circuits can be grouped together This way of the visualization of

vir-tual circuits may be helpful in understanding how operators apply the

con-cept of the virtual connection The Virtual Path, which is identified by the

value of a VPI field in the ATM layer header, can be also thought as a small

multi-core cable within a larger cable Particular cores of the multi-core

cable would be Virtual Channels, identified by VCI values in the ATM cell

header Having in mind that the size of the VPI field is equal to 12 bits at

the NNI, it is possible to have up to 4096 VPs per a physical port/link

Fig 2-6, The concept of Virtual Paths and Virtual Channels

The physical link can carry many Virtual Paths and, if a bearer failurerequires the re-routing of VPs, this can be achieved much more easily at the

VP level than at the VC level Conceptually, a Virtual Path is like a bundle

of twisted pairs (e.g UTP): when a bundle is re-routed, all the pairs (i.e.Virtual Channels) are re-routed simultaneously At the VP level it is onlynecessary to issue a command to re-route one VP, and all the VCs travelingwithin that VP are automatically switched as well This minimizes the load

on control mechanisms and facilitates the recovery from the failure tion Therefore, efficient handling of VPs can be considered as the tool fortraffic engineering operations

situa-Fig 2-7, VP Switching vs VP/VC Switching

A two-level connection hierarchy allows for two different methods of

switch-ing cells in ATM networks In VP switchswitch-ing, a number of VCs is

multi-plexed into a VP, and then travel through ATM switches with the VCI

num-bers unchanged That approach reduces the volume of work needed to read

the routing table (its size is decreased) and network control complexity It is

important to note that traffic managements and policing functions are

per-formed only on the aggregated VP level As a consequence, the quality of

ser-vice characteristics of the bundled virtual connections must be that of the

most stringent VC, since the switch deals with the VP level only Virtual

Paths can be terminated at the switch or they can be cross-connected

through the switch VP switching is typically used in switches located in the

core network

VP/VC switching is yet another method for switching of ATM cells This

method requires that an ATM switch is capable of simultaneous change of

both identifiers: VPI and VCI In a switch cells that belongs to a given

vir-tual circuit can be extracted from the combination of a virvir-tual channel and

a virtual path and passed to another combination of a virtual channel and a

virtual path

The values for the VPI and VCI fields are unique with regards to a specific

link connecting two ATM sites The values may change when routing

through a switch In fact switching operations performed in an ATM switch

are restricted to the cross-connection of a VPI/VCI combination on the input

port to a VPI/VCI combination on the output port

For any ATM cell that arrives to an ATM device, the ATM layer is firstchecked with the help of the HEC Provided no errors are detected, the cellheader is checked to determine if the cell carries user information or net-work related information (this is identified with the value of the PTI field).

If the cell contains user information, then VPI/VCI or only VPI values arelooked up in the switch map associated with that physical interface to deter-mine the way the cell should be directed to

A switch map (or a routing table) can be found at each interface (the namefor this structure varies between manufacturers) The tables are stored inthe MIB (Management Information Base) structures and the manner ofimplementation is entirely vendor-specific The map contains the mappingbetween incoming VPI/VCI values and the new values for the next part ofthe virtual connection The record naturally specifies the output port from

Fig 2-8, ATM Switching Operation

the switch This is all the information needed to condition the fabric to take

the cell from input buffer to the output buffer The records in the switch map

are entered either by a manual process (in the case of Permanent Virtual

Connections), or assigned dynamically by the signaling mechanism (in the

case of Switched Virtual Connections)

Some of the combinations of VPI/VCI values are reserved for specific

func-tions The first 32 VCIs numbers (using decimal notation from 0 to 31) are

reserved and, therefore, the first VCI which is user-assignable is VCI = 32

The ITU-T reserved the first 16, and the ATM Forum was allocated the

sec-ond group of 16 numbers Until now, only certain values of VCI are reserved

on particular VPIs However, by popular usage carriers have adopted the

rule saying that VCI values 0 through 31 are reserved for all values of VPI

Assuming the range of values available (using 16 bits it is possible to have

VCI numbers ranging from 0 to 65535), this is not seen as a problem and it

simplifies implementation

2.2.7 ATM Switch

The basic structure of an ATM switching node is comprised of a set of

inter-faces for input and output connections, a switching fabric and a set of

soft-ware blocks responsible for the control of the switch and signaling towards

other devices The Fig 2-9 presents the general and simplified architecture

of an ATM switch The interface cards contain buffers for input and output

traffic Buffers can act as scheduler that select which cells are to be placed

upon the output media The switch fabric is the high-speed component that

moves cells from input buffer to output buffer

Cells actually arrive at the input ports in an asynchronous way However,

ATM switches are generally synchronous in the sense of cycles during which

cells are taken from each input interface, passed into the internal switching

fabric and transmitted through the appropriate output interface It may

take several cycles before a cell travels between the input and output ports

The cycles are dictated by a master clock Any cell, that is fully received at

the input port when the clock ticks, is eligible for being switched during that

cycle The number of cells that must be simultaneously switched is

depen-would require that at maximum 16 cells could appear simultaneously at theswitch The cycle time of the switch typically reflects the speed of transmis-sion at the physical layer At 622 Mbps, about every 700 ns a new batch ofcells is injected into the switch fabric Due to the fact that ATM cells aresmall in size and of fixed length it possible to build switching devices oper-ating with the speed that couldn’t be reached by IP routers for a long time.However, the technological developments in late 90’s led to the design andimplementation of gigabit routing

Fig 2-9, The general architecture of an ATM switch