Design and Implementation of VLSI Systems_Lecture 04: Mos transistor Theory pdf

CURRENT-VOLTAGE RELATIONS As L increases, Vds diminishes in effect more voltage drop  takes longer to push carriers across the transistor  reducing current flow... TRANSISTOR CAPACITA

Design and Implementation of

VLSI Systems Lecture 04

Thuan Nguyen Faculty of Electronics and Telecommunications,

University of Science, VNU HCMUS

Spring 2011

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LECTURE 04: MOS TRANSISTOR THEORY

LECTURE 04: MOS TRANSISTOR THEORY

I DEAL (S HOCKLEY ) M ODEL

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Review: p-n junction

 A p–n junction in thermal equilibrium

 A p–n junction in thermal

equilibrium with zero bias voltage applied Under the junction, plots for the charge density, the electric field

and the voltage are reported

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GATE-OXIDE-BODY SANDWICH = CAPACITOR

Vg < 0

(b)

+ -

0 < Vg < Vt

depletion region

(c)

+ -

Vg > Vt

depletion region inversion region

NMOS CUTOFF

 No channel

 Ids ≈ 0

+ -

Vgs = 0

+ -

Vgs > Vt

+ -

Vgd = Vgs

+ -

Vgs > Vt

+ -

Vgs > Vgd > Vt

Vds = 0

0 < Vds < Vgs-Vtp-type body

NMOS SATURATION

 Channel pinches off

 Ids independent of Vds

 We say current saturates

 Similar to current source

+ -

Vgs > Vt

+ -

Vgd < Vt

Vds > Vgs-Vtp-type body

b

g

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THE MOS TRANSISTOR HAS THREE REGIONS

HOW TO CALCULATE THE CURRENT VALUE?

 MOS structure looks like parallel plate

capacitor while operating in inversion

 Gate – oxide – channel

CARRIER VELOCITY IS A FACTOR IN

 Charge is carried by electrons

 Carrier velocity v proportional to lateral

E-field between source and drain

 v = μE μ called mobility

 E = Vds/L

 Time for carrier to cross channel:

t = L / v

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I=Q/ T

 Now we know

IN LINEAR MODE (VGS > VT & VDS < VGS-VT)

Can be ignored for small Vds

 For a given V gs , I ds is proportional (linear) to V ds

IN SATURATION MODE (VGS > VT AND VDS ≥

OPERATION MODES SUMMARY

 2

cutoff linear saturatio

CURRENT-VOLTAGE RELATIONS

 As L increases, Vds diminishes in effect (more

voltage drop)  takes longer to push carriers

across the transistor  reducing current flow

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TRANSISTOR CAPACITANCE

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 Gate capacitance: to body + to drain + to source

 Diffusion capacitance: source-body and drain-body

capacitances

GATE CAPACITANCE AS A FUNCTION OF VGS

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QuickTime™ and a decompressor are needed to see this picture.

SOURCE/DRAIN DIFFUSION CAPACITANCE

SUMMARY OF SHOCKLEY MODEL

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cutoff linear saturatio

Covered ideal (long channel) operation (Shockley model) of transistor

LECTURE 04: MOS TRANSISTOR THEORY

IDEAL VS NON-IDEAL

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 Saturation current does not increase quadratically with Vgs

 Saturation current lightly increases with increase in Vds

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 There is leakage current when the transistor is in cut off

 Ids depends on the temperature

At high electric field, drift velocity rolls

of due to carrier scattering

Empirically:

ALPHA MODEL

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linear saturation

MOBILITY DEGRADATION

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C HANNEL LENGTH MODULATION

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• The reverse-bias p-n junction between drain

and body forms a depletion region with a width

L d that increases with V db

• Increasing Vds

 increases depletion width

 decreases effective channel length

 increases current

Channel length modulation factor (empirical factor)

n + p

Gate

bulk Si

n +

V DD

GND

L Leff

Depletion Region Width: L d

L EAKAGE CURRENT : SUBTHRESHOLD

Subthreshold conduction

Tunnel current

Junction leakage

 Subthreshold leakage is

the biggest source in

LEAKAGE CURRENT: JUNCTION LEAKAGE AND TUNNELING

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D T

V v

D S

   

Junction leakage: reverse-biased p-n junctions

have some leakage

Is depends on doping levels and area and

perimeter of diffusion regions

Tunneling leakage:

 Carriers may tunnel thorough very thin gate oxides

 Negligible for older processes

(and future processes with high-k dielectrics!)

I MPACT OF TEMPERATURE

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o Carrier mobility decreases with T o ↑

o Threshold voltage decreases nearly linearly with T o ↑

o Junction leakage increases with T o ↑

o ON current decreases and OFF current increases with T o ↑

 Circuit performance is generally worst at high T o ↑

 negative temperature coefficient

I MPACT OF TEMPERATURE ( CONT )

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Circuit performance can be improved by cooling

o Subthreshold leakage decreases with T o ↓

o Velocity saturation increases with T o ↓  more current

o Mobility increases with T o ↓  save power

o Depletion regions become wider with T o ↓  less junction

capacitance

 

si ox

PROCESS VARIATIONS

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Both MOSFETs have 30nm channel with 130 dopant atoms in the channel depletion region

Process variations impact gate length, threshold

voltage, and oxide thickness

SUMMARY OF TRANSISTOR OPERATION

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NMOS transistor PMOS transistor

 Homework Assignment #3 View

 Submit your answer in the next week

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LECTURE 04: MOS TRANSISTOR THEORY

 In between, Vout depends on

transistor size and current

 By KCL, must settle such that

Idsn = |Idsp|

 We could solve equations

 But graphical solution gives more insight

TRANSISTOR OPERATION

 Current depends on region of transistor behavior

 For what Vin and Vout are nMOS and pMOS in

 Cutoff?

 Linear?

 Saturation?

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LOAD LINE ANALYSIS

BETA RATIO

 If p / n  1, switching point will move from

VDD/2

 Called skewed gate

 Other gates: collapse into equivalent inverter

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p n



0.1

p n



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NOISE MARGINS

 How much noise can a gate input see before it

does not recognize the input?

Indeterminate Region

NML

NMH

Input Characteristics Output Characteristics

Logical Low Input Range

 To maximize noise margins, select logic levels at

 unity gain point of DC transfer characteristic

TRANSIENT RESPONSE

 DC analysis tells us Vout if Vin is constant

 Transient analysis tells us Vout(t) if Vin(t) changes

 Requires solving differential equations

 Input is usually considered to be a step or ramp

 From 0 to VDD or vice versa

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 Hence transistor would turn itself off

 nMOS pass transistors pull no higher than VDD

-Vtn

 Called a degraded “1”

 Approach degraded value slowly (low Ids)

 pMOS pass transistors pull no lower than Vtp

 Transmission gates are needed to pass both 0

and 1

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PASS TRANSISTOR DC CHARACTERISTICS

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As the source can rise to within a threshold voltage of the

gate, the output of several transistors in series is no more

degraded than that of a single transistor

 Homework Assignment #4 View

 Submit your answer in the next week

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Q & A

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