Design and Implementation of VLSI Systems_Lecture 06: Circuit characterization and performance estimation ppt

SKEWED GATES Skewed gates favor one edge over another  Ex: suppose rising output of inverter is most critical  Downsize noncritical nMOS transistor  Calculate logical effort by comp

Design and Implementation

of VLSI Systems

Lecture 06

Thuan Nguyen Faculty of Electronics and Telecommunications,

University of Science, VNU HCMUS

Spring 2011

1

 All the node voltages in static CMOS must transition

between 0 and VDD  propagation delay + power

consumption

 Circuit families

LECTURE 06: CIRCUIT CHARACTERIZATION &

LECTURE 06: CIRCUIT CHARACTERIZATION &

D1 S

Y

6

EXAMPLE 2

Y

D0 S

D1 S

2) Sketch a design using NAND, NOR, and NOT

gates Assume ~S is available

BUBBLE PUSHING

 Start with network of AND / OR gates

 Convert to NAND / NOR + inverters

 Push bubbles around to simplify logic

 Remember DeMorgan’s Law

Y D

Y

8

3) Sketch a design using one compound gate and one

NOT gate Assume ~S is available

Y

D0 S D1

COMPOUND GATES

 Logical Effort of compound gates

A B C D

Y

A B

C D

A C

B D

2

2

1 4

4 4

D E

Y B

Y

A D

E

A

B C

6 6

EXAMPLE 4

 The multiplexer has a maximum input capacitance

of 16 units on each input It must drive a load of

160 units Estimate the delay of the two designs

H = 160 / 16 = 10 B = 1 N = 2

4 1 5 (6 / 3) (1) 2

6

10 10

Y

24 12

10 10

8 8

8 8

8 8

8 8

25 25

 Annotate your designs with transistor sizes that

achieve this delay

Y

8 8

8 8

8 8

8 8

25 25

12

INPUT ORDER

 Our parasitic delay model was too simple

 Calculate parasitic delay for Y falling

 If A arrives latest? 2 

 If B arrives latest? 2.33 

6C 2C 2

2

2 2

INNER & OUTER INPUTS

 Inner input is closest to output (A)

 Outer input is closest to rail (B)

 If input arrival time is known

 Connect latest input to inner terminal

2 2

2 2

A B

Y

14

ASYMMETRIC GATES

 Asymmetric gates favor one input over another

 Ex: suppose input A of a NAND gate is most critical

 Use smaller transistor on A (less capacitance)

 Boost size of noncritical input

 So total resistance is same

 gA = 10/9

 gB = 2

 gtotal = gA + gB = 28/9

 Asymmetric gate approaches g = 1 on critical input

 But total logical effort goes up

A reset Y

4 4/3

2 2

reset A

Y

15

SYMMETRIC GATES

 Inputs can be made perfectly symmetric

A B

Y

2 1 1

2 1 1

16

SKEWED GATES

 Skewed gates favor one edge over another

 Ex: suppose rising output of inverter is most

critical

 Downsize noncritical nMOS transistor

 Calculate logical effort by comparing to

unskewed inverter with same effective resistance

unskewed inverter (equal rise resistance)

unskewed inverter (equal fall resistance)

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HI- AND LO-SKEW

particular transition is the ratio of the input

capacitance of that gate to the input capacitance

of an un-skewed inverter delivering the same

output current for the same transition

 Skewed gates reduce size of noncritical

transistors

 HI-skew gates favor rising output (small nMOS)

 LO-skew gates favor falling output (small pMOS)

 Logical effort is smaller for favored direction

 But larger for the other direction

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2 2

B A

Y

B A

1/2 1/2

4 4

1 1

B A

Y

B A

1 1

2 2

2 2

B A

Y

B A

1 1

4 4

20

ASYMMETRIC SKEW

 Combine asymmetric and skewed gates

 Downsize noncritical transistor on unimportant input

 Reduces parasitic delay for critical input

A reset Y

4 4/3

2 1

reset A

Y

22

 We have selected P/N ratio for unit rise and fall

resistance (m = 2-3 for an inverter)

 Alternative: choose ratio for least average delay

2 2

B A

Y

B A

1 1 2

1

1.414

2 2

2 2

B A

Y

B A

1 1 2

 In general, best P/N ratio is sqrt of equal delay

ratio

 Only improves average delay slightly for inverters

 But significantly decreases area and power

 For area and power:

 Many simple stages vs fewer high fan-in stages

STATIC CMOS CIRCUIT (REVIEW)

 At every point in time (except during the switching

transients) each gate output is connected to

 The outputs of the gates assume at all times the

the circuit (ignoring, once again, the transient effects during switching periods)

 This is in contrast to the dynamic circuit class,

which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes

25

STATIC CMOS (REVIEW)

26

PROPERTIES OF COMPLEMENTARY CMOS

 High noise margins:

VOH and VOL are at VDD and GND, respectively

 No static power consumption:

There never exists a direct path between VDD and

VSS (GND) in steady-state mode

 Comparable rise and fall times:

(under the appropriate scaling conditions)

27

INFLUENCE OF FAN-IN AND FAN-OUT

28

FAST COMPLEX GATE-DESIGN TECHNIQUES

29

FAST COMPLEX GATE - DESIGN TECHNIQUES

30

FAST COMPLEX GATE - DESIGN TECHNIQUES

31

LECTURE 06: CIRCUIT CHARACTERIZATION &

33

Small Vout (VOL) a)

RATIOED CIRCUITS

the strength of the down transistor to the

pull-up device

 Ratioed circuits dissipate power continually in

certain states and have poorer noise margins than

complementary circuits

 Ratioed circuits tend to be used only in very limited circumstances

34

 In the old days, nMOS processes had no pMOS

 Instead, use pull-up transistor that is always ON

 In CMOS, use a pMOS that is always ON

0 0.3 0.6 0.9 1.2 1.5 1.8 0

0.3 0.6 0.9 1.2 1.5 1.8

PSEUDO-NMOS GATES

 Design for unit current on output

to compare with unit inverter

 pMOS fights nMOS

A

Y

B A

Y

36

PSEUDO-NMOS GATES

 Design for unit current on output

to compare with unit inverter

 pMOS fights nMOS

B A

Y

37

PSEUDO-NMOS DESIGN

 Ex: Design a k-input AND gate using

pseudo-nMOS Estimate the delay driving a fanout of H

PSEUDO-NMOS POWER

 Pseudo-nMOS draws power whenever Y = 0

 Called static power P = IDDVDD

 A few mA / gate * 1M gates would be a problem

 Explains why nMOS went extinct

 Use pseudo-nMOS sparingly for wide NORs

 Turn off pMOS when not in use

Y C

en

39

RATIO EXAMPLE

 The chip contains a 32 word x 48 bit ROM

 Uses pseudo-nMOS decoder and bitline pullups

 On average, one wordline and 24 bitlines are high

 Find static power drawn by the ROM

 Ion-p = 36 m A, VDD = 1.0 V

 Solution:

pull-up pull-up static pull-up

36 μW (31 24) 1.98 mW

LECTURE 06: CIRCUIT CHARACTERIZATION &

DYNAMIC LOGIC

 Dynamic gates uses a clocked pMOS pullup

 Two modes: precharge and evaluate

Y

1

1 A

THE FOOT

 What if pulldown network is ON during precharge?

 Use series evaluation transistor to prevent fight



Y inputs

footed unfooted

43

DYNAMIC LOGIC: PRINCIPLES

44

DYNAMIC LOGIC: PRINCIPLES

45

LOGICAL EFFORT

1

1 A

Y

2 2 1

B A

Y

3 3 1

B A

DYNAMIC LOGIC

 N+2 transistors for N-input function

– Better than 2N transistors for complementary

static CMOS

– Comparable to N+1 for ratio-ed logic

 No static power dissipation

– Better than ratio-ed logic

 Careful design, clock signal F needed

47

 Ratioless

 No Static Power Consumption

 Noise Margins small (NML)

 Requires Clock

48

DYNAMIC 4-INPUT NAND GATE

49

CASCADING DYNAMIC GATES

 Internal nodes can only make 0-1 transitions during evaluation period

50

 Dynamic gates require monotonically rising

inputs during evaluation

A



51

MONOTONICITY WOES

 But dynamic gates produce monotonically falling

outputs during evaluation

 Illegal for one dynamic gate to drive another!

DOMINO GATES

 Follow dynamic stage with inverting static gate

 Dynamic / static pair is called domino gate

 Produces monotonic outputs

dynamic

NAND

static inverter

53

RELIABILITY PROBLEMS - CHARGE LEAKAGE

54

 Dynamic node floats high during evaluation

 Transistors are leaky (IOFF  0)

 Dynamic value will leak away over time

 Formerly miliseconds, now nanoseconds

 Use keeper to hold dynamic node

 Must be weak enough not to fight evaluation

A



H 2

CHARGE SHARING (REDISTRIBUTION)

56

CHARGE REDISTRIBUTION - SOLUTIONS

58

SECONDARY PRECHARGE

 Solution: add secondary precharge transistors

 Typically need to precharge every other node

 Big load capacitance CY helps as well

B A

Y



x

secondary precharge transistor

59

 Domino gates have high activity factors

 Output evaluates and precharges

 If output probability = 0.5, a = 0.5

 Output rises and falls on half the cycles

 Clocked transistors have a = 1

 Leads to very high power consumption

61

DOMINO LOGIC

62

DOMINO GATES

63

DOMINO LOGIC - CHARACTERISTICS

 Only non-inverting logic

 Very fast – Only 1  0 transitions at input of inverter

 Adding level restorer reduces leakage and charge

redistribution problems

 Optimize inverter for fan-out

64

DOMINO OPTIMIZATIONS

 Each domino gate triggers next one, like a string

of dominos toppling over

 Gates evaluate sequentially but precharge in

parallel

 Thus evaluation is more critical than precharge

 HI-skewed static stages can perform logic

S0 D0

S1 D1

S2 D2

S3 D3



S4 D4

S5 D5

S6 D6

S7 D7



Y H

65

DUAL-RAIL DOMINO

 Domino only performs noninverting functions:

 AND, OR but not NAND, NOR, or XOR

 Dual-rail domino solves this problem

 Takes true and complementary inputs

 Produces true and complementary outputs

sig_h sig_l Meaning

f

66

EXAMPLE: AND/NAND

 Given A_h, A_l, B_h, B_l

 Compute Y_h = AB, Y_l = AB

 Pulldown networks are conduction complements

A_l

= A*B

= A*B

67

= A xor B B_l

A_h A_l

A_h

= A xnor B

68

DOMINO SUMMARY

 Domino logic is attractive for high-speed circuits

 1.3 – 2x faster than static CMOS

 But many challenges:

 Monotonicity, leakage, charge sharing, noise

 Widely used in high-performance microprocessors

in 1990s when speed was king

 Largely displaced by static CMOS now that

power is the limiter

 Still used in memories for area efficiency

69

LECTURE 06: CIRCUIT CHARACTERIZATION &

PASS TRANSISTOR CIRCUITS

 Use pass transistors like switches to do logic

 Inputs drive diffusion terminals as well as gates

 CMOS + Transmission Gates:

 2-input multiplexer

 Gates should be restoring

A

B S S

S

Y

A

B S S

S

Y

71

 LEAn integration with Pass transistors

 Get rid of pMOS transistors

 Use weak pMOS feedback to pull fully high

 Ratio constraint

B

SS

A

YL

72

 Complementary Pass-transistor Logic

 Dual-rail form of pass transistor logic

 Avoids need for ratioed feedback

 Optional cross-coupling for rail-to-rail swing

B

A

Y

Y L

L

73

P ASS TRANSISTOR SUMMARY

 Researchers investigated pass transistor logic for

general purpose applications in the 1990’s

 Benefits over static CMOS were small or negative

 No longer generally used

 However, pass transistors still have a niche in

special circuits such as memories where they

offer small size and the threshold drops can be

managed

74

CMOS CIRCUIT STYLES - SUMMARY

4-input NAND Gate

75

 Homework Assignment #5 View

 Submit your answer in the next week

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Q & A

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