Handbook of algorithms for physical design automation part 90 pptx

Note that as inductance effects increase, the short-circuit power consumption significantly decreases due to the faster input rise time.. Hence, as the interconnect behavior becomes domi

41.4.1 EFFECTS OFINDUCTANCE ONDELAY ANDSIGNALRISETIME

A general expression for the propagation delay from the input to the output of an RLC line of length

l with an ideal power supply and an open circuit load is given by [18]

tpd=√LC



e−2.9( αasyml )1.35

l + 0.74αasyml2

(41.8)

where

αasym= R

2

C

αasymis the asymptotic value at high frequencies of the attenuation per unit length of the signals as the signals propagate across a lossy transmission line, as shown in Figure 41.4

For the limiting case where L → 0, Equation 41.8 reduces to 0.37RCl2, illustrating the square

dependence on the length of an RC wire as aforementioned For the other limiting case where R→ 0, the propagation delay is given by√

LtCt = l√LC Note the linear dependence on the length of the line Note also that inductance always increases the delay as compared to an RC model; i.e., if inductance is neglected, the delay is underestimated by the incomplete RC model.

The rise time of signals propagating across RLC lines improves as the inductance effects of the

line increase This behavior can be explained by referring to Figure 41.4, which depicts the attenuation

of signals as they travel across an RLC line as a function of frequency Higher frequency components

at the edges of a pulse suffer greater attenuation as compared to low frequency components The shape of a signal degrades as the signal travels across a lossy transmission line because of the loss

of these high-frequency components The attenuation constant becomes less frequency dependent

as inductance effects increase or as R /ωL decreases as shown in Figure 41.4 In the limiting case

of a lossless line representing maximum inductance effects, the attenuation constantα is 0 Thus,

as inductance effects increase, a pulse propagating across an RLC line maintains the high-frequency

components in the edges, improving the signal rise and fall times

R= 100 Ω /cm

R= 50 Ω /cm

R= 10 Ω /cm

R= 200 Ω /cm 2

1

0

0 2
10 9 4
10 9 6
10 9 8
10 9 1
10 10

Frequency (Hz)

FIGURE 41.4 Attenuation constant versus frequency L = 10 nH/cm, C = 1 pF/cm, and R is 10, 50, 100,

200, and 400/cm, respectively.

41.4.2 EFFECTS OFINDUCTANCE ONPOWERDISSIPATION

Power consumption is an increasingly important design parameter with mobile systems and high performance, high-complexity circuits such as leading edge microprocessors If the frequency of

switching is f cycles per second, then the dynamic power consumption is described by the well-known

formula,

Pdyn = CtV2

The dynamic power depends only on the total load capacitance, the supply voltage, and the operating frequency As discussed in Section 41.7, increasing inductance effects result in a lower number of repeaters as well as smaller repeater size The smaller size and number of repeaters therefore signif-icantly reduces the total capacitance of the repeaters and, consequently, reduces the total dynamic power consumption

The short-circuit power results from the NMOS and PMOS blocks of a CMOS gate being on simultaneously during the rise and fall times of the input signal, creating a current path between the power supply and ground As discussed in Section 41.4.1, the inductance reduces the rise time of the signals in an integrated circuit, reducing the short-circuit power The short-circuit power consumption

of a gate driven by an RLC line versus the line inductance is plotted in Figure 41.5 Note that as

inductance effects increase, the short-circuit power consumption significantly decreases due to the faster input rise time Also, the smaller repeater sizes dramatically reduces the short-circuit power consumption because the short-circuit power of a CMOS gate is super linearly dependent on the transistor widths Finally, it has been shown in Ref [19] that the short-circuit power consumption

of a CMOS gate decreases as the inductance of the driven net becomes more significant Intuitively, inductance is an element that does not consume any power while resistance consumes power Hence,

as the interconnect behavior becomes dominated by inductance rather than resistance, the power consumption of integrated circuits will be reduced

41.4.3 EFFECTS OFINDUCTIVECOUPLING ONDELAYUNCERTAINTY

In a set of inductively and capacitively coupled lines, the signal propagation delay on a particular line reaches a minimum when neighbor lines are switching in the same direction The delay on that line reaches a maximum when that particular line is switching in opposite direction to neighbor lines because of the increased effective capacitance that has to be charged or discharged The ratio of

2.5 2 1.5 1 0.5

0

Lt (nH )

FIGURE 41.5 Short-circuit energy consumed per cycle by CMOS gate driven by an RLC line versus the

inductance of the line The total resistance and capacitance of the line are maintained constant at 100 and

1 pF, respectively

the maximum and minimum signal delays on a certain signal line can be defined as delay uncertainty

(DU) for that line, as given by

DU = t dmax

For RLC lines, the delay is given by [20]

t d = 1.047 · E · τ LC + 1 · 4 · τ RC (41.12)

where E is a term that depends on the damping factor of this line as described in Ref [20],

τ RC=

k



R k·

r,j

C rj · (α r − α j )



(41.13)

and

τ LC=

k



L k·

r,j

C rj · (α r − α j ) + M k·

l,m

C lm · (α l − α m )



(41.14)

Each line has a switching factor associated with it and is denotedα i for interconnect i The

switch-ing factor takes the values 1, 0, and−1 for lines switching from low-to-high, nonswitching lines,

and lines switching from high-to-low, respectively k runs over all the branches on the path from the primary input to node i on the tree (which i belongs to), r runs over all the nodes downstream of k

on that tree, and j runs over all the nodes to which r has a capacitance connected to In the case of capacitances to ground, j = 0 The index l runs over all the nodes downstream of M kon the coupled

tree (which i does not belong to) The index m runs over all the nodes, which l has a capacitance

connected to

The time constantsτ RCandτ LCdepend on the switching directions of neighbor lines As neighbor lines switch in opposite directions to the line in consideration,τ RCis maximum When neighbor lines switch in the same direction, τ RC is minimum as given by Equation 41.13 On the other hand,

τ LC decreases when neighbor lines switch in opposite directions because of the opposite currents

in neighbor lines, which causes negative mutual inductance terms to appear in Equation 41.14 When neighbor lines switch in the same direction,τ LCincreases because the mutual inductances add

to the self-inductance as in Equation 41.14 This opposite behavior ofτ RCandτ LCresults in reducing the discrepancy between the maximum and the minimum delays of a line because of coupling with other lines

Circuit simulation (Figure 41.6) for the signal on the middle line of three coupled lines shows that

as inductance effects increase, the ratio between the maximum and the minimum delays decreases That is, higher inductive effects lead to lower delay uncertainty and narrower switching windows Lowering delay uncertainty is a positive effect of inductance because narrower switching windows give significant degrees of freedom in physical design to limit noise and control glitches among many other benefits

41.5 INDUCTIVE NOISE

As discussed before, a line can inductively couple to lines that are far away unlike capacitive coupling, which only occurs between adjacent lines The problem of inductive coupling is particularly severe

in wide busses, which are commonplace in most digital integrated circuits such as DSP and micro-processor circuits The width of busses in digital circuits is continuously increasing with technology

Delay uncertainty

Minimum delay Maximum delay

0 50 100 150 200 250

Increasing inductance

FIGURE 41.6 Delay uncertainty dependence on inductance effects The data shown are for the delay of the

middle line of three coupled parallel lines

scaling Hence, the problem of inductive coupling in busses will have even more significance in future technologies

Physically, a wide bus with all the lines switching in the same direction behaves as one wide line Such a wide line has much higher inductance effects as compared to any of the individual lines

in the bus Hence, the effective inductance of a line that is part of a bus is far larger than the self-inductance of that line This fact can also be quantitatively understood by referring to Equation 41.14,

which shows that if all the lines are switching in the same direction, the LC time constant of the line

becomes much larger than the case of an individual line because of all the mutual terms adding to

the self-inductance term This increase in the LC time constant means much higher overshoots and

inductive noise on any line in the bus

To examine the impact of inductance on circuit cross talk in a high-performance 0.18-µm process, the worst-case noise generated on an 8-bit, 3000-µm long, standard data bus was simulated in Refs [9,21] The bus was implemented in metal 6 with all lines having a metal width of 3µm and a metal-to-metal spacing of 1.5µm consistent with typical level metal implementations of

high-performance global busses The data bus was also sandwiched between a VDDline and a GND line each 15-µm wide to provide a return path for the current flowing in the buses The drivers and receivers

were implemented using simple buffers A distributed RLC model for the interconnect was produced

where FastCap [22] was used to model the interconnect capacitance, and FastHenry [15] was used to model both the resistance and the inductance of the interconnects By applying a 5-ps rise time step signal to all the inputs except the one in the middle, SPICE simulations show a totally unacceptable voltage glitch of 1.17 V Such a glitch could cause erroneous switching and logic failures Note that

if the inductance is neglected and not modeled, the cross-talk noise becomes only 0.59 V, which is almost half the value of the actual glitch This shows the importance of modeling on-chip inductance for accurate detection of cross-talk voltage glitches

In terms of substrate coupling, inductance effects increase this type of noise significantly Over-shoots and underOver-shoots owing to inductance cause noise coupling through the common substrate, which is both difficult to measure and difficult to control Substrate noise-conduction modes can

be classified into (1) resistive coupling, (2) capacitive coupling, (3) impact ionization, and (4) body effect (Figure 41.7) All these modes involve currents running into the substrate from the drains or

the sources of transistors and affecting other devices Ideally, the p-bulk is grounded, which always

Contact Contact

n-well

n+ n-well

p+ source

p+ drain

n + drain

p+ bulk

Impact ionization

p-epitaxy

Capacitive coupling Negative transient causing

depletion layer increase

Resistive coupling

FIGURE 41.7 Mechanisms of substrate noise propagation in an integrated circuit.

reverse biases the p −n junctions at the drains and sources of NMOS transistors assuming that ground

is the lowest voltage that can appear at the drain or source of any transistor Similarly, the n-well is connected to VDDto reverse bias the drains and sources of PMOS transistors However, inductance effects cause overshoots and undershoots that can forward bias these junctions resulting in currents flowing into the substrate causing substrate coupling For that reason, substrate coupling noise is sometimes called bootstrap noise Also, if the bulk is biased with a switching ground bus, the ground

on the bulk is not perfect because switching transients will cause voltage drops across the line Hence,

the switching transients on the power supply line can couple to transistors resistively through the p+ bulk contacts The parallel summation of bulk contacts and epitaxy resistances provides a very low

impedance path (nearly short) to the p+ buried layer

The second source of substrate noise is capacitive coupling through the MOSFET source and

drain p − n junctions Each n-well on p+ bulk also introduces fairly large p − n junctions forming

a capacitance between the VDDrails biasing the n-well and the VSSrails biasing the bulk The noise injected into the substrate via capacitive coupling is inversely proportional to the rise time of the signals on the drains and sources of transistors As discussed in the previous section, inductance effects result in faster signal transition times Another source of substrate noise is impact ionization current, generated at the pinch-off point of the NMOS transistors Impact ionization causes a whole current in the bulk A negative bulk transient will increase the depletion region between the source and

the bulk This depletes the channel of charge carriers and increase Vth The total effect is a sporadic

decrease in the IDScurrent In general, these transients increase with higher inductance effects owing

to the higher voltage swings and overshoots

41.6 REQUIREMENTS ON CAD TOOLS AND THEIR PERFORMANCE

The signals that occur in RLC circuits are significantly more complicated than signals in RC circuits For example, the RLC signals shown in Figure 41.1 have overshoots, very large inertial delay, fast

rise time, and are rich in harmonics Hence, new delay models and model order reduction techniques

are required to handle RLC circuits One of the most popular approximate delay models used for the

design and analysis of integrated circuits is the Elmore delay model This first order delay model

cannot be used with RLC circuits with underdamped responses, because underdamped responses

involve complex poles that appear in conjugate pairs Hence, at least a second order approximation

is required for RLC circuits One such model was developed in Ref [17] and maintains the popular

characteristics of Elmore delay

Model order reduction techniques allow the calculation of approximations of higher orders to accurately simulate the interconnect Asymptotic waveform evaluation (AWE) is one popular

tech-nique used successfully with RC interconnects [23] However, AWE cannot calculate enough poles

to handle complex underdamped responses because of numerical errors Hence, a set of new model order reduction techniques have been recently developed that are capable of calculating higher order approximations necessary for simulating systems with complex responses Examples are Pade via Lanczos (PVL) and matrix Pade via Lanczos (MPVL) [24], Arnoldi algorithms [25], block Arnoldi algorithms [26], passive reduced-order interconnect macromodeling algorithm (PRIMA) [27], and SyPVL algorithm [28] However, these model order reduction techniques can have significantly higher computational complexity than AWE Hence, there is a need for innovative simulation

techniques for handling complex responses arising in RLC circuits.

Another feature that complicates the analysis and design of integrated circuits including on-chip inductance, is the far-reaching inductive coupling to other lines in the integrated circuit Typically, a line in a wide bus couples to all the lines in the bus As compared to capacitive coupling, which only couples a line to the immediate neighbors, inductive coupling results in larger circuits (the whole bus rather than three lines) to be analyzed, and these circuits have a significant amount of inputs

In general, all CAD tools will run significantly slower when using an RLC model as compared

to an RC model This behavior is simply due to the more complex model used and the higher

signal integrity issues involved In addition to the lower performance of CAD tools, a very large

infrastructure of RC-based CAD tools needs to be modified to include inductance effects.

41.7 PHYSICAL DESIGN INCLUDING INDUCTANCE EFFECTS

Currently, the industry applies a three-step design process for integrated circuits when handling inductance First, employ design methodologies and techniques to reduce the inductance effects in

the design Second, use the well-developed RC-based design tools to optimize and verify the circuit.

Third, pray nothing will go wrong However, as discussed in this chapter, inductance can have useful effects such as improving the rise time of signals, reducing the power consumption, and reducing the

number of inserted repeaters Hence, by suppressing inductance effects and using RC-based tools,

a suboptimal circuit results in terms of area, power consumption, and speed Also, signal integrity and cross-talk issues owing to inductive coupling are neglected, which can result in undetected reliability problems Fortunately, in recent years many researchers have started modifying design methodologies and physical design to include inductance rather than suppressing it A sample of these works is discussed in this section

Including inductance in interconnect routing has been dealt with in several works An example

is the work in Ref [29] The work mainly deals with reducing capacitive and inductive cross talk within the interconnect during full chip routing The work shows a reduction in cross talk by a factor

of 2.5 while increasing the routing area with less than 5 percent as compared to an algorithm that does not include cross talk In wide busses, inductive cross talk can sometimes exceed capacitive coupling when all lines switch in the same direction

Repeater insertion is another common design methodology for driving long-resistive interconnect

(e.g., Refs [3–5]) Because the RC time constant of a line is given by RtCt = RCl2 and has a square dependence on the length of the line, subdividing the line into shorter sections by inserting repeaters is an effective strategy for reducing the total propagation delay Currently, typical high-performance circuits have a significant number of repeaters inserted along global interconnect lines These repeaters are large gates and consume a significant portion of the total circuit power

As discussed in Section 41.2, the amount of inductance effects present in an RLC line depends

on the ratio between the RC and the LC time constants of the line Hence, as inductance effects increase, the LC time constant dominates the RC time constant and the delay of the line changes

from a quadratic to a linear dependence on the line length [18] As a consequence, the optimum number of repeaters for minimum propagation delay decreases as inductance effects increase In the

limit, an LC line requires zero repeater area to minimize the overall propagation delay.

Inserting repeaters based on an RC model and neglecting inductance result in a larger repeater

area than necessary to achieve a minimum delay The magnitude of the excess repeater area when

TABLE 41.4

Total Repeater Area, Total Power, and Total Maximum Path Delay of All of the Trees

Area (minimum inverters) 0 — 14,116 40.8 23,854 Maximum delay (ps) 6,554 42.2 3,787 6.7 4,061 Power (pJ/cycle) — — 1,379 15.6 1,632

The percent savings shown here represent the average savings in area, power, and maximum path delay when using an RLC

model for repeater insertion

using an RC model depends upon the relative magnitude of the inductance within the RLC tree The

reduced number of inserted repeaters also simplifies the layout and routing constraints Also, the reduced repeater area greatly reduces the power consumed by the repeaters in an integrated circuit

A more thorough analytical analysis of the effect of inductance on the repeater insertion process can

be found in Ref [18] Practical data are listed in Table 41.4 for repeaters inserted in a large number

of typical copper interconnects from a 0.25-µm CMOS technology [30] Note that by using an RLC model rather than an RC model, a better delay can be achieved with significantly less repeater area

and power consumption by the repeaters

Inductance plays a central role in power and clock distribution networks [31–36] Typically, the inductive characteristics of the clock distribution network are intimately related to the power distribution network The return currents from the clock determine the size of the inductive loop These currents typically return in the wide, low-resistance, power distribution network wires The clock wires are typically wide enough to exhibit significant inductance effects Full transmission line models are needed for these wires when sizing the clock distribution network Several works (such

as Refs [34,35]) have dealt with these clock distribution design including inductance

In terms of the power distribution networks, inductance does dominate the total impedance of the network [31–36] Electromigration poses an upper limit on the current density carried by the power distribution networks Because of the unidirectional nature of the currents carried by the power distribution network, it is crucial to upsize these wires to meet the upper bound on current density Hence, power distribution networks typically have very wide wires that exhibit significant inductance effects However, typically a power distribution network is designed with interleaving

VDDand GND lines on each layer This design results in inductive coupling typically limited to adja-cent wires with opposing currents canceling at far distances Hence, inductance in the power grid can be easily modeled using loop inductance models rather than partial inductances Interestingly, designers have found ways to justify ignoring inductance in power distribution networks despite its dominance The justification is typically that currents taken from the power distribution network are

DC There is no experimental data that supports this claim In fact, in synchronous circuits, most of the currents are drawn around the clock edges, giving rise to very large current slopes Several works have considered inductance in the power distribution network However, accurate estimation of the currents drawn from the power distribution network remains crucial

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42 Clock Network Design: Basics

Chris Chu and Min Pan

CONTENTS

42.1 Metrics for Clock Network Design 882

42.1.1 Skew 882

42.1.2 Transition Time 882

42.1.3 Phase Delay 883

42.1.4 Area 883

42.1.5 Power 883

42.1.6 Skew Sensitivity to Process Variations 883

42.2 Clock Networks with Tree Structures 883

42.2.1 Method of Means and Medians 884

42.2.2 Geometric Matching Algorithm 884

42.2.3 Exact Zero-Skew Algorithm 885

42.2.4 Deferred Merge Embedding 887

42.2.5 Wire Width and Buffer Considerations in Clock Tree 888

42.3 Clock Networks with Nontree Structures 889

42.3.1 Grid 889

42.3.2 Spine 889

42.3.3 Hybrid 890

42.4 Clock Skew Scheduling 891

42.5 Handling Variability 893

References 894

A vast majority of VLSI chips are based on a synchronous sequential circuit design methodology For these circuits, a clock signal is used to synchronize the operations of different components across the chip Typically, this signal is produced by a clock generator circuit based on an external reference, and it is distributed inside the chip by a clock network Because the timing of the entire chip is controlled by the clock signal, a poor design of the clock distribution network will limit the performance of the chip As the clock network connects the clock generator to a huge number of clocked elements (including latches, flip-flops, memories, and dynamic gates) all over the chip and it has high switching activity, it usually consumes a significant portion of the overall routing resources and of the total chip power Hence the clock network must be carefully designed to optimize the performance of the chip, routing resource usage, and power consumption

This chapter discusses some basic issues in clock network design In Section 42.1, the metrics used in designing clock networks are introduced In Sections 42.2 and 42.3, algorithms to generate clock networks with tree structures and nontree structures are described, respectively In Section 42.4, the clock skew scheduling technique, which makes use of intentional clock skew to optimize per-formance, is introduced In Section 42.5, clock network design techniques that focus on handling variability are presented In Chapter 43, the clock network designs of several high-performance

881