Handbook of algorithms for physical design automation part 89 pptx

Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C041 Finals Page 867 24-9-2008 #4TABLE 41.1 Circuit Simulation of a 4-Bit Bus All Lines Are Switching in the Same Dire

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Part IX

Designing Large Global Nets

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in Global Nets

Yehea I Ismail

CONTENTS

41.1 Historical Perspective 865

41.2 Importance of Inductance in Current and Future Technologies 866

41.3 Extraction and Physical Representations of Inductance 869

41.4 Effects of Inductance 871

41.4.1 Effects of Inductance on Delay and Signal Rise Time 872

41.4.2 Effects of Inductance on Power Dissipation 873

41.4.3 Effects of Inductive Coupling on Delay Uncertainty 873

41.5 Inductive Noise 874

41.6 Requirements on CAD Tools and Their Performance 876

41.7 Physical Design Including Inductance Effects 877

References 878

41.1 HISTORICAL PERSPECTIVE

Historically, the gate parasitic impedances have been much larger than interconnect parasitic imped-ances because the gate geometries (the width and length) were quite large (about 5µm was a typical minimum feature size in 1980) Thus, interconnect parasitic impedances have historically been neglected and the interconnect was modeled as a short circuit With the scaling of the minimum gate feature size, interconnect capacitances have become comparable to the gate capacitance, requiring the interconnect to be modeled as a single lumped capacitance that is added to the gate capacitance With this interconnect model, new design techniques emerged to drive large capacitive loads associ-ated with long global interconnects and large interconnect trees with high fanout Cascaded tapered buffers are used to minimize the propagation delay of CMOS gates driving these large capacitive loads (e.g., [1,2])

With increasing device densities per unit area, the cross-sectional area of interconnects has been reduced to provide more interconnect per unit area Also, the improved yield of CMOS fabrica-tion processes permits manufacturing larger chips with higher reliability Thus, the global wires connecting modules across an IC have increased in length Both the decreased cross-sectional area and the increased wirelength have caused the global wire resistances to dramatically increase The interconnect model now includes the resistance of the interconnect Including resistance in the inter-connect model dramatically changed the design and analysis of integrated circuits, e.g., [3–5] With

a short circuit or a capacitive interconnect model, the interconnect could be treated as a single node However, by including the series resistance, the interconnect is composed of multiple nodes, each node having a different voltage waveform This characteristic has greatly complicated the analysis of circuits with resistive interconnect Completely new problems and design techniques have emerged

due to the transition from a capacitive to an RC model such as RC tree analysis techniques, clock

skew problems, repeater insertion techniques, power consumption estimation, model order reduction

865

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techniques, and IR drops in the power supply, to name a few Almost every aspect of the design and analysis of integrated circuits was affected by the new interconnect model

The rest of this chapter summarizes the importance, effects, and issues involved in a transition

from an RC interconnect model to an RLC model, which includes the inductance of the interconnect.

This transition has the potential to change all aspects of the design and analysis of integrated circuits in

analogy to the transition from a capacitive to an RC interconnect model However, unlike the transition from a capacitive to an RC model, which only resulted into undesirable effects, the increasing

inductance effects can have several desirable consequences, which are pointed out later

41.2 IMPORTANCE OF INDUCTANCE IN CURRENT AND FUTURE

TECHNOLOGIES

On-chip inductance has currently become more important with faster on-chip rise times and wider wires Wide wires are frequently encountered in clock distribution networks and in upper metal layers These wires are low-resistance lines that can exhibit significant inductive effects Furthermore, performance requirements are pushing the introduction of new materials such as copper interconnect for low-resistance interconnect and new dielectrics to reduce the interconnect capacitance These technological advances increase the importance of inductance

On-chip inductance can cause significant errors in current deep-submicron technologies For example, three sets of simulation∗ results are presented based on IBM’s 0.1-µm technology to illustrate the importance of on-chip self and mutual inductances The first example is a four-bit coupled bus (Table 41.1) The second example is a tree coupled with two lines (Table 41.2) And the third example is a pair of lines coupled with each other (Table 41.3) In all three examples, simulations are done for three cases In case I, self and mutual inductances are not included That

is, signal lines are considered as standard RC lines with coupling capacitances only In case II, self-inductance is included, and lines are considered as RLC lines with coupling capacitance, but

no coupling inductance In case III, both self and mutual inductances are included and lines are

considered as RLC lines with coupling capacitance and mutual inductance Results show that the error

owing to neglecting inductance can be more than 100 percent for the delay calculation and 70 percent

in the rise time What makes these errors even more serious is that neglecting inductance and using

an RC model always results in underestimating the propagation delay (e.g., see Figure 41.1) Thus, VLSI circuits designed using an RC interconnect model may not satisfy the assigned performance

targets despite a worst-case analysis being applied in the circuit design process

In general, there are two factors controlling the error between an RC model and an RLC model These two factors are the damping factor of an RLC line and the ratio between the input signal rise time to the time of flight of signals across the line [7] The damping factor of an RLC

line is given by

2

C

where

R, L, and C are the resistance, inductance, and capacitance per unit length of the line, respectively

l is the length of the line

The damping factor of the line represents the degree of attenuation the wave suffers as it propagates

a distance equal to the length of the line As this attenuation increases, the effects of the reflections

decrease and the RC model becomes more accurate Note that the damping factor is proportional to

∗ Circuit simulations in this section are either performed using HSPICE or IBM’s circuit simulation tool AS/X [6].

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TABLE 41.1 Circuit Simulation of a 4-Bit Bus

All Lines Are Switching in the Same Direction Case Deviation (percent)

TABLE 41.2 Circuit Simulation of a Coupled Tree Network

TABLE 41.3 Circuit Simulation of a Pair of Coupled Lines

VDD

RC

FIGURE 41.1 Signal behavior on one net of a 4-bit bus.

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the length of the line and thus very long lines will exhibit less inductance effects Alternatively, the damping factor can be expressed as

ξ = RtCt

2√

LtCt

= τRC

2τLC

(41.2)

where

Rt, Lt, and Ct are the total resistance, inductance, and capacitance of the line, respectively

τ RCandτ LC are the RC and LC time constants of the line

This relation illustrates the fight between the RC and LC time constants of the line A reduction in the RC time constant results in a direct increase in the inductance effects exhibited by the line Note

that many of the technological advancements that have been achieved or are still in development

target reducing the RC time constant Examples are copper interconnect, dielectrics with lower εr, and superconductive interconnects Also, many of the design methodologies used to reduce the delay

of critical lines concentrates mainly on reducing the RC time constant of the line, such as using wider wires, wider drivers, and repeater insertion In the limit, if the RC time constant of a line is sufficiently

reduced, the line will behave as a lossless transmission line and signals can be transmitted across the line with the speed of light

The other factor determining inductance effects is the ratio between the input signal rise time to the time of flight of signals across the line and is given by

tr

2l√

where tris the rise time of the input signal As this ratio increases, the line can be more accurately

modeled as an RC line Note that in this case the relation implies that shorter lines will suffer less inductance effects mainly because the rise time of the input signal will override the LC time constant.

Hence, there is a range of the length of the interconnect for which inductance effects are significant with very short and very long lines suffering no inductance effects [7] Note that the rise times of input signals to the interconnect are becoming faster all the time with technology scaling, increasing inductance effects in future technologies Even if some techniques can be applied today to reduce the

effect of inductance allowing the use of the well-developed RC-based CAD tools, inductance effects

will be very hard to suppress or ignore in future technologies and CAD tools have to be modified to include the effect of inductance

Equivalent figures of merit for trees were developed in Ref [8] to characterize the importance

of on-chip inductance These expressions at node i of a tree are given by

ζ i= 1 2

k

C k R ik

k

C k L ik

(41.4)

and

k

respectively, where R ik (L ik ) is the common resistance (inductance) from the input of the tree to nodes

i and k and k runs over all the capacitances in the tree.

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41.3 EXTRACTION AND PHYSICAL REPRESENTATIONS OF INDUCTANCE

Each interconnect line has an associated self-inductance and an associated mutual inductance to other lines in the circuit Unlike the resistance and capacitance of interconnect lines, both self and mutual inductances are loop quantities, and they can be determined only if the whole current loop is known; i.e., the exact path in which the current returns to the source is known The self-inductance of a loop is defined as the flux linked through the loop because of the variation in the current flowing in the loop divided by the value of the current The current loop also has corresponding coupling inductances that couple the current loop to surrounding current loops The coupling inductance is the flux caused

by an aggressor loop linked to a given loop divided by the value of the aggressor current [9] The current return path is frequency dependent At low frequency, the inductive impedance

(ωL) is less than the resistive impedance (R) Hence, the current tries to minimize the interconnect

impedance and thus tries to minimize the interconnect resistance This causes the current to use as many returns as possible to have parallel resistances, as shown in Figure 41.2 [9] However, at high frequencyωL > R and the current tries to minimize interconnect impedance by minimizing the

loop inductance This causes the current to use the closest possible return path to form the smallest possible loop inductance, as shown in Figure 41.2 [9] The current would be confined to the nearest possible return only at ultra-high frequencies (higher than 20 GHz) [10] Therefore, at current clock frequencies, current can spread into a number of possible current return paths This behavior makes the extraction of inductance a nontrivial task as it tremendously increases the number of surrounding interconnects that have to be considered The distribution of the current into different wires as a function of frequency is typically referred to as proximity effects, while the confinement of current

in parts of an interconnect, as shown below, is referred to as skin effect

To limit the complexity of the problem, the inductance can be approximated [11] by assuming that the current return path is limited to the nearest power or ground line Other approaches such

as in Ref [12] incrementally improve the accuracy by adding more ground lines to the return path until the extracted inductance is accurate enough One way to go around the prerequisite of knowing the actual current return paths beforehand is by using the three-dimensional (3D) field solver A common approach that is used by 3D solvers is to extract inductance by applying a finite difference

or finite element method to the governing Maxwell equations in differential form Such an approach generates a global 3D mesh for all parts of analyzed structure and for surrounding external space This causes the number of unknowns to increase significantly, and thus a very large linear system can be generated Solving this large linear system requires excessive memory and consumes long CPU time, which makes inductance extraction of complex 3D structures using finite element or finite difference methods impractical

The other approach used in inductance extraction employs the partial element equivalent circuit method (PEEC) [13,14] Using PEEC, only the volume of the conductors needs to be discretized

High frequency

Low frequency Signal

Signal

FIGURE 41.2 Frequency dependence of current distribution across signal and ground lines.

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Thus, using the PEEC method produces a fewer number of unknowns than finite elements and dif-ferences The integral formulation of the PEEC method is used in the widely known MIT inductance extraction program, FastHenry [15]

Hence, inductance extraction is a nontrivial process However, there are two characteristics of on-chip inductance that can be exploited to simplify the extraction process of on-chip inductance First, the sensitivity of a signal waveform to errors in the inductance values is low compared to sensitivity to errors in resistance and capacitance values, particularly the propagation delay and rise time Second, the value of the on-chip inductance is a slow varying function of the width of the wire and the geometry of the surrounding wires [16]

The first characteristic can be explained by the fact that inductance only appears under a square root function in a waveform or timing expression characterizing a signal The reason for this square

root dependence is physical because an LC constant has the dimensions of time squared, where L and

C are any inductance and capacitance values in the circuit, respectively The square root dependence

can be compared to the linear dependence of the delay expressions on the resistance because any RC constant has the dimensions of time, where R is any resistance of the circuit For example, according

to the equivalent Elmore delay for RLC trees that was introduced in Ref [17], the 50 percent delay

of the signal at node i of an RLC tree is

tpdi = 1.047 ·

k

C k L ik· e− ζi0.85 + 0.695 ·

k

whereζ i is the damping factor at node i and is

ζ i= 1 2

k

C k R ik

k

C k L ik

(41.7)

Note that inductance only appears under a square root This fact is also evident in Equations 41.8 and 41.14

As an example, circuit [6] simulations are performed for an RLC tree with no inductance (an RC

model), and with all of the inductance values increased by 10, 20, and 30 percent These simulations are depicted in Figure 41.3 Note in the simulations that using an approximate inductance estimation

Vo1

2.50 3.00

2.00 1.50 1.00 0.50

(a)

Time (ns)

FIGURE 41.3 Circuit simulations of an RLC tree with the actual inductance values, with no inductance (an RC

model), and with all of the inductance values increased by (a) 10 percent

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Vo1

2.50 3.00 3.50

2.00 1.50 1.00 0.50 0.00

20 percent error in extracted inductance values

Actual inductance values

Rough inductance values

(b)

Time (ns)

Vo1

2.50 3.00 3.50

2.00 1.50 1.00 0.50 0.00

30 percent error in extracted inductance values

(c)

Time (ns)

FIGURE 41.3 (continued) (b) 20 percent, and (c) 30 percent.

greatly improves the accuracy of the waveform as compared to using an RC model Even with a 30

percent error in the inductance values, the propagation delay differs by 9.4 percent from the actual

value as compared to 51 percent if an RC model is used The improvement in the rise time is even

greater The rise time differs from the actual value by 5.9 percent with a 30 percent error in the

inductance values as compared to a 71 percent error when an RC model is used The maximum

error in the waveform shape occurs around the overshoots (Figure 41.3) However, estimating the overshoot requires less accuracy because the overshoot is usually evaluated to decide if the overshoot

is within an acceptable limit This high tolerance of the delay expressions to errors in the extracted inductance combined with the slow variation of extracted inductance values with changes in geometry encourage the use of simplified techniques with higher computational efficiency to extract the on-chip inductance

41.4 EFFECTS OF INDUCTANCE

This section briefly discusses the effects of inductance on the performance of integrated circuits The effects of inductance on signal delay and rise time, power consumption, and delay uncertainty are discussed

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