Handbook of algorithms for physical design automation part 72 ppsx

Alpert/Handbook of Algorithms for Physical Design Automation AU7242_S007 Finals Page 693 24-9-2008 #2Part VII Manufacturability and Detailed Routing... Alpert/Handbook of Algorithms for

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Alpert/Handbook of Algorithms for Physical Design Automation AU7242_S007 Finals Page 693 24-9-2008 #2

Part VII

Manufacturability and Detailed

Routing

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Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 Finals Page 695 24-9-2008 #2

Lithography

Franklin M Schellenberg

CONTENTS

35.1 Introduction 696

35.1.1 Modeling in a Design Flow 696

35.1.2 Lithographic Processing 697

35.2 Lithographic Modeling 699

35.2.1 Introduction 699

35.2.2 Lithographic Modeling Fundamentals 699

35.2.2.1 Maxwell’s Equations 700

35.2.2.2 Propagation 701

35.2.2.3 Linearity 703

35.2.2.4 Computation by Superposition 704

35.2.3 RET Tools 705

35.2.3.1 OPC 706

35.2.3.2 PSM 707

35.2.3.3 OAI 710

35.2.3.4 RET Combinations 711

35.2.3.5 Polarization 712

35.2.4 RET Flow and Computational Lithography 713

35.2.5 Mask Manufacturing Flow 715

35.2.6 Contour-Based EPE 715

35.3 Simulation Techniques 717

35.3.1 Introduction 717

35.3.2 Imaging System Modeling 717

35.3.3 Mask Transmission Function 720

35.3.3.1 FDTD 720

35.3.3.2 RCWA and Waveguide Techniques 723

35.3.3.3 DDM 723

35.3.4 Wafer Simulation 723

35.4 EDA Results 725

35.4.1 Process Windows 726

35.4.2 MEEF 727

35.4.3 PV-Bands 728

35.4.4 Extraction 731

35.5 Conclusion 731

References 731

695

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696 Handbook of Algorithms for Physical Design Automation

35.1 INTRODUCTION

35.1.1 MODELING IN ADESIGNFLOW

Electronic design automation (EDA) for integrated circuits, and especially digital circuits, by and large concerns itself with computer algorithms for the arrangement and interconnection of transistors [1] These are often fairly abstract representations of an IC Design, and their use and optimization

is generally an application of algorithms in computer science At some point, however, an IC layout must be generated and fabricated as actual structures on a silicon wafer It is at this point where process modeling and simulation must enter the domain of EDA

To fabricate an IC, numerous processes are employed: doping of materials, deposition of thin film layers, planarization, and etching or removing material, among others [2–4] Most of these processes are bulk processes, carried out on an entire wafer or batches of wafers at one time, but each can leave its signature on the individual features as they are fabricated These differences between the ideal, as-designed layout and the final as-manufactured device can be trivial and insignificant, or can cause the device to fail utterly, depending on the sensitivity to variation

Technology CAD (TCAD) tools have existed to model aspects of certain processes and devices ever since these processes and devices came into existence [5] TCAD tools typically set up a physics-based model of a structure or process, and are used to examine these physical structures in great detail They have served as useful tools for research scientists and process engineers to study the relationships between different process variables and predicted device properties They can be extremely cost effective, in that one can run a virtual experiment without incurring the expense of a complicated, multivariable experiment in a silicon clean room These tools, however, are generally run off-line—that is, they are tools for simulating small, representative samples of layouts or devices

in great detail to guide experts in process and device engineering These are not tools for the simulation

of entire layouts

With the advent of inexpensive parallel processing for computing, simulation tools are now becoming more streamlined and their use on entire layouts can be reconsidered A typical EDA flow [6] incorporating a process model is shown in Figure 35.1 In this flow, once the physical layout has been created in a layout format such as GDS-II [7] or OASIS [8], a model is called to transform

Synthesis

Place and Route

Maskmaking Lithography

RTL SPICE

Model

Extracted netlist

Extraction Simulation result

Yield prediction

Model Correction

Netlist Layout

Modified layout Mask Wafer

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this layout into a new version that represents what is expected on the wafer Sections of a layout, discrete cells, or the entire layout can be simulated, depending on the desired outcome The output of this model is typically represented as a set of contours, and stored as new data layers in the layout file Extraction tools can then be used on this modified layout, and the suitable SPICE models used

to predict the expected electrical behavior of the manufactured result [9] If the results deviate too much for the desired electrical specifications, the information is passed back into the earlier design flow in the form of new constraints or rules would prevent this specific deviation from occurring, and that the upstream tools must now consider in creating revised versions of the IC

There are other processing steps besides lithography that can be modeled Bulk processing steps such as plasma etching or chemical–mechanical polishing (CMP) are broadly understood, but detailed modeling behavior, especially on individual feature scale, is still an active area of research [10–12] And, even if perfectly understood, the ability to quantify and manage statistical variation expected in these processes also affects the yield expected for a particular design [13] Coping with variation in

IC modeling and incorporating those results into EDA tools for improved IC performance and yield remains an active topic of research [14] A number of related issues are described in Chapter 36

On the other hand, various analysis tools such as Critical area analysis (CAA) [15–18] or various density metrics [19] can be applied once simulated results have been generated, to better estimate expectations of real wafer yield Such analysis tools are currently run on layouts generated by EDA tools, but their use with simulated wafer results can lead to a more accurate estimation of real yield [20] The accuracy of the overall yield model then depends on the accuracy of the underlying model used for the simulation A more detailed discussion is provided in Chapter 37

35.1.2 LITHOGRAPHICPROCESSING

The most commonly used process for detailed patterning has been relatively well understood in principle for nearly a century This process is optical lithography [21] The processing steps for optical lithography are illustrated in Figure 35.2 To begin, a photomask, sometimes called simply a mask but more precisely referred to as a reticle, is retrieved from its storage location The mask is a flat piece of quartz coated with an opaque layer (usually chrome) written with the layout patterns required for a particular layer (e.g., poly, contact, metal-1, etc.) This serves as the master for patterning the wafers, analogous to a negative for printing conventional photography This photomask is mounted

in a projection printer, which forms a miniaturized image of the mask (usually four times smaller) using a highly precise multielement lens system

The lithographic process flow starts by loading wafers in the processing system (called a track) and preprocessing them This involves an initial cleaning, to remove any particles or contaminants, coating with photosensitive polymer, called a photoresist, and sometimes a baking step, to drive

Load mask

Wafer coating Prebake Align wafer to mask Photoexposure Postexposure bake Development Etch/deposition

FIGURE 35.2 Typical steps in an optical lithography process.

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any remaining solvent out of the photoresist Once prepared, the wafer is then transferred into the optical projection system for exposure The wafer is aligned precisely to the patterns on the photomask to minimize overlay errors, and a timed exposure of the image of the photomask is made onto the photosensitive polymer With photoexposure, the polymer properties (usually the polymer solubility) change The wafer is subsequently transferred back to the track and further processed (e.g., developed) to selectively remove the more soluble materials, leaving resist polymer in a local pattern corresponding to the patterns in the IC layout

This wafer will then be used in the subsequent processing step Only the uncovered regions experience the desired process action (e.g., material deposition, etching, etc.) The regions that remain covered by the polymer are protected and remain unchanged (hence the name – they resist the process) [22]

Typically, a photomask will contain the layouts for the appropriate layers (e.g., gate, contact, etc.) for only a few chips (or, for a complex microprocessor, a single chip) Repetition throughout the wafer, allowing hundreds of chips to be printed on a standard 300 mm diameter silicon wafer, occurs by moving the wafer stage under the photomask and making a succession of exposures until exposures have been made for all chips on the wafer Projection exposure equipment is commonly called a stepper, because the wafer is stepped from exposure to exposure

Lithographic patterning processes are superb examples of the highest precision imaging ever achieved With contemporary processing, light with a wavelength ofλ = 193 nm is being used to

produce ICs with dimensions of 65 nm, and even being considered for the next generations as well, which have features as small as 45 nm or 32 nm [23] However, certain limitations inherent in the patterning and subsequent processing steps can distort the transfer of the pattern from the desired, ideal layout When projection optical lithography was initially introduced in the manufacture of ICs, the wavelength of the light used to form patterns was much smaller than the individual feature sizes

As a result, there was very little image distortion, and the patterns on the wafer appeared essentially

as designed The alignment and overlay of these features was a more critical concern

As Moore’s law [24] continued to push transistors to be ever smaller, in 1998 the feature size became smaller than the wavelength used for manufacturing This is shown in Figure 35.3 [25,26]

Year 1980

0.01

1

10

10 100

1,000

365 nm

130 nm

90 nm

65 nm

Lithography wavelength

Feature size

248 nm

193 nm

13 nm EUV

193 nm + i

10,000

1990 2000 2010 2020

Gap

FIGURE 35.3 Evolution of lithography wavelength and IC feature size (Data from Bohr, M., Intel’s 65 nm

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Now, significant process distortions were routinely occurring on the wafer, and without correction, wafer yield would be impacted Although some relief was provided by introducing lithography technology using immersion, with the shrinking of IC dimensions to be smaller than 100 nm, these distortions are significant, and unless compensated, IC yield drops to zero Process modeling for lithography is therefore essential for the design of manufacturable ICs in this sub-wavelength world

In this chapter, I give an overview of the requirements of lithography modeling for subwavelength EDA flows In Section 35.2, I describe the physics of optical image formation for lithography, and the various lithographic techniques that must be modeled This is essentially the framework in which the models must fit to describe the lithographic process In Section 35.3, I describe some of the mathematical techniques used to compute specific results that fit into the framework of Section 35.2 Finally, in Section 35.4, I describe some of the issues encountered in the implementation of the models in contemporary EDA software

35.2 LITHOGRAPHIC MODELING

35.2.1 INTRODUCTION

In this section, the fundamental steps of a lithographic process are described, along with the techniques used to represent lithography in models Then, the most frequently used configurations of models needed for the implementation of various resolution enhancement techniques (RETs) are presented The fundamental elements of the lithographic patterning process are shown in Figure 35.4 Light from a source (typically UV light from a lamp or an excimer laser) is shaped by the illumination system

to control intensity uniformity, polarization properties, and angular spectrum This light illuminates the photomask, patterned with the layout for the particular layer to be reproduced A very large and complex lens system then forms an image of the photomask (typically reduced in linear dimension by

a factor of four) on the resist-coated silicon wafer The wafer may actually be coated with a number

of layers that complicate exposure considerably For immersion lithography systems, the lens–wafer gap itself may be filled with a fluid (typically water) to enhance imaging fidelity [27] Once exposed, the patterns are developed and the wafer moved on to the next process step

35.2.2 LITHOGRAPHICMODELINGFUNDAMENTALS

Although the imaging systems are very complex, with lenses containing over 20 precision optical elements and costing several million dollars, modeling this process is actually a fairly straightforward procedure This is due to the following:

Mask

Illumination

UV

Lens

Wafer

FIGURE 35.4 Elements of a typical lithographic exposure system (After Schellenberg, F M., EDA for IC

Implementation, Circuit Design, and Process Technology, L Scheffer, L Lavagno, and G Martin, Eds., CRC

Press, Boca Raton, FL, 2006.)

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1 Light in the system is an electromagnetic wave, governed by Maxwell’s Equations [28]

2 Propagation through the illumination system is generally collimated, and therefore can be modeled by the approximations for far-field diffraction

3 All optical processes in the stepper (aside from the possible generation of the initial source photons) can be represented by a linear superposition (typically of electric fields, however, under some circumstances, using field intensity)

4 Imaging for complex illumination systems and layout patterns can be modeled with a suitable linear superposition of subcomponent systems (because of (3))

35.2.2.1 Maxwell’s Equations

All electromagnetic phenomena can be described through the use of the well-known Maxwell equations [28,29]:

∇ × E = −µ ∂ H

∇ × H = ε ∂ E

where

E and H represent the vector electric and magnetic fields, respectively

ε and µ the electric permittivity and magnetic permeability of the material in which the fields

exist

ρ represents the electric charge density

σ the electrical conductivity

When combined, and in the absence of charges and currents, a wave equation is formed [29]

∇2E − n2

c2

∂2E

where the refractive index n is defined relative to the permittivity ε0 and permeabilityµ0 of the vacuum by

n=

ε

ε0

µ

µ0

(35.3)

and c is

c= √µ10ε0

= 2.998 × 108

This corresponds to the speed of light in a vacuum (which has n = 1) The value of n, which is better known as the refractive index of the material, relates the speed v of a wave in a material to the speed

of light in a vacuum

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c is related to the physical properties of wavelength ( λ, λ0in vacuum) and frequency v of the wave

through

v= c

n = λν = λ0ν

In the presence of charges and currents, the wave equation becomes

∇2E − n2

c2

∂2E

∂t2 − µσ ∂ E ∂t = 0 (35.7) For most situations, this simply becomes a more complex wave, in which the refractive index can be represented by a complex number

where

n represents the ratio of speeds as before

κ (kappa) represents a loss related to electrical conductivity σ as the wave propagates through

the material, and is sometimes called the extinction coefficient

35.2.2.2 Propagation

When a collimated wave propagates through a well-behaved medium, the propagation of waves

from an extended source P S at some point P a distance r paway can be represented by an integral of spherical waves emitted from across the source:

E (P) =

S

M (P S )e+i(2π/λ)rp

r p

where M (P S ) is a representation of the field strength (or amplitude) and phase at various points

P S in the source This illuminating source can in turn fall on a mask, with a transmission function

M (x, y) The mask acts as a secondary source, and the integral of Equation 35.9 applies again, this

time with the mask function describing the source In the far field, when the light is monochromatic (λ constant), the transmission through the mask becomes a function of the patterns on the mask,

E (p, q) ∝ −ie+i(2π/λ)R0+Rp

R0R p

M

M (x, y)e −i(2π/λ)(xp+yq)dx dy (35.10)

where the R0and R pfactors are geometric distances from the source to the mask, and the and each point in the mask having both a transmission value (typically 0 or 1) and a phase shiftφ This is

called the Fraunhofer diffraction formula, and it is clear that, with the exception of the phase factor

in front, the far field amplitude pattern will be proportional to the 2D Fourier transform [30] of the

mask function M (x, y) The approximation that the mask can be represented by this infinitely thin

transmission function is sometimes called the Kirchhoff boundary condition [29]

Although electromagnetic wave propagation can occur in arbitrary directions, for most optical systems, the direction of propagation is very well defined Light falls on a mask at near normal incidence, and diffracts at relatively small angles (typically less than 20◦) When a simple lens of

focal length f is inserted into the optical path, the lens introduces a quadratic phase factor:

L (a, b) = e −i(2π/λ)(1/f )(a2+b2) (35.11)

where a and b are the Cartesian coordinates in the lens plane.

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