Handbook of algorithms for physical design automation part 47 pps

With the availability of OpenAccess [64] and the OpenAccess gear timer [65,66], it is possible to push the frontier of the very successful International Symposium on Physical Design ISPD

cons A hybrid approach is proposed recently [15] to combine the netweighting and net constraints together with LP-based formulations Furthermore, because of the complexity of modern placement problems and the iterative refinement nature from global placement to detailed/legal placement, it

is very important to have stability between placement iterations In this section, we present several representative and recent techniques for TDP and timing-aware placement

21.6.1 HYBRIDNET ANDPATH-BASEDAPPROACH

In Ref [15], a hybrid approach is proposed to combine the netweighting and net constraints together with LP-based formulations The net-based approaches, especially the netweighting, have low com-putational complexity and high flexibility/scalability Therefore, net-based approaches have more advantages as the circuit complexity continues to increase However, netweighting often completely ignores slew propagation Because timing is inherently path based, an effective netweighting algo-rithm should be based on path analysis and consider timing propagation Furthermore, net-based approaches are often done in an ad hoc manner and may have problems with convergence For instance, while the delay on critical paths decrease, other paths become critical, and this leads

to a convergence problem A systematic way of explicit perturbation control is important for netweighting-based algorithms The hybrid approach in Ref [15] uses a hybrid net and path-based delay sensitivity with limited-stage slew propagation as basis for netweighting The objective func-tion is the weighted wirelength for a set of critical paths The LP formulafunc-tion considers not only cells on the timing-critical paths, but also cells that are logically adjacent to the critical paths in a unified manner, through weighted LP objective function and net-bound constraints This approach

is suitable for incremental timing improvement

21.6.2 HIPPOCRATES:A DETAILEDPLACER WITHOUTDEGRADINGTIMING

Another timing-driven incremental placement algorithm [60] helps to reduce TWL and improve timing at the same time It specifically maintains the timing constraints while reducing wirelength during detailed placement The detailed placement algorithms it uses can be any commonly used move-based transforms, i.e., cell swapping, cell moving, etc Instead of modeling path constraints, it models the timing constraints at each input pin The advantage of this is that it reduces the computation complexity, which allows it to model timing constraints on every timing path Therefore, the output

of this algorithm guarantees no timing degradation The timing constraint on each pin is called delta arrival time constraint, which is defined as the difference of arrival time at this pin to the arrival time

of the most critical input pin on this gate By constraining the delta delay changed by moving cells

to be less than the delta arrival time on each pin, it guarantees that the final arrival time at timing endpoints would not degrade It also models slew and load capacitance constraints Experimental results [60] show that Hippocrates helps improve wirelength and timing significantly, in particular

on TNS, while conventional detailed placement algorithms fail to maintain the original timing

21.6.3 ACCURATENET-MODELINGISSUE

While most timing driven placers assume simple net models, some use specialized net models for timing critical nets, e.g., during global placement [61] or detailed placement [21] The first, [61], based on force-directed global placement [35], proposes a more accurate tree net model to replace the ubiquitous clique/star net models normally used in quadratic placers A Steiner tree net model is constructed and the length of each tree segment is controlled by weighting the individual segments

to improve timing This new model does not increase numerical complexity This net model is not specific to the force-directed formulation and could be used in other QP-based placers To determine the weight of each Steiner segment, the segment sensitivity is computed by determining the net delay derivative with respect to the segment length In this way, the segments that produce the most slack improvement are shortened the most

Another work [21] proposes simultaneous detailed placement and routing to optimize timing The algorithm is stable and incremental, and it reduces WNS by 9–14 percent, although the runtime

is quite high It begins with a placed and global-routed netlist and optimizes the k most critical

paths using a nonconvex mathematical programming model that optimizes slack while capturing the timing impact of cell movements and Steiner point changes of the global route In this approach, cell movements may change the Steiner tree topology Within the solving steps, each net is analyzed to ensure that its Steiner tree is correct, otherwise a new topology is generated Because routing changes are modeled, this is a more accurate net model than those commonly used net models discussed in previous sections

21.7 CONCLUSIONS

Although TDP has been studied extensively in the past two decades, the problem is still far away from being solved [62] Many challenges still remain due to the ever-growing problem size and complexity On the one hand, modern system-on-chip designs have millions of placeable cells and hundreds/thousands of macros [63]; on the other hand, stringent timing requirements and physical effects pose increasing challenges to the timing closure where TDP plays a key role

It shall be noted that to achieve the overall timing closure, TDP needs to work closely with synthesis/optimization tools (such as buffer insertion and gate sizing) and routing (in particular global routing) The entire physical design/synthesis closure is an extremely complex task Furthermore, modern complex SOC designs usually have multiple clock domains, or even multiple cycle paths, which make the TDP problem even more complicated Because of the infrastructure limitation, the academia has not been able to fully push the state of the art and limits of TDP With the availability

of OpenAccess [64] and the OpenAccess gear timer [65,66], it is possible to push the frontier of the very successful International Symposium on Physical Design (ISPD) placement contest [63] for university researchers to work on more realistic timing objectives As technology scales into sub100

nm regimes, new physical and manufacturing effects, in particular leakage/power and variations, have to be considered together with timing closure during TDP [67,68], which requires continuous innovations for better quality and productivity

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22 Congestion-Driven

Physical Design

Saurabh N Adya and Xiaojian Yang

CONTENTS

22.1 Introduction 447

22.2 Netlist-Connectivity-Based Approaches 448

22.2.1 Metrics for Structural Logic Synthesis 448

22.2.2 Congestion-Aware Logic Synthesis 449

22.2.3 Perimeter-Degree: A Priori Interconnection Complexity Metric 450

22.3 Global-Placement Congestion Improvement 452

22.3.1 Incorporating Congestion Estimation during Global Placement 452

22.3.2 Steiner Wirelength Optimization during Global Placement 454

22.3.3 Free Space Management during Global Placement 455

22.4 Detailed Placement Congestion Improvement 456

22.4.1 Router Integration 458

22.4.2 Whitespace Management 458

22.5 Simulated Annealing for Congestion Improvement 461

22.5.1 RISA 461

22.5.2 Overflow with Look-Ahead 462

22.5.3 A-Tree Router 463

22.5.4 Sparse Parameter 463

22.6 Conclusion 464

References 464

22.1 INTRODUCTION

This chapter discusses the impact and optimization of placement on the routing stage This is com-monly referred as congestion-driven placement Although a placer that produces unroutable designs will be of little use, historically optimization to directly reduce routing congestion has received less attention than wirelength and timing optimization Often placement papers fail to report any infor-mation on congestion and routability Over the last decade, with design sizes increasing dramatically and limited number of metal layers available for routing of signals and power, routability has become

a paramount issue This has driven the recent research interest in placement techniques to mitigate congestion while optimizing other placement objectives

Congestion-driven placement techniques can be classified into the following groups: netlist-connectivity-based methods, pin-density-based methods, and routing-estimation-based methods Netlist-connectivity-based methods use a priori information about the netlist characteristics to influ-ence the placement process Pin-density-based methods seek to limit the average pin density in local regions to indirectly address the routability concerns Routing-estimation-based methods are frequently used during and after the placement process when sufficient routing congestion informa-tion is available Global routers or probabilistic route estimators are often used to drive the various

447

congestion mitigation techniques Other notable techniques for addressing congestion in the design process include congestion-driven logic synthesis and global-placement density control Several of these techniques are applied separately during global placement and detail placement, the details

of each approach change according to the specific context Often a placement flow will employ one

or several of these methods

22.2 NETLIST-CONNECTIVITY-BASED APPROACHES

Recent advances in placement technology have attempted to alleviate the problem of wiring con-gestion during very large scale integration (VLSI) chip design Classically, placement algorithms find the optimal location of the logic without attempting to change the structure of the logic netlist itself However, the inherent structure of the logic netlist has a significant impact on the routabil-ity, irrespective of the placement algorithm used With the advent of physical synthesis techniques, there have been several attempts to combine placement transformations of the netlist in conjunction with logic synthesis transforms Such efforts [14,15,31] have concentrated mainly in improving the delay or area characteristics of the final implementation of the design Significant decisions regard-ing the circuit structure are made early in the synthesis stages such as register transfer level (RTL) decomposition, technology-independent logic optimization, technology mapping, etc For deep sub-micron (DSM) technologies, the wiring capacitance dominates the gate capacitance and the delay estimation based on fanout, and design legacy statistics (wireload tables) can be highly inaccurate

In addition, logic block size is no longer dictated solely by total cell area, and is often limited by routing resources For these reasons, wiring congestion is an extremely important design metric and should be taken into consideration at the earliest possible stage of the design flow In physical design, the required routing resources are captured in terms of routing congestion Placement or routing can sometimes fix, or avoid, potential congestion problems However, the netlist structure determined during logic synthesis may mean that it is too late in the flow to target congestion problems In the following subsections, we detail several recent approaches to target placement congestion by netlist transformations during the logic synthesis stage or by using inherent netlist properties to influence congestion-driven placement

22.2.1 METRICS FORSTRUCTURALLOGICSYNTHESIS

The work in Ref [26] motivates that a property of the network structure called adhesion can make a significant contribution to routing congestion The work targets the technology-independent logic optimization stage Classically, in this stage, literal count is used as a metric for optimiza-tion However, this does not adequately capture the intrinsic entanglement of the netlist Two circuits with identical literal counts may have significantly different congestion characteristics post-placement It is shown that by optimizing the adhesion metric in addition to literal count during technology-independent optimization, postrouting congestion can be improved

The adhesion metric of a logic network is defined as follows:

Definition 1 The adhesion of a logic network represented by an undirected graph G(V,E) can be

measured by the minimum number of edges between all pairs s, t ∈ V that if removed from the graph would disconnect the graph.

For measuring connectivity in a technology-independent netlist, the authors propose use of the all-pairs minimum-cut problem to determine the minimum cutsize of all pairs of nodes of a graph The metric used to describe adhesion of a graph is sum of all-pairs mincut (SAPMC) The following lemma is hence proposed

Lemma 1 The adhesion in an undirected graph representing a logic network as given by

Definition 1, can be measured by the SAPMC for the graph.

The authors propose the following conjectures to apply the property of adhesion during logic synthesis optimization This conjecture is then evaluated empirically

Conjecture 1 Networks with lower adhesion value will on the average have better routability

postplacement.

Conjecture 2 Using adhesion during logic synthesis transformations will result on the average in

better routability postplacement.

As an example of adhesion, the authors give the example in Figure 22.1 Figure 22.1a is an unoptimized network Two possible optimizations are applied to the original unoptimized network

to obtain two implementations, opt 1 in Figure 22.1b and opt 2 in Figure 22.1c The opt1 circuit has a SAPMC cost of 173, while the opt2 optimized circuit has a SAPMC cost of 152 According

to Conjecture 2, opt 2 is a better optimization for the same connection cost of 18 for the two implementations

The authors perform extensive experiments to validate their conjecture that optimizing the adhe-sion metric during logic synthesis does indeed reduce congestion postplacement of the mapped netlist First, they show a strong corelation between SAPMC metric and postplacement congestion

by changing the fast extraction, f x, logic synthesis transform to randomly select an improvement rather than operate in a greedy fashion Such choices to optimize adhesion as a metric could also be made during other logic synthesis optimizations like cloning, buffer insertion, rewiring, and factor-ization The results show a correlation of adhesion as measured by SAPMC to average, and maximum wirelength Adhesion can be used in conjunction with traditional properties like literal count, number

of cells, and cell count as logic synthesis metrics

22.2.2 CONGESTION-AWARELOGICSYNTHESIS

The work by Pandini et al [31] proposes several techniques to incorporate congestion minimiza-tion within logic synthesis Modern logic synthesis systems are typically divided into two phases: technology-independent optimization and technology mapping The first phase is concerned with finding a representation of the Boolean equations with the minimum number of literals in the factored form Technology mapping is the task of transforming a technology-independent logic network into

a technology-dependent gate-level netlist A popular approach to technology mapping implemented

in DAGON [12] and MIS [24] is to reduce the problem to directed acyclic graph (DAG) covering problem The DAG covering problem was approximated by a sequence of tree coverings, which can be solved optimally using dynamic programming The technology mapping is usually divided into three stages: DAG partitioning, matching, and covering During DAG partitioning, the network DAG is partitioned into a forest of trees Subsequently, for each tree, a matching algorithm identifies

(a) Original circuit (b) Optimized circuit 1: opt1 (c) Optimized circuit 2: opt 2

h g

+

*

*

*

*

c * b

f e

~b ~d

~c

h g

+

*

*

*

*

~b ~c

h g

+

*

*

*

*

~b ~c

FIGURE 22.1 Example of adhesion in a logic network (From Kudva, P and Dougherty, A., ICCAD, 2002.)

Technology independent optimization Logic synthesis

Technology mapping

Global placement and congestion map

Initial placement

Technology independent netlist

High level description

Routing Placement

YES

NO

Is congestion OK?

FIGURE 22.2 Application specific integrated circuit (ASIC) design flow to account for congestion in logic

synthesis (From Pandini, D., Pileggi, L T., and Strojwas, A J., DATE, 2002.)

all possible matches, corresponding to instances of a cell library, for each subnetwork Finally, an optimal choice according to a cost factor is selected among the matches The work in Ref [31] targets the DAG partitioning and covers steps to improve congestion of the final implementation

The proposed approach in Ref [31] for congestion-aware technology mapping can be integrated into traditional ASIC design flow, as shown in Figure 22.2 A technology-independent netlist and its initial placement is obtained If congestion is deemed as a problem for the netlist, technology mapping is carried out in a congestion-aware manner as explained below

Placement-driven DAG partitioning algorithm proposed in Ref [31] is shown in Figure 22.3 and is based on depth-first search (DFS) traversal from the circuit primary outputs to the primary inputs The difference from classical DAG partitioning is that partitioning at multifanout vertices is carried out by taking into account the physical location of the corresponding base gates obtained from placement of the technology-independent netlist The partitioning is based on the following property: the father of every internal vertex is always the nearest vertex on the chip layout image according

to some distance metric The function distance() uses the placement information to compute the geometric distance between two adjacent vertices The performance of the partitioning algorithm

is not dependent on the order the DAG roots are processed, but it depends only on the physical locations of the technology-independent gates Also, subject trees that cluster vertices placed in the same neighborhood are obtained by means of this DAG partitioning algorithm

For the tree-covering stage of the DAG covering problem, the authors propose only a change

in the cost function to the original tree-covering algorithm proposed in Ref [24] The optimization objective is expanded by including the wirelength contribution into the cost function

22.2.3 PERIMETER-DEGREE:A PRIORIINTERCONNECTIONCOMPLEXITYMETRIC

Several of the popular congestion mitigation techniques can be classified as a priori congestion tech-niques (preplacement), online methods (during placement), and posteriori methods (postplacement) Most of existing congestion minimization techniques are posteriori The work in Ref [34] present several techniques for a priori congestion minimization using the concept of perimeter-degree They show that the number of external nets is not a desirable candidate for identifying potential regions

of high-interconnect density Alternatively, they propose perimeter-degree as an effective metric for

for _each v inDAG do

v.father=nil;

od;

for _each v in DAG.roots()do

PDP(DAG, v, COORD);

od;

v.visited =true;

for _each e in DAG.outedges(v) do

if (not w.visited) then

for _each f in DAG.inedges(w) do

this_dist=distance(COORD[u], COORD[w]);

if(this_dist<dist) then

dist=this_dist;

w.father=u;

fi;

od;

PDP(DAG, w, COORD);

fi;

od;

FIGURE 22.3 Placement-driven DAG partitioning algorithm PDP stands for placement-driven partitioning.

(From Pandini, D., Pileggi, L T., and Strojwas, A J., DATE, 2002.)

identifying congested regions on a chip perimeter-degree(Pperi) is defined as follows A region

represents a placement bin on the die or a cluster of cells The degree of a region is the number of nets exposed from the region The perimeter-degree of the region is the region degree divided by the region perimeter The bin degree and pin density are two common metrics used for simple congestion control [44] However, it is misleading to compare just degrees of two regions with dissimilar area The degree needs to be normalized Because the degree of a region represents the routing demand

at the edges of a region, it is natural to use the perimeter of the region as the normalizing factor Figure 22.4 shows how two regions with the same degree can have different perimeter degrees Naturally, region A would have a higher routing supply demand compared to region B

The authors of Ref [34] detail simple ways to incorporate the perimeter-degree objective in a multilevel partitioning-based placement tool The first is to use the perimeter-degree at every cell to compute the cell inflation before placement starts The rational is to inflate cells with higher perime-ter degree before the clusperime-tering phase of multilevel placement This has the effect of diluting the inherently high-density portions of the netlist There are different thresholds for higher utilization designs compared to lower utilization designs The second technique is to inflate the clusters formed during the clustering stage with respect to their perimeter-degree This is done to prevent dense

FIGURE 22.4 Equal degree but different perimeter-degree (From Selvakkumaran, N., Parakh, P., and,

Karypis, G., SLIP, 2003.)